src/mesa/drivers/dri/i965/gen7_hs_state.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28 #include "main/shaderapi.h"
  29
  30 static void
  31 gen7_upload_tcs_push_constants(struct brw_context *brw)
  32 {
  33    struct brw_stage_state *stage_state = &brw->tcs.base;
  34    /* BRW_NEW_TESS_PROGRAMS */
  35    const struct brw_program *tcp = brw_program_const(brw->tess_ctrl_program);
  36    bool active = brw->tess_eval_program;
  37
  38    if (active) {
  39       /* BRW_NEW_TCS_PROG_DATA */
  40       const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
  41
  42       _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
  43       gen6_upload_push_constants(brw, &tcp->program, prog_data, stage_state,
  44                                  AUB_TRACE_VS_CONSTANTS);
  45    }
  46
  47    gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_HS);
  48 }
  49
  50 const struct brw_tracked_state gen7_tcs_push_constants = {
  51    .dirty = {
  52       .mesa  = _NEW_PROGRAM_CONSTANTS,
  53       .brw   = BRW_NEW_BATCH |
  54                BRW_NEW_BLORP |
  55                BRW_NEW_DEFAULT_TESS_LEVELS |
  56                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
  57                BRW_NEW_TESS_PROGRAMS |
  58                BRW_NEW_TCS_PROG_DATA,
  59    },
  60    .emit = gen7_upload_tcs_push_constants,
  61 };
  62
  63 static void
  64 gen7_upload_hs_state(struct brw_context *brw)
  65 {
  66    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  67    const struct brw_stage_state *stage_state = &brw->tcs.base;
  68    /* BRW_NEW_TESS_PROGRAMS */
  69    bool active = brw->tess_eval_program;
  70    /* BRW_NEW_TCS_PROG_DATA */
  71    const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
  72    const struct brw_tcs_prog_data *tcs_prog_data =
  73       brw_tcs_prog_data(stage_state->prog_data);
  74
  75    if (active) {
  76       BEGIN_BATCH(7);
  77       OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
  78       OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
  79                           GEN7_HS_SAMPLER_COUNT) |
  80                 SET_FIELD(prog_data->binding_table.size_bytes / 4,
  81                           GEN7_HS_BINDING_TABLE_ENTRY_COUNT) |
  82                 (devinfo->max_tcs_threads - 1));
  83       OUT_BATCH(GEN7_HS_ENABLE |
  84                 GEN7_HS_STATISTICS_ENABLE |
  85                 SET_FIELD(tcs_prog_data->instances - 1,
  86                           GEN7_HS_INSTANCE_COUNT));
  87       OUT_BATCH(stage_state->prog_offset);
  88       if (prog_data->total_scratch) {
  89          OUT_RELOC(stage_state->scratch_bo,
  90                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  91                    ffs(stage_state->per_thread_scratch) - 11);
  92       } else {
  93          OUT_BATCH(0);
  94       }
  95       OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
  96                 SET_FIELD(prog_data->dispatch_grf_start_reg,
  97                           GEN7_HS_DISPATCH_START_GRF));
  98       /* Ignore URB semaphores */
  99       OUT_BATCH(0);
 100       ADVANCE_BATCH();
 101    } else {
 102       BEGIN_BATCH(7);
 103       OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 104       OUT_BATCH(0);
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       ADVANCE_BATCH();
 111    }
 112    brw->tcs.enabled = active;
 113 }
 114
 115 const struct brw_tracked_state gen7_hs_state = {
 116    .dirty = {
 117       .mesa  = 0,
 118       .brw   = BRW_NEW_BATCH |
 119                BRW_NEW_BLORP |
 120                BRW_NEW_TCS_PROG_DATA |
 121                BRW_NEW_TESS_PROGRAMS,
 122    },
 123    .emit = gen7_upload_hs_state,
 124 };