src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/program.h"
  31 #include "program/prog_parameter.h"
  32 #include "program/prog_statevars.h"
  33 #include "intel_batchbuffer.h"
  34
  35 static void
  36 upload_wm_state(struct brw_context *brw)
  37 {
  38    struct gl_context *ctx = &brw->ctx;
  39    /* BRW_NEW_FRAGMENT_PROGRAM */
  40    const struct brw_fragment_program *fp =
  41       brw_fragment_program_const(brw->fragment_program);
  42    /* BRW_NEW_FS_PROG_DATA */
  43    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  44    bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
  45    uint32_t dw1, dw2;
  46
  47    /* _NEW_BUFFERS */
  48    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
  49
  50    dw1 = dw2 = 0;
  51    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  52    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  53    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  54
  55    /* _NEW_LINE */
  56    if (ctx->Line.StippleFlag)
  57       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  58
  59    /* _NEW_POLYGON */
  60    if (ctx->Polygon.StippleFlag)
  61       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  62
  63    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  64       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  65
  66    dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
  67    dw1 |= prog_data->barycentric_interp_modes <<
  68       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  69
  70    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  71    /* Enable if the pixel shader kernel generates and outputs oMask.
  72     */
  73    if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
  74        ctx->Multisample.SampleAlphaToCoverage ||
  75        prog_data->uses_omask) {
  76       dw1 |= GEN7_WM_KILL_ENABLE;
  77    }
  78
  79    /* _NEW_BUFFERS | _NEW_COLOR */
  80    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  81        dw1 & GEN7_WM_KILL_ENABLE) {
  82       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  83    }
  84    if (multisampled_fbo) {
  85       /* _NEW_MULTISAMPLE */
  86       if (ctx->Multisample.Enabled)
  87          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  88       else
  89          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  90
  91       if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false) > 1)
  92          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  93       else
  94          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
  95    } else {
  96       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  97       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  98    }
  99
 100    if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
 101       dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
 102    }
 103
 104    BEGIN_BATCH(3);
 105    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 106    OUT_BATCH(dw1);
 107    OUT_BATCH(dw2);
 108    ADVANCE_BATCH();
 109 }
 110
 111 const struct brw_tracked_state gen7_wm_state = {
 112    .dirty = {
 113       .mesa  = _NEW_BUFFERS |
 114                _NEW_COLOR |
 115                _NEW_LINE |
 116                _NEW_MULTISAMPLE |
 117                _NEW_POLYGON,
 118       .brw   = BRW_NEW_BATCH |
 119                BRW_NEW_FRAGMENT_PROGRAM |
 120                BRW_NEW_FS_PROG_DATA,
 121    },
 122    .emit = upload_wm_state,
 123 };
 124
 125 static void
 126 upload_ps_state(struct brw_context *brw)
 127 {
 128    struct gl_context *ctx = &brw->ctx;
 129    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 130    const int max_threads_shift = brw->is_haswell ?
 131       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 132
 133    /* BRW_NEW_FS_PROG_DATA */
 134    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 135
 136    dw2 = dw4 = dw5 = ksp2 = 0;
 137
 138    dw2 |=
 139       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 140
 141    dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
 142            GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 143
 144    if (prog_data->base.use_alt_mode)
 145       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 146
 147    /* Haswell requires the sample mask to be set in this packet as well as
 148     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 149    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 150    if (brw->is_haswell)
 151       dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
 152
 153    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 154
 155    if (prog_data->base.nr_params > 0)
 156       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 157
 158    /* From the IVB PRM, volume 2 part 1, page 287:
 159     * "This bit is inserted in the PS payload header and made available to
 160     * the DataPort (either via the message header or via header bypass) to
 161     * indicate that oMask data (one or two phases) is included in Render
 162     * Target Write messages. If present, the oMask data is used to mask off
 163     * samples."
 164     */
 165    if (prog_data->uses_omask)
 166       dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
 167
 168    /* From the IVB PRM, volume 2 part 1, page 287:
 169     * "If the PS kernel does not need the Position XY Offsets to
 170     * compute a Position Value, then this field should be programmed
 171     * to POSOFFSET_NONE."
 172     * "SW Recommendation: If the PS kernel needs the Position Offsets
 173     * to compute a Position XY value, this field should match Position
 174     * ZW Interpolation Mode to ensure a consistent position.xyzw
 175     * computation."
 176     * We only require XY sample offsets. So, this recommendation doesn't
 177     * look useful at the moment. We might need this in future.
 178     */
 179    if (prog_data->uses_pos_offset)
 180       dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
 181    else
 182       dw4 |= GEN7_PS_POSOFFSET_NONE;
 183
 184    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
 185     *
 186     * The hardware wedges if you have this bit set but don't turn on any dual
 187     * source blend factors.
 188     */
 189    if (prog_data->dual_src_blend &&
 190        (ctx->Color.BlendEnabled & 1) &&
 191        ctx->Color.Blend[0]._UsesDualSrc) {
 192       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 193    }
 194
 195    /* BRW_NEW_FS_PROG_DATA */
 196    if (prog_data->num_varying_inputs != 0)
 197       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 198
 199    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 200     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 201     * is successfully compiled. In majority of the cases that bring us
 202     * better performance than 'SIMD8 only' dispatch.
 203     */
 204    int min_inv_per_frag =
 205       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
 206    assert(min_inv_per_frag >= 1);
 207
 208    if (prog_data->prog_offset_16 || prog_data->no_8) {
 209       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 210       if (!prog_data->no_8 && min_inv_per_frag == 1) {
 211          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 212          dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 213                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 214          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 215                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 216          ksp0 = brw->wm.base.prog_offset;
 217          ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
 218       } else {
 219          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 220                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 221          ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
 222       }
 223    }
 224    else {
 225       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 226       dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 227               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 228       ksp0 = brw->wm.base.prog_offset;
 229    }
 230
 231    dw4 |= brw->wm.fast_clear_op;
 232
 233    BEGIN_BATCH(8);
 234    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 235    OUT_BATCH(ksp0);
 236    OUT_BATCH(dw2);
 237    if (prog_data->base.total_scratch) {
 238       OUT_RELOC(brw->wm.base.scratch_bo,
 239                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 240                 ffs(prog_data->base.total_scratch) - 11);
 241    } else {
 242       OUT_BATCH(0);
 243    }
 244    OUT_BATCH(dw4);
 245    OUT_BATCH(dw5);
 246    OUT_BATCH(0); /* kernel 1 pointer */
 247    OUT_BATCH(ksp2);
 248    ADVANCE_BATCH();
 249 }
 250
 251 const struct brw_tracked_state gen7_ps_state = {
 252    .dirty = {
 253       .mesa  = _NEW_BUFFERS |
 254                _NEW_COLOR |
 255                _NEW_MULTISAMPLE,
 256       .brw   = BRW_NEW_BATCH |
 257                BRW_NEW_FRAGMENT_PROGRAM |
 258                BRW_NEW_FS_PROG_DATA,
 259    },
 260    .emit = upload_ps_state,
 261 };