src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 upload_wm_state(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41    bool writes_depth = false;
  42    uint32_t dw1;
  43
  44    /* _NEW_LIGHT */
  45    bool flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
  46
  47    dw1 = 0;
  48    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  49    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  50    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  51
  52    /* _NEW_LINE */
  53    if (ctx->Line.StippleFlag)
  54       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  55
  56    /* _NEW_POLYGON */
  57    if (ctx->Polygon.StippleFlag)
  58       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  59
  60    /* BRW_NEW_FRAGMENT_PROGRAM */
  61    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
  62       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  63    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  64       writes_depth = true;
  65       dw1 |= GEN7_WM_PSCDEPTH_ON;
  66    }
  67    dw1 |= brw_compute_barycentric_interp_modes(flat_shade, &fp->program) <<
  68       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  69
  70    /* _NEW_COLOR */
  71    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
  72       dw1 |= GEN7_WM_KILL_ENABLE;
  73
  74    /* _NEW_BUFFERS */
  75    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  76        dw1 & GEN7_WM_KILL_ENABLE) {
  77       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  78    }
  79
  80    BEGIN_BATCH(3);
  81    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
  82    OUT_BATCH(dw1);
  83    OUT_BATCH(0);
  84    ADVANCE_BATCH();
  85 }
  86
  87 const struct brw_tracked_state gen7_wm_state = {
  88    .dirty = {
  89       .mesa  = (_NEW_LINE | _NEW_LIGHT | _NEW_POLYGON |
  90                 _NEW_COLOR | _NEW_BUFFERS),
  91       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
  92                 BRW_NEW_BATCH),
  93       .cache = 0,
  94    },
  95    .emit = upload_wm_state,
  96 };
  97
  98 static void
  99 upload_ps_state(struct brw_context *brw)
 100 {
 101    struct intel_context *intel = &brw->intel;
 102    uint32_t dw2, dw4, dw5;
 103
 104    BEGIN_BATCH(2);
 105    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 106    OUT_BATCH(brw->bind.bo_offset);
 107    ADVANCE_BATCH();
 108
 109    /* CACHE_NEW_SAMPLER */
 110    BEGIN_BATCH(2);
 111    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 112    OUT_BATCH(brw->sampler.offset);
 113    ADVANCE_BATCH();
 114
 115    /* CACHE_NEW_WM_PROG */
 116    if (brw->wm.prog_data->nr_params == 0) {
 117       /* Disable the push constant buffers. */
 118       BEGIN_BATCH(7);
 119       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 120       OUT_BATCH(0);
 121       OUT_BATCH(0);
 122       OUT_BATCH(0);
 123       OUT_BATCH(0);
 124       OUT_BATCH(0);
 125       OUT_BATCH(0);
 126       ADVANCE_BATCH();
 127    } else {
 128       BEGIN_BATCH(7);
 129       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 130
 131       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 132                       brw->wm.prog_data->dispatch_width) / 8);
 133       OUT_BATCH(0);
 134       /* Pointer to the WM constant buffer.  Covered by the set of
 135        * state flags from gen7_prepare_wm_constants
 136        */
 137       OUT_BATCH(brw->wm.push_const_offset);
 138       OUT_BATCH(0);
 139       OUT_BATCH(0);
 140       OUT_BATCH(0);
 141       ADVANCE_BATCH();
 142    }
 143
 144    dw2 = dw4 = dw5 = 0;
 145
 146    dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 147
 148    /* Use ALT floating point mode for ARB fragment programs, because they
 149     * require 0^0 == 1.
 150     */
 151    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
 152       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 153
 154    /* CACHE_NEW_SAMPLER */
 155    dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
 156
 157    /* CACHE_NEW_WM_PROG */
 158    if (brw->wm.prog_data->nr_params > 0)
 159       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 160
 161    /* BRW_NEW_FRAGMENT_PROGRAM */
 162    if (brw->fragment_program->Base.InputsRead != 0)
 163       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 164
 165    if (brw->wm.prog_data->dispatch_width == 8) {
 166       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 167       if (brw->wm.prog_data->prog_offset_16)
 168          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 169    } else {
 170       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 171    }
 172
 173    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 174            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 175    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 176            GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 177
 178    BEGIN_BATCH(8);
 179    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 180    OUT_BATCH(brw->wm.prog_offset);
 181    OUT_BATCH(dw2);
 182    if (brw->wm.prog_data->total_scratch) {
 183       OUT_RELOC(brw->wm.scratch_bo,
 184                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 185                 ffs(brw->wm.prog_data->total_scratch) - 11);
 186    } else {
 187       OUT_BATCH(0);
 188    }
 189    OUT_BATCH(dw4);
 190    OUT_BATCH(dw5);
 191    OUT_BATCH(0); /* kernel 1 pointer */
 192    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 193    ADVANCE_BATCH();
 194 }
 195
 196 const struct brw_tracked_state gen7_ps_state = {
 197    .dirty = {
 198       .mesa  = _NEW_PROGRAM_CONSTANTS,
 199       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 200                 BRW_NEW_PS_BINDING_TABLE |
 201                 BRW_NEW_BATCH),
 202       .cache = (CACHE_NEW_SAMPLER |
 203                 CACHE_NEW_WM_PROG)
 204    },
 205    .emit = upload_ps_state,
 206 };