2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "intel_batchbuffer.h"
30 upload_ps_extra(struct brw_context
*brw
)
32 /* BRW_NEW_FRAGMENT_PROGRAM */
33 const struct brw_fragment_program
*fp
=
34 brw_fragment_program_const(brw
->fragment_program
);
37 dw1
|= GEN8_PSX_PIXEL_SHADER_VALID
;
39 if (fp
->program
.UsesKill
)
40 dw1
|= GEN8_PSX_KILL_ENABLE
;
42 /* BRW_NEW_FRAGMENT_PROGRAM */
43 if (brw
->wm
.prog_data
->num_varying_inputs
!= 0)
44 dw1
|= GEN8_PSX_ATTRIBUTE_ENABLE
;
46 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
47 switch (fp
->program
.FragDepthLayout
) {
48 case FRAG_DEPTH_LAYOUT_NONE
:
49 case FRAG_DEPTH_LAYOUT_ANY
:
50 dw1
|= GEN8_PSX_PSCDEPTH_ON
;
52 case FRAG_DEPTH_LAYOUT_GREATER
:
53 dw1
|= GEN8_PSX_PSCDEPTH_ON_GE
;
55 case FRAG_DEPTH_LAYOUT_LESS
:
56 dw1
|= GEN8_PSX_PSCDEPTH_ON_LE
;
58 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
63 if (fp
->program
.Base
.InputsRead
& VARYING_BIT_POS
)
64 dw1
|= GEN8_PSX_USES_SOURCE_DEPTH
| GEN8_PSX_USES_SOURCE_W
;
67 OUT_BATCH(_3DSTATE_PS_EXTRA
<< 16 | (2 - 2));
72 const struct brw_tracked_state gen8_ps_extra
= {
75 .brw
= BRW_NEW_CONTEXT
| BRW_NEW_FRAGMENT_PROGRAM
,
78 .emit
= upload_ps_extra
,
82 upload_wm_state(struct brw_context
*brw
)
84 struct gl_context
*ctx
= &brw
->ctx
;
87 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
88 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
89 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
90 dw1
|= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT
;
93 if (ctx
->Line
.StippleFlag
)
94 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
97 if (ctx
->Polygon
.StippleFlag
)
98 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
100 /* CACHE_NEW_WM_PROG */
101 dw1
|= brw
->wm
.prog_data
->barycentric_interp_modes
<<
102 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
105 OUT_BATCH(_3DSTATE_WM
<< 16 | (2 - 2));
110 const struct brw_tracked_state gen8_wm_state
= {
112 .mesa
= _NEW_LINE
| _NEW_POLYGON
,
113 .brw
= BRW_NEW_CONTEXT
,
114 .cache
= CACHE_NEW_WM_PROG
,
116 .emit
= upload_wm_state
,
120 upload_ps_state(struct brw_context
*brw
)
122 struct gl_context
*ctx
= &brw
->ctx
;
123 uint32_t dw3
= 0, dw6
= 0, dw7
= 0;
125 /* BRW_NEW_PS_BINDING_TABLE */
127 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS
<< 16 | (2 - 2));
128 OUT_BATCH(brw
->wm
.base
.bind_bo_offset
);
131 /* CACHE_NEW_SAMPLER */
133 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS
<< 16 | (2 - 2));
134 OUT_BATCH(brw
->wm
.base
.sampler_offset
);
137 /* CACHE_NEW_WM_PROG */
138 gen8_upload_constant_state(brw
, &brw
->wm
.base
, true, _3DSTATE_CONSTANT_PS
);
140 /* Initialize the execution mask with VMask. Otherwise, derivatives are
141 * incorrect for subspans where some of the pixels are unlit. We believe
142 * the bit just didn't take effect in previous generations.
144 dw3
|= GEN7_PS_VECTOR_MASK_ENABLE
;
146 /* CACHE_NEW_SAMPLER */
148 (ALIGN(brw
->wm
.base
.sampler_count
, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT
;
150 /* CACHE_NEW_WM_PROG */
152 ((brw
->wm
.prog_data
->base
.binding_table
.size_bytes
/ 4) <<
153 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
155 /* Use ALT floating point mode for ARB fragment programs, because they
156 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
157 * rendering, CurrentFragmentProgram is used for this check to
158 * differentiate between the GLSL and non-GLSL cases.
160 if (ctx
->Shader
.CurrentProgram
[MESA_SHADER_FRAGMENT
] == NULL
)
161 dw3
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
163 dw6
|= (brw
->max_wm_threads
- 2) << HSW_PS_MAX_THREADS_SHIFT
;
165 /* CACHE_NEW_WM_PROG */
166 if (brw
->wm
.prog_data
->base
.nr_params
> 0)
167 dw6
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
169 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
170 if (brw
->wm
.prog_data
->prog_offset_16
)
171 dw6
|= GEN7_PS_16_DISPATCH_ENABLE
;
174 brw
->wm
.prog_data
->first_curbe_grf
<< GEN7_PS_DISPATCH_START_GRF_SHIFT_0
|
175 brw
->wm
.prog_data
->first_curbe_grf_16
<< GEN7_PS_DISPATCH_START_GRF_SHIFT_2
;
178 OUT_BATCH(_3DSTATE_PS
<< 16 | (12 - 2));
179 OUT_BATCH(brw
->wm
.base
.prog_offset
);
182 if (brw
->wm
.prog_data
->total_scratch
) {
183 OUT_RELOC64(brw
->wm
.base
.scratch_bo
,
184 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
185 ffs(brw
->wm
.prog_data
->total_scratch
) - 11);
192 OUT_BATCH(0); /* kernel 1 pointer */
194 OUT_BATCH(brw
->wm
.base
.prog_offset
+ brw
->wm
.prog_data
->prog_offset_16
);
199 const struct brw_tracked_state gen8_ps_state
= {
201 .mesa
= _NEW_PROGRAM_CONSTANTS
,
202 .brw
= BRW_NEW_FRAGMENT_PROGRAM
|
203 BRW_NEW_PS_BINDING_TABLE
|
205 BRW_NEW_PUSH_CONSTANT_ALLOCATION
,
206 .cache
= CACHE_NEW_SAMPLER
| CACHE_NEW_WM_PROG
208 .emit
= upload_ps_state
,