1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "intel_fbo.h"
34 #include "brw_context.h"
37 intel_batchbuffer_reset(struct brw_context
*brw
);
40 intel_batchbuffer_init(struct brw_context
*brw
)
42 intel_batchbuffer_reset(brw
);
45 /* We can't just use brw_state_batch to get a chunk of space for
46 * the gen6 workaround because it involves actually writing to
47 * the buffer, and the kernel doesn't let us write to the batch.
49 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
50 "pipe_control workaround",
54 brw
->batch
.need_workaround_flush
= true;
57 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
58 brw
->batch
.map
= brw
->batch
.cpu_map
;
63 intel_batchbuffer_reset(struct brw_context
*brw
)
65 if (brw
->batch
.last_bo
!= NULL
) {
66 drm_intel_bo_unreference(brw
->batch
.last_bo
);
67 brw
->batch
.last_bo
= NULL
;
69 brw
->batch
.last_bo
= brw
->batch
.bo
;
71 brw_render_cache_set_clear(brw
);
73 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
76 drm_intel_bo_map(brw
->batch
.bo
, true);
77 brw
->batch
.map
= brw
->batch
.bo
->virtual;
80 brw
->batch
.reserved_space
= BATCH_RESERVED
;
81 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
83 brw
->batch
.needs_sol_reset
= false;
85 /* We don't know what ring the new batch will be sent to until we see the
86 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
88 brw
->batch
.ring
= UNKNOWN_RING
;
92 intel_batchbuffer_save_state(struct brw_context
*brw
)
94 brw
->batch
.saved
.used
= brw
->batch
.used
;
95 brw
->batch
.saved
.reloc_count
=
96 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
100 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
102 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
104 brw
->batch
.used
= brw
->batch
.saved
.used
;
105 if (brw
->batch
.used
== 0)
106 brw
->batch
.ring
= UNKNOWN_RING
;
110 intel_batchbuffer_free(struct brw_context
*brw
)
112 free(brw
->batch
.cpu_map
);
113 drm_intel_bo_unreference(brw
->batch
.last_bo
);
114 drm_intel_bo_unreference(brw
->batch
.bo
);
115 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
119 do_batch_dump(struct brw_context
*brw
)
121 struct drm_intel_decode
*decode
;
122 struct intel_batchbuffer
*batch
= &brw
->batch
;
125 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
129 ret
= drm_intel_bo_map(batch
->bo
, false);
131 drm_intel_decode_set_batch_pointer(decode
,
137 "WARNING: failed to map batchbuffer (%s), "
138 "dumping uploaded data instead.\n", strerror(ret
));
140 drm_intel_decode_set_batch_pointer(decode
,
146 drm_intel_decode_set_output_file(decode
, stderr
);
147 drm_intel_decode(decode
);
149 drm_intel_decode_context_free(decode
);
152 drm_intel_bo_unmap(batch
->bo
);
154 brw_debug_batch(brw
);
159 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
161 /* We may need to enable and snapshot OA counters. */
162 brw_perf_monitor_new_batch(brw
);
166 * Called when starting a new batch buffer.
169 brw_new_batch(struct brw_context
*brw
)
171 /* Create a new batchbuffer and reset the associated state: */
172 intel_batchbuffer_reset(brw
);
174 /* If the kernel supports hardware contexts, then most hardware state is
175 * preserved between batches; we only need to re-emit state that is required
176 * to be in every batch. Otherwise we need to re-emit all the state that
177 * would otherwise be stored in the context (which for all intents and
178 * purposes means everything).
180 if (brw
->hw_ctx
== NULL
)
181 SET_DIRTY_BIT(brw
, BRW_NEW_CONTEXT
);
183 SET_DIRTY_BIT(brw
, BRW_NEW_BATCH
);
185 /* Assume that the last command before the start of our batch was a
186 * primitive, for safety.
188 brw
->batch
.need_workaround_flush
= true;
190 brw
->state_batch_count
= 0;
194 /* We need to periodically reap the shader time results, because rollover
195 * happens every few seconds. We also want to see results every once in a
196 * while, because many programs won't cleanly destroy our context, so the
197 * end-of-run printout may not happen.
199 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
200 brw_collect_and_report_shader_time(brw
);
202 if (INTEL_DEBUG
& DEBUG_PERFMON
)
203 brw_dump_perf_monitors(brw
);
207 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
210 * This function can emit state (say, to preserve registers that aren't saved
211 * between batches). All of this state MUST fit in the reserved space at the
212 * end of the batchbuffer. If you add more GPU state, increase the reserved
213 * space by updating the BATCH_RESERVED macro.
216 brw_finish_batch(struct brw_context
*brw
)
218 /* Capture the closing pipeline statistics register values necessary to
219 * support query objects (in the non-hardware context world).
221 brw_emit_query_end(brw
);
223 /* We may also need to snapshot and disable OA counters. */
224 if (brw
->batch
.ring
== RENDER_RING
)
225 brw_perf_monitor_finish_batch(brw
);
227 /* Mark that the current program cache BO has been used by the GPU.
228 * It will be reallocated if we need to put new programs in for the
231 brw
->cache
.bo_used_by_gpu
= true;
234 /* TODO: Push this whole function into bufmgr.
237 do_flush_locked(struct brw_context
*brw
)
239 struct intel_batchbuffer
*batch
= &brw
->batch
;
243 drm_intel_bo_unmap(batch
->bo
);
245 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
246 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
247 ret
= drm_intel_bo_subdata(batch
->bo
,
248 batch
->state_batch_offset
,
249 batch
->bo
->size
- batch
->state_batch_offset
,
250 (char *)batch
->map
+ batch
->state_batch_offset
);
254 if (!brw
->intelScreen
->no_hw
) {
257 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
258 flags
= I915_EXEC_BLT
;
260 flags
= I915_EXEC_RENDER
;
262 if (batch
->needs_sol_reset
)
263 flags
|= I915_EXEC_GEN7_SOL_RESET
;
266 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
267 brw_annotate_aub(brw
);
268 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
269 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
272 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
273 4 * batch
->used
, flags
);
278 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
282 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
290 _intel_batchbuffer_flush(struct brw_context
*brw
,
291 const char *file
, int line
)
295 if (brw
->batch
.used
== 0)
298 if (brw
->first_post_swapbuffers_batch
== NULL
) {
299 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
300 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
303 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
304 int bytes_for_commands
= 4 * brw
->batch
.used
;
305 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
306 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
307 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
308 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
309 bytes_for_commands
, bytes_for_state
,
311 100.0f
* total_bytes
/ BATCH_SZ
);
314 brw
->batch
.reserved_space
= 0;
316 brw_finish_batch(brw
);
318 /* Mark the end of the buffer. */
319 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
320 if (brw
->batch
.used
& 1) {
321 /* Round batchbuffer usage to 2 DWORDs. */
322 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
325 intel_upload_finish(brw
);
327 /* Check that we didn't just wrap our batchbuffer at a bad time. */
328 assert(!brw
->no_batch_wrap
);
330 ret
= do_flush_locked(brw
);
332 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
333 fprintf(stderr
, "waiting for idle\n");
334 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
337 /* Start a new batch buffer. */
344 /* This is the only way buffers get added to the validate list.
347 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
348 drm_intel_bo
*buffer
,
349 uint32_t read_domains
, uint32_t write_domain
,
354 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
356 read_domains
, write_domain
);
361 * Using the old buffer offset, write in what the right data would be, in case
362 * the buffer doesn't move and we can short-circuit the relocation processing
365 intel_batchbuffer_emit_dword(brw
, buffer
->offset64
+ delta
);
371 intel_batchbuffer_emit_reloc64(struct brw_context
*brw
,
372 drm_intel_bo
*buffer
,
373 uint32_t read_domains
, uint32_t write_domain
,
376 int ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
378 read_domains
, write_domain
);
382 /* Using the old buffer offset, write in what the right data would be, in
383 * case the buffer doesn't move and we can short-circuit the relocation
384 * processing in the kernel
386 uint64_t offset
= buffer
->offset64
+ delta
;
387 intel_batchbuffer_emit_dword(brw
, offset
);
388 intel_batchbuffer_emit_dword(brw
, offset
>> 32);
395 intel_batchbuffer_data(struct brw_context
*brw
,
396 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
398 assert((bytes
& 3) == 0);
399 intel_batchbuffer_require_space(brw
, bytes
, ring
);
400 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
401 brw
->batch
.used
+= bytes
>> 2;
405 * According to the latest documentation, any PIPE_CONTROL with the
406 * "Command Streamer Stall" bit set must also have another bit set,
407 * with five different options:
409 * - Render Target Cache Flush
410 * - Depth Cache Flush
411 * - Stall at Pixel Scoreboard
412 * - Post-Sync Operation
415 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
416 * in the past, but the choice is fairly arbitrary.
419 gen8_add_cs_stall_workaround_bits(uint32_t *flags
)
421 uint32_t wa_bits
= PIPE_CONTROL_WRITE_FLUSH
|
422 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
423 PIPE_CONTROL_WRITE_IMMEDIATE
|
424 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
425 PIPE_CONTROL_WRITE_TIMESTAMP
|
426 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
427 PIPE_CONTROL_DEPTH_STALL
;
429 /* If we're doing a CS stall, and don't already have one of the
430 * workaround bits set, add "Stall at Pixel Scoreboard."
432 if ((*flags
& PIPE_CONTROL_CS_STALL
) != 0 && (*flags
& wa_bits
) == 0)
433 *flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
437 * Emit a PIPE_CONTROL with various flushing flags.
439 * The caller is responsible for deciding what flags are appropriate for the
443 brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
)
446 gen8_add_cs_stall_workaround_bits(&flags
);
449 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
456 } else if (brw
->gen
>= 6) {
458 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
466 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
475 * Emit a PIPE_CONTROL that writes to a buffer object.
477 * \p flags should contain one of the following items:
478 * - PIPE_CONTROL_WRITE_IMMEDIATE
479 * - PIPE_CONTROL_WRITE_TIMESTAMP
480 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
483 brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
484 drm_intel_bo
*bo
, uint32_t offset
,
485 uint32_t imm_lower
, uint32_t imm_upper
)
488 gen8_add_cs_stall_workaround_bits(&flags
);
491 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
493 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
495 OUT_BATCH(imm_lower
);
496 OUT_BATCH(imm_upper
);
498 } else if (brw
->gen
>= 6) {
499 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
500 * on later platforms. We always use PPGTT on Gen7+.
502 unsigned gen6_gtt
= brw
->gen
== 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE
: 0;
505 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
507 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
509 OUT_BATCH(imm_lower
);
510 OUT_BATCH(imm_upper
);
514 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
515 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
516 PIPE_CONTROL_GLOBAL_GTT_WRITE
| offset
);
517 OUT_BATCH(imm_lower
);
518 OUT_BATCH(imm_upper
);
524 * Restriction [DevSNB, DevIVB]:
526 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
527 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
528 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
529 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
530 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
531 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
532 * unless SW can otherwise guarantee that the pipeline from WM onwards is
533 * already flushed (e.g., via a preceding MI_FLUSH).
536 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
538 assert(brw
->gen
>= 6 && brw
->gen
<= 8);
540 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
541 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
542 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
546 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
547 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
548 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
549 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
550 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
551 * to be sent before any combination of VS associated 3DSTATE."
554 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
556 assert(brw
->gen
== 7);
557 brw_emit_pipe_control_write(brw
,
558 PIPE_CONTROL_WRITE_IMMEDIATE
559 | PIPE_CONTROL_DEPTH_STALL
,
560 brw
->batch
.workaround_bo
, 0,
566 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
569 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
571 brw_emit_pipe_control_write(brw
,
572 PIPE_CONTROL_CS_STALL
573 | PIPE_CONTROL_WRITE_IMMEDIATE
,
574 brw
->batch
.workaround_bo
, 0,
580 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
581 * implementing two workarounds on gen6. From section 1.4.7.1
582 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
584 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
585 * produced by non-pipelined state commands), software needs to first
586 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
589 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
590 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
592 * And the workaround for these two requires this workaround first:
594 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
595 * BEFORE the pipe-control with a post-sync op and no write-cache
598 * And this last workaround is tricky because of the requirements on
599 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
602 * "1 of the following must also be set:
603 * - Render Target Cache Flush Enable ([12] of DW1)
604 * - Depth Cache Flush Enable ([0] of DW1)
605 * - Stall at Pixel Scoreboard ([1] of DW1)
606 * - Depth Stall ([13] of DW1)
607 * - Post-Sync Operation ([13] of DW1)
608 * - Notify Enable ([8] of DW1)"
610 * The cache flushes require the workaround flush that triggered this
611 * one, so we can't use it. Depth stall would trigger the same.
612 * Post-sync nonzero is what triggered this second workaround, so we
613 * can't use that one either. Notify enable is IRQs, which aren't
614 * really our business. That leaves only stall at scoreboard.
617 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
619 if (!brw
->batch
.need_workaround_flush
)
622 brw_emit_pipe_control_flush(brw
,
623 PIPE_CONTROL_CS_STALL
|
624 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
626 brw_emit_pipe_control_write(brw
, PIPE_CONTROL_WRITE_IMMEDIATE
,
627 brw
->batch
.workaround_bo
, 0, 0, 0);
629 brw
->batch
.need_workaround_flush
= false;
632 /* Emit a pipelined flush to either flush render and texture cache for
633 * reading from a FBO-drawn texture, or flush so that frontbuffer
634 * render appears on the screen in DRI1.
636 * This is also used for the always_flush_cache driconf debug option.
639 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
641 if (brw
->batch
.ring
== BLT_RING
&& brw
->gen
>= 6) {
643 OUT_BATCH(MI_FLUSH_DW
);
649 int flags
= PIPE_CONTROL_NO_WRITE
| PIPE_CONTROL_WRITE_FLUSH
;
651 flags
|= PIPE_CONTROL_INSTRUCTION_FLUSH
|
652 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
653 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
654 PIPE_CONTROL_TC_FLUSH
|
655 PIPE_CONTROL_CS_STALL
;
658 /* Hardware workaround: SNB B-Spec says:
660 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
661 * Flush Enable =1, a PIPE_CONTROL with any non-zero
662 * post-sync-op is required.
664 intel_emit_post_sync_nonzero_flush(brw
);
667 brw_emit_pipe_control_flush(brw
, flags
);
670 brw_render_cache_set_clear(brw
);
674 brw_load_register_mem(struct brw_context
*brw
,
677 uint32_t read_domains
, uint32_t write_domain
,
680 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
681 assert(brw
->gen
>= 7);
685 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
687 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
);
691 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
693 OUT_RELOC(bo
, read_domains
, write_domain
, offset
);