2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/colormac.h"
31 #include "main/fbobject.h"
33 #include "brw_context.h"
34 #include "brw_defines.h"
35 #include "intel_blit.h"
36 #include "intel_buffers.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_mipmap_tree.h"
42 #define FILE_DEBUG_FLAG DEBUG_BLIT
44 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
48 CMD |= type ## _TILED_X; \
51 if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
52 CMD |= type ## _TILED_64K; \
54 CMD |= type ## _TILED_Y; \
57 unreachable("not reached"); \
62 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
63 struct intel_mipmap_tree
*mt
,
64 int x
, int y
, int width
, int height
);
66 static GLuint
translate_raster_op(GLenum logicop
)
69 case GL_CLEAR
: return 0x00;
70 case GL_AND
: return 0x88;
71 case GL_AND_REVERSE
: return 0x44;
72 case GL_COPY
: return 0xCC;
73 case GL_AND_INVERTED
: return 0x22;
74 case GL_NOOP
: return 0xAA;
75 case GL_XOR
: return 0x66;
76 case GL_OR
: return 0xEE;
77 case GL_NOR
: return 0x11;
78 case GL_EQUIV
: return 0x99;
79 case GL_INVERT
: return 0x55;
80 case GL_OR_REVERSE
: return 0xDD;
81 case GL_COPY_INVERTED
: return 0x33;
82 case GL_OR_INVERTED
: return 0xBB;
83 case GL_NAND
: return 0x77;
84 case GL_SET
: return 0xFF;
104 unreachable("not reached");
109 get_tr_horizontal_align(uint32_t tr_mode
, uint32_t cpp
, bool is_src
) {
110 /* Alignment tables for YF/YS tiled surfaces. */
111 const uint32_t align_2d_yf
[] = {64, 64, 32, 32, 16};
112 const uint32_t bpp
= cpp
* 8;
113 const uint32_t shift
= is_src
? 17 : 10;
117 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
120 /* Compute array index. */
121 assert (bpp
>= 8 && bpp
<= 128 && _mesa_is_pow_two(bpp
));
122 i
= ffs(bpp
/ 8) - 1;
124 align
= tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
128 assert(_mesa_is_pow_two(align
));
130 /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
134 return (ffs(align
) - 6) << shift
;
138 get_tr_vertical_align(uint32_t tr_mode
, uint32_t cpp
, bool is_src
) {
139 /* Vertical alignment tables for YF/YS tiled surfaces. */
140 const unsigned align_2d_yf
[] = {64, 32, 32, 16, 16};
141 const uint32_t bpp
= cpp
* 8;
142 const uint32_t shift
= is_src
? 15 : 8;
146 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
149 /* Compute array index. */
150 assert (bpp
>= 8 && bpp
<= 128 && _mesa_is_pow_two(bpp
));
151 i
= ffs(bpp
/ 8) - 1;
153 align
= tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
157 assert(_mesa_is_pow_two(align
));
159 /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
160 if (align
== 16 || align
== 32)
163 return (ffs(align
) - 7) << shift
;
167 * Emits the packet for switching the blitter from X to Y tiled or back.
169 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
170 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
171 * part of the power context, not a render context, and if the batchbuffer was
172 * to get flushed between setting and blitting, or blitting and restoring, our
173 * tiling state would leak into other unsuspecting applications (like the X
177 set_blitter_tiling(struct brw_context
*brw
,
178 bool dst_y_tiled
, bool src_y_tiled
,
181 assert(brw
->gen
>= 6);
183 /* Idle the blitter before we update how tiling is interpreted. */
184 OUT_BATCH(MI_FLUSH_DW
);
189 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
190 OUT_BATCH(BCS_SWCTRL
);
191 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
192 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
193 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
196 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
198 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
199 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
200 if (dst_y_tiled || src_y_tiled) \
201 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
203 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
204 if (dst_y_tiled || src_y_tiled) \
205 SET_BLITTER_TILING(brw, false, false); \
209 blt_pitch(struct intel_mipmap_tree
*mt
)
211 int pitch
= mt
->pitch
;
218 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
220 /* The BLT doesn't handle sRGB conversion */
221 assert(src
== _mesa_get_srgb_format_linear(src
));
222 assert(dst
== _mesa_get_srgb_format_linear(dst
));
224 /* No swizzle or format conversions possible, except... */
228 /* ...we can either discard the alpha channel when going from A->X,
229 * or we can fill the alpha channel with 0xff when going from X->A
231 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
232 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
233 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
235 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
236 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
237 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
243 * Implements a rectangular block transfer (blit) of pixels between two
246 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
247 * but limited, pitches and sizes allowed.
249 * The src/dst coordinates are relative to the given level/slice of the
252 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
253 * will be inverted (including scanline order) when copying. This is common
254 * in GL when copying between window system and user-created
255 * renderbuffers/textures.
258 intel_miptree_blit(struct brw_context
*brw
,
259 struct intel_mipmap_tree
*src_mt
,
260 int src_level
, int src_slice
,
261 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
262 struct intel_mipmap_tree
*dst_mt
,
263 int dst_level
, int dst_slice
,
264 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
265 uint32_t width
, uint32_t height
,
268 /* The blitter doesn't understand multisampling at all. */
269 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
272 /* No sRGB decode or encode is done by the hardware blitter, which is
273 * consistent with what we want in the callers (glCopyTexSubImage(),
274 * glBlitFramebuffer(), texture validation, etc.).
276 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
277 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
279 /* The blitter doesn't support doing any format conversions. We do also
280 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
281 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
282 * channel to 1.0 at the end.
284 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
285 perf_debug("%s: Can't use hardware blitter from %s to %s, "
286 "falling back.\n", __func__
,
287 _mesa_get_format_name(src_format
),
288 _mesa_get_format_name(dst_format
));
292 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
293 * Data Size Limitations):
295 * The BLT engine is capable of transferring very large quantities of
296 * graphics data. Any graphics data read from and written to the
297 * destination is permitted to represent a number of pixels that
298 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
299 * at the destination. The maximum number of pixels that may be
300 * represented per scan line’s worth of graphics data depends on the
303 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
304 * 16-bit integer to represent buffer pitch, so it can only handle buffer
305 * pitches < 32k. However, the pitch is measured in bytes for linear buffers
306 * and dwords for tiled buffers.
308 * As a result of these two limitations, we can only use the blitter to do
309 * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
311 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
312 perf_debug("Falling back due to >= 32k/128k pitch\n");
316 /* The blitter has no idea about HiZ or fast color clears, so we need to
317 * resolve the miptrees before we do anything.
319 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
320 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
321 intel_miptree_resolve_color(brw
, src_mt
);
322 intel_miptree_resolve_color(brw
, dst_mt
);
325 src_y
= minify(src_mt
->physical_height0
, src_level
- src_mt
->first_level
) - src_y
- height
;
328 dst_y
= minify(dst_mt
->physical_height0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
330 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
331 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
332 &src_image_x
, &src_image_y
);
333 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
334 &dst_image_x
, &dst_image_y
);
335 src_x
+= src_image_x
;
336 src_y
+= src_image_y
;
337 dst_x
+= dst_image_x
;
338 dst_y
+= dst_image_y
;
340 /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
341 * value. The values we're working with are unsigned, so make sure we don't
344 if (src_x
>= 32768 || src_y
>= 32768 || dst_x
>= 32768 || dst_y
>= 32768) {
345 perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
346 src_x
, src_y
, dst_x
, dst_y
);
350 if (!intelEmitCopyBlit(brw
,
352 src_flip
== dst_flip
? src_mt
->pitch
: -src_mt
->pitch
,
353 src_mt
->bo
, src_mt
->offset
,
357 dst_mt
->bo
, dst_mt
->offset
,
367 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
368 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
369 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
370 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
379 alignment_valid(struct brw_context
*brw
, unsigned offset
, uint32_t tiling
)
381 /* Tiled buffers must be page-aligned (4K). */
382 if (tiling
!= I915_TILING_NONE
)
383 return (offset
& 4095) == 0;
385 /* On Gen8+, linear buffers must be cacheline-aligned. */
387 return (offset
& 63) == 0;
393 can_fast_copy_blit(struct brw_context
*brw
,
394 drm_intel_bo
*src_buffer
,
395 int16_t src_x
, int16_t src_y
,
396 uintptr_t src_offset
, uint32_t src_pitch
,
397 uint32_t src_tiling
, uint32_t src_tr_mode
,
398 drm_intel_bo
*dst_buffer
,
399 int16_t dst_x
, int16_t dst_y
,
400 uintptr_t dst_offset
, uint32_t dst_pitch
,
401 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
402 int16_t w
, int16_t h
, uint32_t cpp
)
404 const bool dst_tiling_none
= dst_tiling
== I915_TILING_NONE
;
405 const bool src_tiling_none
= src_tiling
== I915_TILING_NONE
;
410 if (src_buffer
->handle
== dst_buffer
->handle
&&
411 _mesa_regions_overlap(src_x
, src_y
, src_x
+ w
, src_y
+ h
,
412 dst_x
, dst_y
, dst_x
+ w
, dst_y
+ h
))
415 /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
416 * FIXME: Based on performance data, remove this condition later to
417 * enable for all types of surfaces.
419 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
420 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
423 /* For all surface types buffers must be cacheline-aligned. */
424 if ((dst_offset
| src_offset
) & 63)
427 /* Color depth greater than 128 bits not supported. */
431 /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
432 * of the destination pitch must be zero.
434 if ((src_pitch
>> 15 & 1) != 0 || (dst_pitch
>> 15 & 1) != 0)
437 /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
438 if ((src_tiling_none
&& src_pitch
% 16 != 0) ||
439 (dst_tiling_none
&& dst_pitch
% 16 != 0))
446 xy_blit_cmd(uint32_t src_tiling
, uint32_t src_tr_mode
,
447 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
448 uint32_t cpp
, bool use_fast_copy_blit
)
452 if (use_fast_copy_blit
) {
453 CMD
= XY_FAST_COPY_BLT_CMD
;
455 if (dst_tiling
!= I915_TILING_NONE
)
456 SET_TILING_XY_FAST_COPY_BLT(dst_tiling
, dst_tr_mode
, XY_FAST_DST
);
458 if (src_tiling
!= I915_TILING_NONE
)
459 SET_TILING_XY_FAST_COPY_BLT(src_tiling
, src_tr_mode
, XY_FAST_SRC
);
461 CMD
|= get_tr_horizontal_align(src_tr_mode
, cpp
, true /* is_src */);
462 CMD
|= get_tr_vertical_align(src_tr_mode
, cpp
, true /* is_src */);
464 CMD
|= get_tr_horizontal_align(dst_tr_mode
, cpp
, false /* is_src */);
465 CMD
|= get_tr_vertical_align(dst_tr_mode
, cpp
, false /* is_src */);
472 CMD
= XY_SRC_COPY_BLT_CMD
;
475 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
478 unreachable("not reached");
481 if (dst_tiling
!= I915_TILING_NONE
)
484 if (src_tiling
!= I915_TILING_NONE
)
493 intelEmitCopyBlit(struct brw_context
*brw
,
496 drm_intel_bo
*src_buffer
,
499 uint32_t src_tr_mode
,
501 drm_intel_bo
*dst_buffer
,
504 uint32_t dst_tr_mode
,
505 GLshort src_x
, GLshort src_y
,
506 GLshort dst_x
, GLshort dst_y
,
507 GLshort w
, GLshort h
,
510 GLuint CMD
, BR13
, pass
= 0;
511 int dst_y2
= dst_y
+ h
;
512 int dst_x2
= dst_x
+ w
;
513 drm_intel_bo
*aper_array
[3];
514 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
515 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
516 bool use_fast_copy_blit
= false;
517 uint32_t src_tile_w
, src_tile_h
;
518 uint32_t dst_tile_w
, dst_tile_h
;
520 if ((dst_y_tiled
|| src_y_tiled
) && brw
->gen
< 6)
523 /* do space check before going any further */
525 aper_array
[0] = brw
->batch
.bo
;
526 aper_array
[1] = dst_buffer
;
527 aper_array
[2] = src_buffer
;
529 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
530 intel_batchbuffer_flush(brw
);
539 unsigned length
= brw
->gen
>= 8 ? 10 : 8;
541 intel_batchbuffer_require_space(brw
, length
* 4, BLT_RING
);
542 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
544 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
545 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
547 intel_get_tile_dims(src_tiling
, src_tr_mode
, cpp
, &src_tile_w
, &src_tile_h
);
548 intel_get_tile_dims(dst_tiling
, dst_tr_mode
, cpp
, &dst_tile_w
, &dst_tile_h
);
550 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
551 * (X direction width of the Tile). This is ensured while allocating the
554 assert(src_tiling
== I915_TILING_NONE
|| (src_pitch
% src_tile_w
) == 0);
555 assert(dst_tiling
== I915_TILING_NONE
|| (dst_pitch
% dst_tile_w
) == 0);
557 use_fast_copy_blit
= can_fast_copy_blit(brw
,
560 src_offset
, src_pitch
,
561 src_tiling
, src_tr_mode
,
564 dst_offset
, dst_pitch
,
565 dst_tiling
, dst_tr_mode
,
567 assert(use_fast_copy_blit
||
568 (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
569 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
));
571 if (use_fast_copy_blit
) {
572 /* When two sequential fast copy blits have different source surfaces,
573 * but their destinations refer to the same destination surfaces and
574 * therefore destinations overlap it is imperative that a flush be
575 * inserted between the two blits.
577 * FIXME: Figure out a way to avoid flushing when not required.
579 brw_emit_mi_flush(brw
);
582 BR13
= br13_for_cpp(cpp
);
584 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
585 BR13
|= XY_FAST_SRC_TRMODE_YF
;
587 if (dst_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
588 BR13
|= XY_FAST_DST_TRMODE_YF
;
590 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
591 dst_tiling
, dst_tr_mode
,
592 cpp
, use_fast_copy_blit
);
595 /* For big formats (such as floating point), do the copy using 16 or
596 * 32bpp and multiply the coordinates.
605 assert(cpp
% 4 == 0);
613 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
615 if (!alignment_valid(brw
, src_offset
, src_tiling
))
618 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
619 * the low bits. Offsets must be naturally aligned.
621 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
622 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
626 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
628 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
629 dst_tiling
, dst_tr_mode
,
630 cpp
, use_fast_copy_blit
);
633 /* For tiled source and destination, pitch value should be specified
634 * as a number of Dwords.
636 if (dst_tiling
!= I915_TILING_NONE
)
639 if (src_tiling
!= I915_TILING_NONE
)
642 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
)
645 assert(dst_x
< dst_x2
);
646 assert(dst_y
< dst_y2
);
647 assert(src_offset
+ (src_y
+ h
- 1) * abs(src_pitch
) +
648 (w
* cpp
) <= src_buffer
->size
);
649 assert(dst_offset
+ (dst_y
+ h
- 1) * abs(dst_pitch
) +
650 (w
* cpp
) <= dst_buffer
->size
);
652 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
653 OUT_BATCH(CMD
| (length
- 2));
654 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
655 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
656 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
658 OUT_RELOC64(dst_buffer
,
659 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
662 OUT_RELOC(dst_buffer
,
663 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
666 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
667 OUT_BATCH((uint16_t)src_pitch
);
669 OUT_RELOC64(src_buffer
,
670 I915_GEM_DOMAIN_RENDER
, 0,
673 OUT_RELOC(src_buffer
,
674 I915_GEM_DOMAIN_RENDER
, 0,
678 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
680 brw_emit_mi_flush(brw
);
686 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
688 GLubyte
*src_bits
, GLuint src_size
,
691 drm_intel_bo
*dst_buffer
,
694 GLshort x
, GLshort y
,
695 GLshort w
, GLshort h
,
698 int dwords
= ALIGN(src_size
, 8) / 4;
699 uint32_t opcode
, br13
, blit_cmd
;
701 if (dst_tiling
!= I915_TILING_NONE
) {
702 if (dst_offset
& 4095)
704 if (dst_tiling
== I915_TILING_Y
)
708 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
709 assert(dst_pitch
> 0);
714 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
716 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
718 unsigned xy_setup_blt_length
= brw
->gen
>= 8 ? 10 : 8;
719 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
720 (3 * 4) + dwords
* 4, BLT_RING
);
722 opcode
= XY_SETUP_BLT_CMD
;
724 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
725 if (dst_tiling
!= I915_TILING_NONE
) {
726 opcode
|= XY_DST_TILED
;
730 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
731 br13
|= br13_for_cpp(cpp
);
733 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
734 if (dst_tiling
!= I915_TILING_NONE
)
735 blit_cmd
|= XY_DST_TILED
;
737 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
738 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
740 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
741 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
743 OUT_RELOC64(dst_buffer
,
744 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
747 OUT_RELOC(dst_buffer
,
748 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
751 OUT_BATCH(0); /* bg */
752 OUT_BATCH(fg_color
); /* fg */
753 OUT_BATCH(0); /* pattern base addr */
757 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
758 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
759 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
762 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4, BLT_RING
);
764 brw_emit_mi_flush(brw
);
769 /* We don't have a memmove-type blit like some other hardware, so we'll do a
770 * rectangular blit covering a large space, then emit 1-scanline blit at the
771 * end to cover the last if we need.
774 intel_emit_linear_blit(struct brw_context
*brw
,
775 drm_intel_bo
*dst_bo
,
776 unsigned int dst_offset
,
777 drm_intel_bo
*src_bo
,
778 unsigned int src_offset
,
781 struct gl_context
*ctx
= &brw
->ctx
;
782 GLuint pitch
, height
;
783 int16_t src_x
, dst_x
;
787 /* The pitch given to the GPU must be DWORD aligned, and
788 * we want width to match pitch. Max width is (1 << 15 - 1),
789 * rounding that down to the nearest DWORD is 1 << 15 - 4
791 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 64), 4);
792 height
= (size
< pitch
|| pitch
== 0) ? 1 : size
/ pitch
;
794 src_x
= src_offset
% 64;
795 dst_x
= dst_offset
% 64;
796 pitch
= ALIGN(MIN2(size
, (1 << 15) - 64), 4);
797 assert(src_x
+ pitch
< 1 << 15);
798 assert(dst_x
+ pitch
< 1 << 15);
800 ok
= intelEmitCopyBlit(brw
, 1,
801 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
802 INTEL_MIPTREE_TRMODE_NONE
,
803 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
804 INTEL_MIPTREE_TRMODE_NONE
,
805 src_x
, 0, /* src x/y */
806 dst_x
, 0, /* dst x/y */
807 MIN2(size
, pitch
), height
, /* w, h */
810 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n",
811 MIN2(size
, pitch
), height
);
826 * Used to initialize the alpha value of an ARGB8888 miptree after copying
827 * into it from an XRGB8888 source.
829 * This is very common with glCopyTexImage2D(). Note that the coordinates are
830 * relative to the start of the miptree, not relative to a slice within the
834 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
835 struct intel_mipmap_tree
*mt
,
836 int x
, int y
, int width
, int height
)
840 drm_intel_bo
*aper_array
[2];
845 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
846 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
848 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
849 CMD
= XY_COLOR_BLT_CMD
;
850 CMD
|= XY_BLT_WRITE_ALPHA
;
852 if (mt
->tiling
!= I915_TILING_NONE
) {
858 /* do space check before going any further */
859 aper_array
[0] = brw
->batch
.bo
;
860 aper_array
[1] = mt
->bo
;
862 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
863 ARRAY_SIZE(aper_array
)) != 0) {
864 intel_batchbuffer_flush(brw
);
867 unsigned length
= brw
->gen
>= 8 ? 7 : 6;
868 bool dst_y_tiled
= mt
->tiling
== I915_TILING_Y
;
870 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
871 OUT_BATCH(CMD
| (length
- 2));
873 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
874 OUT_BATCH(SET_FIELD(y
+ height
, BLT_Y
) | SET_FIELD(x
+ width
, BLT_X
));
877 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
881 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
884 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
885 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
887 brw_emit_mi_flush(brw
);