src/mesa/drivers/dri/i965/intel_blit.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/mtypes.h"
  27 #include "main/blit.h"
  28 #include "main/context.h"
  29 #include "main/enums.h"
  30 #include "main/colormac.h"
  31 #include "main/fbobject.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "intel_blit.h"
  36 #include "intel_buffers.h"
  37 #include "intel_fbo.h"
  38 #include "intel_reg.h"
  39 #include "intel_batchbuffer.h"
  40 #include "intel_mipmap_tree.h"
  41
  42 #define FILE_DEBUG_FLAG DEBUG_BLIT
  43
  44 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type)           \
  45 ({                                                                   \
  46    switch (tiling) {                                                 \
  47    case I915_TILING_X:                                               \
  48       CMD |= type ## _TILED_X;                                       \
  49       break;                                                         \
  50    case I915_TILING_Y:                                               \
  51       if (tr_mode == INTEL_MIPTREE_TRMODE_YS)                        \
  52          CMD |= type ## _TILED_64K;                                  \
  53       else                                                           \
  54          CMD |= type ## _TILED_Y;                                    \
  55       break;                                                         \
  56    default:                                                          \
  57       unreachable("not reached");                                    \
  58    }                                                                 \
  59 })
  60
  61 static void
  62 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  63                                struct intel_mipmap_tree *mt,
  64                                int x, int y, int width, int height);
  65
  66 static GLuint translate_raster_op(GLenum logicop)
  67 {
  68    switch(logicop) {
  69    case GL_CLEAR: return 0x00;
  70    case GL_AND: return 0x88;
  71    case GL_AND_REVERSE: return 0x44;
  72    case GL_COPY: return 0xCC;
  73    case GL_AND_INVERTED: return 0x22;
  74    case GL_NOOP: return 0xAA;
  75    case GL_XOR: return 0x66;
  76    case GL_OR: return 0xEE;
  77    case GL_NOR: return 0x11;
  78    case GL_EQUIV: return 0x99;
  79    case GL_INVERT: return 0x55;
  80    case GL_OR_REVERSE: return 0xDD;
  81    case GL_COPY_INVERTED: return 0x33;
  82    case GL_OR_INVERTED: return 0xBB;
  83    case GL_NAND: return 0x77;
  84    case GL_SET: return 0xFF;
  85    default: return 0;
  86    }
  87 }
  88
  89 static uint32_t
  90 br13_for_cpp(int cpp)
  91 {
  92    switch (cpp) {
  93    case 16:
  94       return BR13_32323232;
  95    case 8:
  96       return BR13_16161616;
  97    case 4:
  98       return BR13_8888;
  99    case 2:
 100       return BR13_565;
 101    case 1:
 102       return BR13_8;
 103    default:
 104       unreachable("not reached");
 105    }
 106 }
 107
 108 static uint32_t
 109 get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
 110    /* Alignment tables for YF/YS tiled surfaces. */
 111    const uint32_t align_2d_yf[] = {64, 64, 32, 32, 16};
 112    const uint32_t bpp = cpp * 8;
 113    const uint32_t shift = is_src ? 17 : 10;
 114    uint32_t align;
 115    int i = 0;
 116
 117    if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 118       return 0;
 119
 120    /* Compute array index. */
 121    assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
 122    i = ffs(bpp / 8) - 1;
 123
 124    align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
 125            align_2d_yf[i] :
 126            4 * align_2d_yf[i];
 127
 128    assert(_mesa_is_pow_two(align));
 129
 130    /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
 131    if (align == 16)
 132       align = 32;
 133
 134    return (ffs(align) - 6) << shift;
 135 }
 136
 137 static uint32_t
 138 get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
 139    /* Vertical alignment tables for YF/YS tiled surfaces. */
 140    const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
 141    const uint32_t bpp = cpp * 8;
 142    const uint32_t shift = is_src ? 15 : 8;
 143    uint32_t align;
 144    int i = 0;
 145
 146    if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 147       return 0;
 148
 149    /* Compute array index. */
 150    assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
 151    i = ffs(bpp / 8) - 1;
 152
 153    align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
 154            align_2d_yf[i] :
 155            4 * align_2d_yf[i];
 156
 157    assert(_mesa_is_pow_two(align));
 158
 159    /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
 160    if (align == 16 || align == 32)
 161       align = 64;
 162
 163    return (ffs(align) - 7) << shift;
 164 }
 165
 166 /**
 167  * Emits the packet for switching the blitter from X to Y tiled or back.
 168  *
 169  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
 170  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
 171  * part of the power context, not a render context, and if the batchbuffer was
 172  * to get flushed between setting and blitting, or blitting and restoring, our
 173  * tiling state would leak into other unsuspecting applications (like the X
 174  * server).
 175  */
 176 static uint32_t *
 177 set_blitter_tiling(struct brw_context *brw,
 178                    bool dst_y_tiled, bool src_y_tiled,
 179                    uint32_t *__map)
 180 {
 181    assert(brw->gen >= 6);
 182
 183    /* Idle the blitter before we update how tiling is interpreted. */
 184    OUT_BATCH(MI_FLUSH_DW);
 185    OUT_BATCH(0);
 186    OUT_BATCH(0);
 187    OUT_BATCH(0);
 188
 189    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 190    OUT_BATCH(BCS_SWCTRL);
 191    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 192              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 193              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 194    return __map;
 195 }
 196 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 197
 198 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)              \
 199       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 200       if (dst_y_tiled || src_y_tiled)                                   \
 201          SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 202
 203 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)                   \
 204       if (dst_y_tiled || src_y_tiled)                                   \
 205          SET_BLITTER_TILING(brw, false, false);                         \
 206       ADVANCE_BATCH()
 207
 208 static int
 209 blt_pitch(struct intel_mipmap_tree *mt)
 210 {
 211    int pitch = mt->pitch;
 212    if (mt->tiling)
 213       pitch /= 4;
 214    return pitch;
 215 }
 216
 217 bool
 218 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 219 {
 220    /* The BLT doesn't handle sRGB conversion */
 221    assert(src == _mesa_get_srgb_format_linear(src));
 222    assert(dst == _mesa_get_srgb_format_linear(dst));
 223
 224    /* No swizzle or format conversions possible, except... */
 225    if (src == dst)
 226       return true;
 227
 228    /* ...we can either discard the alpha channel when going from A->X,
 229     * or we can fill the alpha channel with 0xff when going from X->A
 230     */
 231    if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
 232       return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
 233               dst == MESA_FORMAT_B8G8R8X8_UNORM);
 234
 235    if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
 236       return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
 237               dst == MESA_FORMAT_R8G8B8X8_UNORM);
 238
 239    return false;
 240 }
 241
 242 /**
 243  * Implements a rectangular block transfer (blit) of pixels between two
 244  * miptrees.
 245  *
 246  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 247  * but limited, pitches and sizes allowed.
 248  *
 249  * The src/dst coordinates are relative to the given level/slice of the
 250  * miptree.
 251  *
 252  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 253  * will be inverted (including scanline order) when copying.  This is common
 254  * in GL when copying between window system and user-created
 255  * renderbuffers/textures.
 256  */
 257 bool
 258 intel_miptree_blit(struct brw_context *brw,
 259                    struct intel_mipmap_tree *src_mt,
 260                    int src_level, int src_slice,
 261                    uint32_t src_x, uint32_t src_y, bool src_flip,
 262                    struct intel_mipmap_tree *dst_mt,
 263                    int dst_level, int dst_slice,
 264                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 265                    uint32_t width, uint32_t height,
 266                    GLenum logicop)
 267 {
 268    /* The blitter doesn't understand multisampling at all. */
 269    if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
 270       return false;
 271
 272    /* No sRGB decode or encode is done by the hardware blitter, which is
 273     * consistent with what we want in the callers (glCopyTexSubImage(),
 274     * glBlitFramebuffer(), texture validation, etc.).
 275     */
 276    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 277    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 278
 279    /* The blitter doesn't support doing any format conversions.  We do also
 280     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 281     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 282     * channel to 1.0 at the end.
 283     */
 284    if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
 285       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 286                  "falling back.\n", __func__,
 287                  _mesa_get_format_name(src_format),
 288                  _mesa_get_format_name(dst_format));
 289       return false;
 290    }
 291
 292    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 293     * Data Size Limitations):
 294     *
 295     *    The BLT engine is capable of transferring very large quantities of
 296     *    graphics data. Any graphics data read from and written to the
 297     *    destination is permitted to represent a number of pixels that
 298     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 299     *    at the destination. The maximum number of pixels that may be
 300     *    represented per scan line’s worth of graphics data depends on the
 301     *    color depth.
 302     *
 303     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 304     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 305     * pitches < 32k. However, the pitch is measured in bytes for linear buffers
 306     * and dwords for tiled buffers.
 307     *
 308     * As a result of these two limitations, we can only use the blitter to do
 309     * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
 310     */
 311    if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
 312       perf_debug("Falling back due to >= 32k/128k pitch\n");
 313       return false;
 314    }
 315
 316    /* The blitter has no idea about HiZ or fast color clears, so we need to
 317     * resolve the miptrees before we do anything.
 318     */
 319    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 320    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 321    intel_miptree_resolve_color(brw, src_mt);
 322    intel_miptree_resolve_color(brw, dst_mt);
 323
 324    if (src_flip)
 325       src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
 326
 327    if (dst_flip)
 328       dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
 329
 330    int src_pitch = src_mt->pitch;
 331    if (src_flip != dst_flip)
 332       src_pitch = -src_pitch;
 333
 334    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
 335    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 336                                   &src_image_x, &src_image_y);
 337    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 338                                   &dst_image_x, &dst_image_y);
 339    src_x += src_image_x;
 340    src_y += src_image_y;
 341    dst_x += dst_image_x;
 342    dst_y += dst_image_y;
 343
 344    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 345     * value. The values we're working with are unsigned, so make sure we don't
 346     * overflow.
 347     */
 348    if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) {
 349       perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
 350                  src_x, src_y, dst_x, dst_y);
 351       return false;
 352    }
 353
 354    if (!intelEmitCopyBlit(brw,
 355                           src_mt->cpp,
 356                           src_pitch,
 357                           src_mt->bo, src_mt->offset,
 358                           src_mt->tiling,
 359                           src_mt->tr_mode,
 360                           dst_mt->pitch,
 361                           dst_mt->bo, dst_mt->offset,
 362                           dst_mt->tiling,
 363                           dst_mt->tr_mode,
 364                           src_x, src_y,
 365                           dst_x, dst_y,
 366                           width, height,
 367                           logicop)) {
 368       return false;
 369    }
 370
 371    /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
 372    if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
 373        _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
 374       intel_miptree_set_alpha_to_one(brw, dst_mt,
 375                                      dst_x, dst_y,
 376                                      width, height);
 377    }
 378
 379    return true;
 380 }
 381
 382 static bool
 383 alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
 384 {
 385    /* Tiled buffers must be page-aligned (4K). */
 386    if (tiling != I915_TILING_NONE)
 387       return (offset & 4095) == 0;
 388
 389    /* On Gen8+, linear buffers must be cacheline-aligned. */
 390    if (brw->gen >= 8)
 391       return (offset & 63) == 0;
 392
 393    return true;
 394 }
 395
 396 static bool
 397 can_fast_copy_blit(struct brw_context *brw,
 398                    drm_intel_bo *src_buffer,
 399                    int16_t src_x, int16_t src_y,
 400                    uintptr_t src_offset, uint32_t src_pitch,
 401                    uint32_t src_tiling, uint32_t src_tr_mode,
 402                    drm_intel_bo *dst_buffer,
 403                    int16_t dst_x, int16_t dst_y,
 404                    uintptr_t dst_offset, uint32_t dst_pitch,
 405                    uint32_t dst_tiling, uint32_t dst_tr_mode,
 406                    int16_t w, int16_t h, uint32_t cpp)
 407 {
 408    const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
 409    const bool src_tiling_none = src_tiling == I915_TILING_NONE;
 410
 411    if (brw->gen < 9)
 412       return false;
 413
 414    if (src_buffer->handle == dst_buffer->handle &&
 415        _mesa_regions_overlap(src_x, src_y, src_x + w, src_y + h,
 416                              dst_x, dst_y, dst_x + w, dst_y + h))
 417       return false;
 418
 419    /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
 420     * FIXME: Based on performance data, remove this condition later to
 421     * enable for all types of surfaces.
 422     */
 423    if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
 424        dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 425       return false;
 426
 427    /* For all surface types buffers must be cacheline-aligned. */
 428    if ((dst_offset | src_offset) & 63)
 429       return false;
 430
 431    /* Color depth greater than 128 bits not supported. */
 432    if (cpp > 16)
 433       return false;
 434
 435    /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
 436     * of the destination pitch must be zero.
 437     */
 438    if ((src_pitch >> 15 & 1) != 0 || (dst_pitch >> 15 & 1) != 0)
 439       return false;
 440
 441    /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
 442    if ((src_tiling_none && src_pitch % 16 != 0) ||
 443        (dst_tiling_none && dst_pitch % 16 != 0))
 444       return false;
 445
 446    /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
 447     * (X direction width of the Tile). This means the pitch value will
 448     * always be Cache Line aligned (64byte multiple).
 449     */
 450    if ((!dst_tiling_none && dst_pitch % 64 != 0) ||
 451        (!src_tiling_none && src_pitch % 64 != 0))
 452       return false;
 453
 454    return true;
 455 }
 456
 457 static uint32_t
 458 xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
 459             uint32_t dst_tiling, uint32_t dst_tr_mode,
 460             uint32_t cpp, bool use_fast_copy_blit)
 461 {
 462    uint32_t CMD = 0;
 463
 464    if (use_fast_copy_blit) {
 465       CMD = XY_FAST_COPY_BLT_CMD;
 466
 467       if (dst_tiling != I915_TILING_NONE)
 468          SET_TILING_XY_FAST_COPY_BLT(dst_tiling, dst_tr_mode, XY_FAST_DST);
 469
 470       if (src_tiling != I915_TILING_NONE)
 471          SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
 472
 473       CMD |= get_tr_horizontal_align(src_tr_mode, cpp, true /* is_src */);
 474       CMD |= get_tr_vertical_align(src_tr_mode, cpp, true /* is_src */);
 475
 476       CMD |= get_tr_horizontal_align(dst_tr_mode, cpp, false /* is_src */);
 477       CMD |= get_tr_vertical_align(dst_tr_mode, cpp, false /* is_src */);
 478
 479    } else {
 480       assert(cpp <= 4);
 481       switch (cpp) {
 482       case 1:
 483       case 2:
 484          CMD = XY_SRC_COPY_BLT_CMD;
 485          break;
 486       case 4:
 487          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 488          break;
 489       default:
 490          unreachable("not reached");
 491       }
 492
 493       if (dst_tiling != I915_TILING_NONE)
 494          CMD |= XY_DST_TILED;
 495
 496       if (src_tiling != I915_TILING_NONE)
 497          CMD |= XY_SRC_TILED;
 498    }
 499    return CMD;
 500 }
 501
 502 /* Copy BitBlt
 503  */
 504 bool
 505 intelEmitCopyBlit(struct brw_context *brw,
 506                   GLuint cpp,
 507                   GLshort src_pitch,
 508                   drm_intel_bo *src_buffer,
 509                   GLuint src_offset,
 510                   uint32_t src_tiling,
 511                   uint32_t src_tr_mode,
 512                   GLshort dst_pitch,
 513                   drm_intel_bo *dst_buffer,
 514                   GLuint dst_offset,
 515                   uint32_t dst_tiling,
 516                   uint32_t dst_tr_mode,
 517                   GLshort src_x, GLshort src_y,
 518                   GLshort dst_x, GLshort dst_y,
 519                   GLshort w, GLshort h,
 520                   GLenum logic_op)
 521 {
 522    GLuint CMD, BR13, pass = 0;
 523    int dst_y2 = dst_y + h;
 524    int dst_x2 = dst_x + w;
 525    drm_intel_bo *aper_array[3];
 526    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 527    bool src_y_tiled = src_tiling == I915_TILING_Y;
 528    bool use_fast_copy_blit = false;
 529
 530    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 531       return false;
 532
 533    /* do space check before going any further */
 534    do {
 535        aper_array[0] = brw->batch.bo;
 536        aper_array[1] = dst_buffer;
 537        aper_array[2] = src_buffer;
 538
 539        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 540            intel_batchbuffer_flush(brw);
 541            pass++;
 542        } else
 543            break;
 544    } while (pass < 2);
 545
 546    if (pass >= 2)
 547       return false;
 548
 549    unsigned length = brw->gen >= 8 ? 10 : 8;
 550
 551    intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
 552    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 553        __func__,
 554        src_buffer, src_pitch, src_offset, src_x, src_y,
 555        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 556
 557    use_fast_copy_blit = can_fast_copy_blit(brw,
 558                                            src_buffer,
 559                                            src_x, src_y,
 560                                            src_offset, src_pitch,
 561                                            src_tiling, src_tr_mode,
 562                                            dst_buffer,
 563                                            dst_x, dst_y,
 564                                            dst_offset, dst_pitch,
 565                                            dst_tiling, dst_tr_mode,
 566                                            w, h, cpp);
 567    assert(use_fast_copy_blit ||
 568           (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
 569            dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE));
 570
 571    if (use_fast_copy_blit) {
 572       /* When two sequential fast copy blits have different source surfaces,
 573        * but their destinations refer to the same destination surfaces and
 574        * therefore destinations overlap it is imperative that a flush be
 575        * inserted between the two blits.
 576        *
 577        * FIXME: Figure out a way to avoid flushing when not required.
 578        */
 579       brw_emit_mi_flush(brw);
 580
 581       assert(cpp <= 16);
 582       BR13 = br13_for_cpp(cpp);
 583
 584       if (src_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 585          BR13 |= XY_FAST_SRC_TRMODE_YF;
 586
 587       if (dst_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 588          BR13 |= XY_FAST_DST_TRMODE_YF;
 589
 590       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 591                         dst_tiling, dst_tr_mode,
 592                         cpp, use_fast_copy_blit);
 593
 594       /* For tiled source and destination, pitch value should be specified
 595        * as a number of Dwords.
 596        */
 597       if (dst_tiling != I915_TILING_NONE)
 598          dst_pitch /= 4;
 599
 600       if (src_tiling != I915_TILING_NONE)
 601          src_pitch /= 4;
 602
 603    } else {
 604       assert(!dst_y_tiled || (dst_pitch % 128) == 0);
 605       assert(!src_y_tiled || (src_pitch % 128) == 0);
 606
 607       /* For big formats (such as floating point), do the copy using 16 or
 608        * 32bpp and multiply the coordinates.
 609        */
 610       if (cpp > 4) {
 611          if (cpp % 4 == 2) {
 612             dst_x *= cpp / 2;
 613             dst_x2 *= cpp / 2;
 614             src_x *= cpp / 2;
 615             cpp = 2;
 616          } else {
 617             assert(cpp % 4 == 0);
 618             dst_x *= cpp / 4;
 619             dst_x2 *= cpp / 4;
 620             src_x *= cpp / 4;
 621             cpp = 4;
 622          }
 623       }
 624
 625       if (!alignment_valid(brw, dst_offset, dst_tiling))
 626          return false;
 627       if (!alignment_valid(brw, src_offset, src_tiling))
 628          return false;
 629
 630       /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 631        * the low bits.  Offsets must be naturally aligned.
 632        */
 633       if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 634           dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 635          return false;
 636
 637       assert(cpp <= 4);
 638       BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 639
 640       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 641                         dst_tiling, dst_tr_mode,
 642                         cpp, use_fast_copy_blit);
 643
 644       if (dst_tiling != I915_TILING_NONE)
 645          dst_pitch /= 4;
 646
 647       if (src_tiling != I915_TILING_NONE)
 648          src_pitch /= 4;
 649    }
 650
 651    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 652       return true;
 653    }
 654
 655    assert(dst_x < dst_x2);
 656    assert(dst_y < dst_y2);
 657    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 658           (w * cpp) <= src_buffer->size);
 659    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 660           (w * cpp) <= dst_buffer->size);
 661
 662    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 663    OUT_BATCH(CMD | (length - 2));
 664    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 665    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 666    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 667    if (brw->gen >= 8) {
 668       OUT_RELOC64(dst_buffer,
 669                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 670                   dst_offset);
 671    } else {
 672       OUT_RELOC(dst_buffer,
 673                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 674                 dst_offset);
 675    }
 676    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 677    OUT_BATCH((uint16_t)src_pitch);
 678    if (brw->gen >= 8) {
 679       OUT_RELOC64(src_buffer,
 680                   I915_GEM_DOMAIN_RENDER, 0,
 681                   src_offset);
 682    } else {
 683       OUT_RELOC(src_buffer,
 684                 I915_GEM_DOMAIN_RENDER, 0,
 685                 src_offset);
 686    }
 687
 688    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 689
 690    brw_emit_mi_flush(brw);
 691
 692    return true;
 693 }
 694
 695 bool
 696 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 697                                   GLuint cpp,
 698                                   GLubyte *src_bits, GLuint src_size,
 699                                   GLuint fg_color,
 700                                   GLshort dst_pitch,
 701                                   drm_intel_bo *dst_buffer,
 702                                   GLuint dst_offset,
 703                                   uint32_t dst_tiling,
 704                                   GLshort x, GLshort y,
 705                                   GLshort w, GLshort h,
 706                                   GLenum logic_op)
 707 {
 708    int dwords = ALIGN(src_size, 8) / 4;
 709    uint32_t opcode, br13, blit_cmd;
 710
 711    if (dst_tiling != I915_TILING_NONE) {
 712       if (dst_offset & 4095)
 713          return false;
 714       if (dst_tiling == I915_TILING_Y)
 715          return false;
 716    }
 717
 718    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 719    assert(dst_pitch > 0);
 720
 721    if (w < 0 || h < 0)
 722       return true;
 723
 724    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 725        __func__,
 726        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 727
 728    unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
 729    intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
 730                                         (3 * 4) + dwords * 4, BLT_RING);
 731
 732    opcode = XY_SETUP_BLT_CMD;
 733    if (cpp == 4)
 734       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 735    if (dst_tiling != I915_TILING_NONE) {
 736       opcode |= XY_DST_TILED;
 737       dst_pitch /= 4;
 738    }
 739
 740    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 741    br13 |= br13_for_cpp(cpp);
 742
 743    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 744    if (dst_tiling != I915_TILING_NONE)
 745       blit_cmd |= XY_DST_TILED;
 746
 747    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 748    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 749    OUT_BATCH(br13);
 750    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 751    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 752    if (brw->gen >= 8) {
 753       OUT_RELOC64(dst_buffer,
 754                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 755                   dst_offset);
 756    } else {
 757       OUT_RELOC(dst_buffer,
 758                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 759                 dst_offset);
 760    }
 761    OUT_BATCH(0); /* bg */
 762    OUT_BATCH(fg_color); /* fg */
 763    OUT_BATCH(0); /* pattern base addr */
 764    if (brw->gen >= 8)
 765       OUT_BATCH(0);
 766
 767    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 768    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 769    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 770    ADVANCE_BATCH();
 771
 772    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 773
 774    brw_emit_mi_flush(brw);
 775
 776    return true;
 777 }
 778
 779 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 780  * rectangular blit covering a large space, then emit 1-scanline blit at the
 781  * end to cover the last if we need.
 782  */
 783 void
 784 intel_emit_linear_blit(struct brw_context *brw,
 785                        drm_intel_bo *dst_bo,
 786                        unsigned int dst_offset,
 787                        drm_intel_bo *src_bo,
 788                        unsigned int src_offset,
 789                        unsigned int size)
 790 {
 791    struct gl_context *ctx = &brw->ctx;
 792    GLuint pitch, height;
 793    int16_t src_x, dst_x;
 794    bool ok;
 795
 796    do {
 797       /* The pitch given to the GPU must be DWORD aligned, and
 798        * we want width to match pitch. Max width is (1 << 15 - 1),
 799        * rounding that down to the nearest DWORD is 1 << 15 - 4
 800        */
 801       pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
 802       height = (size < pitch || pitch == 0) ? 1 : size / pitch;
 803
 804       src_x = src_offset % 64;
 805       dst_x = dst_offset % 64;
 806       pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
 807       assert(src_x + pitch < 1 << 15);
 808       assert(dst_x + pitch < 1 << 15);
 809
 810       ok = intelEmitCopyBlit(brw, 1,
 811                              pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
 812                              INTEL_MIPTREE_TRMODE_NONE,
 813                              pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
 814                              INTEL_MIPTREE_TRMODE_NONE,
 815                              src_x, 0, /* src x/y */
 816                              dst_x, 0, /* dst x/y */
 817                              MIN2(size, pitch), height, /* w, h */
 818                              GL_COPY);
 819       if (!ok) {
 820          _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
 821                        MIN2(size, pitch), height);
 822          return;
 823       }
 824
 825       pitch *= height;
 826       if (size <= pitch)
 827          return;
 828
 829       src_offset += pitch;
 830       dst_offset += pitch;
 831       size -= pitch;
 832    } while (1);
 833 }
 834
 835 /**
 836  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 837  * into it from an XRGB8888 source.
 838  *
 839  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 840  * relative to the start of the miptree, not relative to a slice within the
 841  * miptree.
 842  */
 843 static void
 844 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 845                               struct intel_mipmap_tree *mt,
 846                               int x, int y, int width, int height)
 847 {
 848    uint32_t BR13, CMD;
 849    int pitch, cpp;
 850    drm_intel_bo *aper_array[2];
 851
 852    pitch = mt->pitch;
 853    cpp = mt->cpp;
 854
 855    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 856        __func__, mt->bo, pitch, x, y, width, height);
 857
 858    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 859    CMD = XY_COLOR_BLT_CMD;
 860    CMD |= XY_BLT_WRITE_ALPHA;
 861
 862    if (mt->tiling != I915_TILING_NONE) {
 863       CMD |= XY_DST_TILED;
 864       pitch /= 4;
 865    }
 866    BR13 |= pitch;
 867
 868    /* do space check before going any further */
 869    aper_array[0] = brw->batch.bo;
 870    aper_array[1] = mt->bo;
 871
 872    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 873                                              ARRAY_SIZE(aper_array)) != 0) {
 874       intel_batchbuffer_flush(brw);
 875    }
 876
 877    unsigned length = brw->gen >= 8 ? 7 : 6;
 878    bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 879
 880    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 881    OUT_BATCH(CMD | (length - 2));
 882    OUT_BATCH(BR13);
 883    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 884    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
 885    if (brw->gen >= 8) {
 886       OUT_RELOC64(mt->bo,
 887                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 888                   0);
 889    } else {
 890       OUT_RELOC(mt->bo,
 891                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 892                 0);
 893    }
 894    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 895    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 896
 897    brw_emit_mi_flush(brw);
 898 }