src/mesa/drivers/dri/i965/intel_blit.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/mtypes.h"
  27 #include "main/blit.h"
  28 #include "main/context.h"
  29 #include "main/enums.h"
  30 #include "main/fbobject.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_fbo.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_mipmap_tree.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_BLIT
  41
  42 static void
  43 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  44                                struct intel_mipmap_tree *mt,
  45                                int x, int y, int width, int height);
  46
  47 static GLuint translate_raster_op(GLenum logicop)
  48 {
  49    switch(logicop) {
  50    case GL_CLEAR: return 0x00;
  51    case GL_AND: return 0x88;
  52    case GL_AND_REVERSE: return 0x44;
  53    case GL_COPY: return 0xCC;
  54    case GL_AND_INVERTED: return 0x22;
  55    case GL_NOOP: return 0xAA;
  56    case GL_XOR: return 0x66;
  57    case GL_OR: return 0xEE;
  58    case GL_NOR: return 0x11;
  59    case GL_EQUIV: return 0x99;
  60    case GL_INVERT: return 0x55;
  61    case GL_OR_REVERSE: return 0xDD;
  62    case GL_COPY_INVERTED: return 0x33;
  63    case GL_OR_INVERTED: return 0xBB;
  64    case GL_NAND: return 0x77;
  65    case GL_SET: return 0xFF;
  66    default: return 0;
  67    }
  68 }
  69
  70 static uint32_t
  71 br13_for_cpp(int cpp)
  72 {
  73    switch (cpp) {
  74    case 16:
  75       return BR13_32323232;
  76    case 8:
  77       return BR13_16161616;
  78    case 4:
  79       return BR13_8888;
  80    case 2:
  81       return BR13_565;
  82    case 1:
  83       return BR13_8;
  84    default:
  85       unreachable("not reached");
  86    }
  87 }
  88
  89 /**
  90  * Emits the packet for switching the blitter from X to Y tiled or back.
  91  *
  92  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  93  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  94  * part of the power context, not a render context, and if the batchbuffer was
  95  * to get flushed between setting and blitting, or blitting and restoring, our
  96  * tiling state would leak into other unsuspecting applications (like the X
  97  * server).
  98  */
  99 static uint32_t *
 100 set_blitter_tiling(struct brw_context *brw,
 101                    bool dst_y_tiled, bool src_y_tiled,
 102                    uint32_t *__map)
 103 {
 104    assert(brw->screen->devinfo.gen >= 6);
 105
 106    /* Idle the blitter before we update how tiling is interpreted. */
 107    OUT_BATCH(MI_FLUSH_DW | (4 - 2));
 108    OUT_BATCH(0);
 109    OUT_BATCH(0);
 110    OUT_BATCH(0);
 111
 112    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 113    OUT_BATCH(BCS_SWCTRL);
 114    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 115              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 116              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 117    return __map;
 118 }
 119 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 120
 121 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)              \
 122       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 123       if (dst_y_tiled || src_y_tiled)                                   \
 124          SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 125
 126 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)                   \
 127       if (dst_y_tiled || src_y_tiled)                                   \
 128          SET_BLITTER_TILING(brw, false, false);                         \
 129       ADVANCE_BATCH()
 130
 131 static int
 132 blt_pitch(struct intel_mipmap_tree *mt)
 133 {
 134    int pitch = mt->surf.row_pitch;
 135    if (mt->surf.tiling != ISL_TILING_LINEAR)
 136       pitch /= 4;
 137    return pitch;
 138 }
 139
 140 bool
 141 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 142 {
 143    /* The BLT doesn't handle sRGB conversion */
 144    assert(src == _mesa_get_srgb_format_linear(src));
 145    assert(dst == _mesa_get_srgb_format_linear(dst));
 146
 147    /* No swizzle or format conversions possible, except... */
 148    if (src == dst)
 149       return true;
 150
 151    /* ...we can either discard the alpha channel when going from A->X,
 152     * or we can fill the alpha channel with 0xff when going from X->A
 153     */
 154    if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
 155       return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
 156               dst == MESA_FORMAT_B8G8R8X8_UNORM);
 157
 158    if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
 159       return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
 160               dst == MESA_FORMAT_R8G8B8X8_UNORM);
 161
 162    return false;
 163 }
 164
 165 static void
 166 get_blit_intratile_offset_el(const struct brw_context *brw,
 167                              struct intel_mipmap_tree *mt,
 168                              uint32_t total_x_offset_el,
 169                              uint32_t total_y_offset_el,
 170                              uint32_t *base_address_offset,
 171                              uint32_t *x_offset_el,
 172                              uint32_t *y_offset_el)
 173 {
 174    isl_tiling_get_intratile_offset_el(mt->surf.tiling,
 175                                       mt->cpp * 8, mt->surf.row_pitch,
 176                                       total_x_offset_el, total_y_offset_el,
 177                                       base_address_offset,
 178                                       x_offset_el, y_offset_el);
 179    if (mt->surf.tiling == ISL_TILING_LINEAR) {
 180       /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
 181        *
 182        *    "Base address of the destination surface: X=0, Y=0. Lower 32bits
 183        *    of the 48bit addressing. When Src Tiling is enabled (Bit_15
 184        *    enabled), this address must be 4KB-aligned. When Tiling is not
 185        *    enabled, this address should be CL (64byte) aligned."
 186        *
 187        * The offsets we get from ISL in the tiled case are already aligned.
 188        * In the linear case, we need to do some of our own aligning.
 189        */
 190       uint32_t delta = *base_address_offset & 63;
 191       assert(delta % mt->cpp == 0);
 192       *base_address_offset -= delta;
 193       *x_offset_el += delta / mt->cpp;
 194    } else {
 195       assert(*base_address_offset % 4096 == 0);
 196    }
 197 }
 198
 199 static bool
 200 emit_miptree_blit(struct brw_context *brw,
 201                   struct intel_mipmap_tree *src_mt,
 202                   uint32_t src_x, uint32_t src_y,
 203                   struct intel_mipmap_tree *dst_mt,
 204                   uint32_t dst_x, uint32_t dst_y,
 205                   uint32_t width, uint32_t height,
 206                   bool reverse, GLenum logicop)
 207 {
 208    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 209     * Data Size Limitations):
 210     *
 211     *    The BLT engine is capable of transferring very large quantities of
 212     *    graphics data. Any graphics data read from and written to the
 213     *    destination is permitted to represent a number of pixels that
 214     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 215     *    at the destination. The maximum number of pixels that may be
 216     *    represented per scan line’s worth of graphics data depends on the
 217     *    color depth.
 218     *
 219     * The blitter's pitch is a signed 16-bit integer, but measured in bytes
 220     * for linear surfaces and DWords for tiled surfaces.  So the maximum
 221     * pitch is 32k linear and 128k tiled.
 222     */
 223    if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
 224       perf_debug("Falling back due to >= 32k/128k pitch\n");
 225       return false;
 226    }
 227
 228    /* We need to split the blit into chunks that each fit within the blitter's
 229     * restrictions.  We can't use a chunk size of 32768 because we need to
 230     * ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
 231     * a nice round power of two, big enough that performance won't suffer, and
 232     * small enough to guarantee everything fits.
 233     */
 234    const uint32_t max_chunk_size = 16384;
 235
 236    for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
 237       for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
 238          const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
 239          const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
 240
 241          uint32_t src_offset, src_tile_x, src_tile_y;
 242          get_blit_intratile_offset_el(brw, src_mt,
 243                                       src_x + chunk_x, src_y + chunk_y,
 244                                       &src_offset, &src_tile_x, &src_tile_y);
 245
 246          uint32_t dst_offset, dst_tile_x, dst_tile_y;
 247          get_blit_intratile_offset_el(brw, dst_mt,
 248                                       dst_x + chunk_x, dst_y + chunk_y,
 249                                       &dst_offset, &dst_tile_x, &dst_tile_y);
 250
 251          if (!intelEmitCopyBlit(brw,
 252                                 src_mt->cpp,
 253                                 reverse ? -src_mt->surf.row_pitch :
 254                                            src_mt->surf.row_pitch,
 255                                 src_mt->bo, src_mt->offset + src_offset,
 256                                 src_mt->surf.tiling,
 257                                 dst_mt->surf.row_pitch,
 258                                 dst_mt->bo, dst_mt->offset + dst_offset,
 259                                 dst_mt->surf.tiling,
 260                                 src_tile_x, src_tile_y,
 261                                 dst_tile_x, dst_tile_y,
 262                                 chunk_w, chunk_h,
 263                                 logicop)) {
 264             /* If this is ever going to fail, it will fail on the first chunk */
 265             assert(chunk_x == 0 && chunk_y == 0);
 266             return false;
 267          }
 268       }
 269    }
 270
 271    return true;
 272 }
 273
 274 /**
 275  * Implements a rectangular block transfer (blit) of pixels between two
 276  * miptrees.
 277  *
 278  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 279  * but limited, pitches and sizes allowed.
 280  *
 281  * The src/dst coordinates are relative to the given level/slice of the
 282  * miptree.
 283  *
 284  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 285  * will be inverted (including scanline order) when copying.  This is common
 286  * in GL when copying between window system and user-created
 287  * renderbuffers/textures.
 288  */
 289 bool
 290 intel_miptree_blit(struct brw_context *brw,
 291                    struct intel_mipmap_tree *src_mt,
 292                    int src_level, int src_slice,
 293                    uint32_t src_x, uint32_t src_y, bool src_flip,
 294                    struct intel_mipmap_tree *dst_mt,
 295                    int dst_level, int dst_slice,
 296                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 297                    uint32_t width, uint32_t height,
 298                    GLenum logicop)
 299 {
 300    /* The blitter doesn't understand multisampling at all. */
 301    if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
 302       return false;
 303
 304    /* No sRGB decode or encode is done by the hardware blitter, which is
 305     * consistent with what we want in many callers (glCopyTexSubImage(),
 306     * texture validation, etc.).
 307     */
 308    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 309    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 310
 311    /* The blitter doesn't support doing any format conversions.  We do also
 312     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 313     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 314     * channel to 1.0 at the end.
 315     */
 316    if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
 317       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 318                  "falling back.\n", __func__,
 319                  _mesa_get_format_name(src_format),
 320                  _mesa_get_format_name(dst_format));
 321       return false;
 322    }
 323
 324    /* The blitter has no idea about HiZ or fast color clears, so we need to
 325     * resolve the miptrees before we do anything.
 326     */
 327    intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
 328    intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
 329
 330    if (src_flip) {
 331       const unsigned h0 = src_mt->surf.phys_level0_sa.height;
 332       src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
 333    }
 334
 335    if (dst_flip) {
 336       const unsigned h0 = dst_mt->surf.phys_level0_sa.height;
 337       dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
 338    }
 339
 340    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
 341    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 342                                   &src_image_x, &src_image_y);
 343    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 344                                   &dst_image_x, &dst_image_y);
 345    src_x += src_image_x;
 346    src_y += src_image_y;
 347    dst_x += dst_image_x;
 348    dst_y += dst_image_y;
 349
 350    if (!emit_miptree_blit(brw, src_mt, src_x, src_y,
 351                           dst_mt, dst_x, dst_y, width, height,
 352                           src_flip != dst_flip, logicop)) {
 353       return false;
 354    }
 355
 356    /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
 357    if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
 358        _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
 359       intel_miptree_set_alpha_to_one(brw, dst_mt,
 360                                      dst_x, dst_y,
 361                                      width, height);
 362    }
 363
 364    return true;
 365 }
 366
 367 bool
 368 intel_miptree_copy(struct brw_context *brw,
 369                    struct intel_mipmap_tree *src_mt,
 370                    int src_level, int src_slice,
 371                    uint32_t src_x, uint32_t src_y,
 372                    struct intel_mipmap_tree *dst_mt,
 373                    int dst_level, int dst_slice,
 374                    uint32_t dst_x, uint32_t dst_y,
 375                    uint32_t src_width, uint32_t src_height)
 376 {
 377    /* The blitter doesn't understand multisampling at all. */
 378    if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
 379       return false;
 380
 381    if (src_mt->format == MESA_FORMAT_S_UINT8)
 382       return false;
 383
 384    /* The blitter has no idea about HiZ or fast color clears, so we need to
 385     * resolve the miptrees before we do anything.
 386     */
 387    intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
 388    intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
 389
 390    uint32_t src_image_x, src_image_y;
 391    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 392                                   &src_image_x, &src_image_y);
 393
 394    if (_mesa_is_format_compressed(src_mt->format)) {
 395       GLuint bw, bh;
 396       _mesa_get_format_block_size(src_mt->format, &bw, &bh);
 397
 398       /* Compressed textures need not have dimensions that are a multiple of
 399        * the block size.  Rectangles in compressed textures do need to be a
 400        * multiple of the block size.  The one exception is that the right and
 401        * bottom edges may be at the right or bottom edge of the miplevel even
 402        * if it's not aligned.
 403        */
 404       assert(src_x % bw == 0);
 405       assert(src_y % bh == 0);
 406
 407       assert(src_width % bw == 0 ||
 408              src_x + src_width ==
 409              minify(src_mt->surf.logical_level0_px.width, src_level));
 410       assert(src_height % bh == 0 ||
 411              src_y + src_height ==
 412              minify(src_mt->surf.logical_level0_px.height, src_level));
 413
 414       src_x /= (int)bw;
 415       src_y /= (int)bh;
 416       src_width = DIV_ROUND_UP(src_width, (int)bw);
 417       src_height = DIV_ROUND_UP(src_height, (int)bh);
 418    }
 419    src_x += src_image_x;
 420    src_y += src_image_y;
 421
 422    uint32_t dst_image_x, dst_image_y;
 423    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 424                                   &dst_image_x, &dst_image_y);
 425
 426    if (_mesa_is_format_compressed(dst_mt->format)) {
 427       GLuint bw, bh;
 428       _mesa_get_format_block_size(dst_mt->format, &bw, &bh);
 429
 430       assert(dst_x % bw == 0);
 431       assert(dst_y % bh == 0);
 432
 433       dst_x /= (int)bw;
 434       dst_y /= (int)bh;
 435    }
 436    dst_x += dst_image_x;
 437    dst_y += dst_image_y;
 438
 439    return emit_miptree_blit(brw, src_mt, src_x, src_y,
 440                             dst_mt, dst_x, dst_y,
 441                             src_width, src_height, false, GL_COPY);
 442 }
 443
 444 static bool
 445 alignment_valid(struct brw_context *brw, unsigned offset,
 446                 enum isl_tiling tiling)
 447 {
 448    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 449
 450    /* Tiled buffers must be page-aligned (4K). */
 451    if (tiling != ISL_TILING_LINEAR)
 452       return (offset & 4095) == 0;
 453
 454    /* On Gen8+, linear buffers must be cacheline-aligned. */
 455    if (devinfo->gen >= 8)
 456       return (offset & 63) == 0;
 457
 458    return true;
 459 }
 460
 461 static uint32_t
 462 xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
 463             uint32_t cpp)
 464 {
 465    uint32_t CMD = 0;
 466
 467    assert(cpp <= 4);
 468    switch (cpp) {
 469    case 1:
 470    case 2:
 471       CMD = XY_SRC_COPY_BLT_CMD;
 472       break;
 473    case 4:
 474       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 475       break;
 476    default:
 477       unreachable("not reached");
 478    }
 479
 480    if (dst_tiling != ISL_TILING_LINEAR)
 481       CMD |= XY_DST_TILED;
 482
 483    if (src_tiling != ISL_TILING_LINEAR)
 484       CMD |= XY_SRC_TILED;
 485
 486    return CMD;
 487 }
 488
 489 /* Copy BitBlt
 490  */
 491 bool
 492 intelEmitCopyBlit(struct brw_context *brw,
 493                   GLuint cpp,
 494                   int32_t src_pitch,
 495                   struct brw_bo *src_buffer,
 496                   GLuint src_offset,
 497                   enum isl_tiling src_tiling,
 498                   int32_t dst_pitch,
 499                   struct brw_bo *dst_buffer,
 500                   GLuint dst_offset,
 501                   enum isl_tiling dst_tiling,
 502                   GLshort src_x, GLshort src_y,
 503                   GLshort dst_x, GLshort dst_y,
 504                   GLshort w, GLshort h,
 505                   GLenum logic_op)
 506 {
 507    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 508    GLuint CMD, BR13;
 509    int dst_y2 = dst_y + h;
 510    int dst_x2 = dst_x + w;
 511    bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
 512    bool src_y_tiled = src_tiling == ISL_TILING_Y0;
 513    uint32_t src_tile_w, src_tile_h;
 514    uint32_t dst_tile_w, dst_tile_h;
 515
 516    if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
 517       return false;
 518
 519    const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
 520
 521    /* do space check before going any further */
 522    if (!brw_batch_has_aperture_space(brw, bo_sizes))
 523       intel_batchbuffer_flush(brw);
 524
 525    if (!brw_batch_has_aperture_space(brw, bo_sizes))
 526       return false;
 527
 528    unsigned length = devinfo->gen >= 8 ? 10 : 8;
 529
 530    intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
 531    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 532        __func__,
 533        src_buffer, src_pitch, src_offset, src_x, src_y,
 534        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 535
 536    intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
 537    intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
 538
 539    /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
 540     * (X direction width of the Tile). This is ensured while allocating the
 541     * buffer object.
 542     */
 543    assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
 544    assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
 545
 546    /* For big formats (such as floating point), do the copy using 16 or
 547     * 32bpp and multiply the coordinates.
 548     */
 549    if (cpp > 4) {
 550       if (cpp % 4 == 2) {
 551          dst_x *= cpp / 2;
 552          dst_x2 *= cpp / 2;
 553          src_x *= cpp / 2;
 554          cpp = 2;
 555       } else {
 556          assert(cpp % 4 == 0);
 557          dst_x *= cpp / 4;
 558          dst_x2 *= cpp / 4;
 559          src_x *= cpp / 4;
 560          cpp = 4;
 561       }
 562    }
 563
 564    if (!alignment_valid(brw, dst_offset, dst_tiling))
 565       return false;
 566    if (!alignment_valid(brw, src_offset, src_tiling))
 567       return false;
 568
 569    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 570     * the low bits.  Offsets must be naturally aligned.
 571     */
 572    if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 573        dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 574       return false;
 575
 576    assert(cpp <= 4);
 577    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 578
 579    CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
 580
 581    /* For tiled source and destination, pitch value should be specified
 582     * as a number of Dwords.
 583     */
 584    if (dst_tiling != ISL_TILING_LINEAR)
 585       dst_pitch /= 4;
 586
 587    if (src_tiling != ISL_TILING_LINEAR)
 588       src_pitch /= 4;
 589
 590    if (dst_y2 <= dst_y || dst_x2 <= dst_x)
 591       return true;
 592
 593    assert(dst_x < dst_x2);
 594    assert(dst_y < dst_y2);
 595
 596    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 597    OUT_BATCH(CMD | (length - 2));
 598    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 599    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 600    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 601    if (devinfo->gen >= 8) {
 602       OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
 603    } else {
 604       OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
 605    }
 606    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 607    OUT_BATCH((uint16_t)src_pitch);
 608    if (devinfo->gen >= 8) {
 609       OUT_RELOC64(src_buffer, 0, src_offset);
 610    } else {
 611       OUT_RELOC(src_buffer, 0, src_offset);
 612    }
 613
 614    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 615
 616    brw_emit_mi_flush(brw);
 617
 618    return true;
 619 }
 620
 621 bool
 622 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 623                                   GLuint cpp,
 624                                   GLubyte *src_bits, GLuint src_size,
 625                                   GLuint fg_color,
 626                                   GLshort dst_pitch,
 627                                   struct brw_bo *dst_buffer,
 628                                   GLuint dst_offset,
 629                                   enum isl_tiling dst_tiling,
 630                                   GLshort x, GLshort y,
 631                                   GLshort w, GLshort h,
 632                                   GLenum logic_op)
 633 {
 634    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 635    int dwords = ALIGN(src_size, 8) / 4;
 636    uint32_t opcode, br13, blit_cmd;
 637
 638    if (dst_tiling != ISL_TILING_LINEAR) {
 639       if (dst_offset & 4095)
 640          return false;
 641       if (dst_tiling == ISL_TILING_Y0)
 642          return false;
 643    }
 644
 645    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 646    assert(dst_pitch > 0);
 647
 648    if (w < 0 || h < 0)
 649       return true;
 650
 651    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 652        __func__,
 653        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 654
 655    unsigned xy_setup_blt_length = devinfo->gen >= 8 ? 10 : 8;
 656    intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
 657                                         (3 * 4) + dwords * 4, BLT_RING);
 658
 659    opcode = XY_SETUP_BLT_CMD;
 660    if (cpp == 4)
 661       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 662    if (dst_tiling != ISL_TILING_LINEAR) {
 663       opcode |= XY_DST_TILED;
 664       dst_pitch /= 4;
 665    }
 666
 667    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 668    br13 |= br13_for_cpp(cpp);
 669
 670    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 671    if (dst_tiling != ISL_TILING_LINEAR)
 672       blit_cmd |= XY_DST_TILED;
 673
 674    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 675    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 676    OUT_BATCH(br13);
 677    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 678    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 679    if (devinfo->gen >= 8) {
 680       OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
 681    } else {
 682       OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
 683    }
 684    OUT_BATCH(0); /* bg */
 685    OUT_BATCH(fg_color); /* fg */
 686    OUT_BATCH(0); /* pattern base addr */
 687    if (devinfo->gen >= 8)
 688       OUT_BATCH(0);
 689
 690    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 691    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 692    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 693    ADVANCE_BATCH();
 694
 695    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 696
 697    brw_emit_mi_flush(brw);
 698
 699    return true;
 700 }
 701
 702 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 703  * rectangular blit covering a large space, then emit 1-scanline blit at the
 704  * end to cover the last if we need.
 705  */
 706 void
 707 intel_emit_linear_blit(struct brw_context *brw,
 708                        struct brw_bo *dst_bo,
 709                        unsigned int dst_offset,
 710                        struct brw_bo *src_bo,
 711                        unsigned int src_offset,
 712                        unsigned int size)
 713 {
 714    struct gl_context *ctx = &brw->ctx;
 715    GLuint pitch, height;
 716    int16_t src_x, dst_x;
 717    bool ok;
 718
 719    do {
 720       /* The pitch given to the GPU must be DWORD aligned, and
 721        * we want width to match pitch. Max width is (1 << 15 - 1),
 722        * rounding that down to the nearest DWORD is 1 << 15 - 4
 723        */
 724       pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
 725       height = (size < pitch || pitch == 0) ? 1 : size / pitch;
 726
 727       src_x = src_offset % 64;
 728       dst_x = dst_offset % 64;
 729       pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
 730       assert(src_x + pitch < 1 << 15);
 731       assert(dst_x + pitch < 1 << 15);
 732
 733       ok = intelEmitCopyBlit(brw, 1,
 734                              pitch, src_bo, src_offset - src_x,
 735                              ISL_TILING_LINEAR,
 736                              pitch, dst_bo, dst_offset - dst_x,
 737                              ISL_TILING_LINEAR,
 738                              src_x, 0, /* src x/y */
 739                              dst_x, 0, /* dst x/y */
 740                              MIN2(size, pitch), height, /* w, h */
 741                              GL_COPY);
 742       if (!ok) {
 743          _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
 744                        MIN2(size, pitch), height);
 745          return;
 746       }
 747
 748       pitch *= height;
 749       if (size <= pitch)
 750          return;
 751
 752       src_offset += pitch;
 753       dst_offset += pitch;
 754       size -= pitch;
 755    } while (1);
 756 }
 757
 758 /**
 759  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 760  * into it from an XRGB8888 source.
 761  *
 762  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 763  * relative to the start of the miptree, not relative to a slice within the
 764  * miptree.
 765  */
 766 static void
 767 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 768                               struct intel_mipmap_tree *mt,
 769                               int x, int y, int width, int height)
 770 {
 771    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 772    uint32_t BR13, CMD;
 773    int pitch, cpp;
 774
 775    pitch = mt->surf.row_pitch;
 776    cpp = mt->cpp;
 777
 778    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 779        __func__, mt->bo, pitch, x, y, width, height);
 780
 781    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 782    CMD = XY_COLOR_BLT_CMD;
 783    CMD |= XY_BLT_WRITE_ALPHA;
 784
 785    if (mt->surf.tiling != ISL_TILING_LINEAR) {
 786       CMD |= XY_DST_TILED;
 787       pitch /= 4;
 788    }
 789    BR13 |= pitch;
 790
 791    /* do space check before going any further */
 792    if (!brw_batch_has_aperture_space(brw, mt->bo->size))
 793       intel_batchbuffer_flush(brw);
 794
 795    unsigned length = devinfo->gen >= 8 ? 7 : 6;
 796    const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0;
 797
 798    /* We need to split the blit into chunks that each fit within the blitter's
 799     * restrictions.  We can't use a chunk size of 32768 because we need to
 800     * ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
 801     * a nice round power of two, big enough that performance won't suffer, and
 802     * small enough to guarantee everything fits.
 803     */
 804    const uint32_t max_chunk_size = 16384;
 805
 806    for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
 807       for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
 808          const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
 809          const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
 810
 811          uint32_t offset, tile_x, tile_y;
 812          get_blit_intratile_offset_el(brw, mt,
 813                                       x + chunk_x, y + chunk_y,
 814                                       &offset, &tile_x, &tile_y);
 815
 816          BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 817          OUT_BATCH(CMD | (length - 2));
 818          OUT_BATCH(BR13);
 819          OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
 820                    SET_FIELD(x + chunk_x, BLT_X));
 821          OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
 822                    SET_FIELD(x + chunk_x + chunk_w, BLT_X));
 823          if (devinfo->gen >= 8) {
 824             OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
 825          } else {
 826             OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
 827          }
 828          OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 829          ADVANCE_BATCH_TILED(dst_y_tiled, false);
 830       }
 831    }
 832
 833    brw_emit_mi_flush(brw);
 834 }