src/mesa/drivers/dri/i965/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "brw_context.h"
  36 #include "intel_blit.h"
  37 #include "intel_buffers.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 static void
  47 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  48                                struct intel_mipmap_tree *mt,
  49                                int x, int y, int width, int height);
  50
  51 static GLuint translate_raster_op(GLenum logicop)
  52 {
  53    switch(logicop) {
  54    case GL_CLEAR: return 0x00;
  55    case GL_AND: return 0x88;
  56    case GL_AND_REVERSE: return 0x44;
  57    case GL_COPY: return 0xCC;
  58    case GL_AND_INVERTED: return 0x22;
  59    case GL_NOOP: return 0xAA;
  60    case GL_XOR: return 0x66;
  61    case GL_OR: return 0xEE;
  62    case GL_NOR: return 0x11;
  63    case GL_EQUIV: return 0x99;
  64    case GL_INVERT: return 0x55;
  65    case GL_OR_REVERSE: return 0xDD;
  66    case GL_COPY_INVERTED: return 0x33;
  67    case GL_OR_INVERTED: return 0xBB;
  68    case GL_NAND: return 0x77;
  69    case GL_SET: return 0xFF;
  70    default: return 0;
  71    }
  72 }
  73
  74 static uint32_t
  75 br13_for_cpp(int cpp)
  76 {
  77    switch (cpp) {
  78    case 4:
  79       return BR13_8888;
  80       break;
  81    case 2:
  82       return BR13_565;
  83       break;
  84    case 1:
  85       return BR13_8;
  86       break;
  87    default:
  88       assert(0);
  89       return 0;
  90    }
  91 }
  92
  93 /**
  94  * Emits the packet for switching the blitter from X to Y tiled or back.
  95  *
  96  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  97  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  98  * part of the power context, not a render context, and if the batchbuffer was
  99  * to get flushed between setting and blitting, or blitting and restoring, our
 100  * tiling state would leak into other unsuspecting applications (like the X
 101  * server).
 102  */
 103 static void
 104 set_blitter_tiling(struct brw_context *brw,
 105                    bool dst_y_tiled, bool src_y_tiled)
 106 {
 107    assert(brw->gen >= 6);
 108
 109    /* Idle the blitter before we update how tiling is interpreted. */
 110    OUT_BATCH(MI_FLUSH_DW);
 111    OUT_BATCH(0);
 112    OUT_BATCH(0);
 113    OUT_BATCH(0);
 114
 115    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 116    OUT_BATCH(BCS_SWCTRL);
 117    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 118              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 119              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 120 }
 121
 122 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
 123       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 124       if (dst_y_tiled || src_y_tiled)                                   \
 125          set_blitter_tiling(brw, dst_y_tiled, src_y_tiled);             \
 126    } while (0)
 127
 128 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
 129       if (dst_y_tiled || src_y_tiled)                                   \
 130          set_blitter_tiling(brw, false, false);                         \
 131       ADVANCE_BATCH();                                                  \
 132    } while (0)
 133
 134 /**
 135  * Implements a rectangular block transfer (blit) of pixels between two
 136  * miptrees.
 137  *
 138  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 139  * but limited, pitches and sizes allowed.
 140  *
 141  * The src/dst coordinates are relative to the given level/slice of the
 142  * miptree.
 143  *
 144  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 145  * will be inverted (including scanline order) when copying.  This is common
 146  * in GL when copying between window system and user-created
 147  * renderbuffers/textures.
 148  */
 149 bool
 150 intel_miptree_blit(struct brw_context *brw,
 151                    struct intel_mipmap_tree *src_mt,
 152                    int src_level, int src_slice,
 153                    uint32_t src_x, uint32_t src_y, bool src_flip,
 154                    struct intel_mipmap_tree *dst_mt,
 155                    int dst_level, int dst_slice,
 156                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 157                    uint32_t width, uint32_t height,
 158                    GLenum logicop)
 159 {
 160    /* No sRGB decode or encode is done by the hardware blitter, which is
 161     * consistent with what we want in the callers (glCopyTexSubImage(),
 162     * glBlitFramebuffer(), texture validation, etc.).
 163     */
 164    gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 165    gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 166
 167    /* The blitter doesn't support doing any format conversions.  We do also
 168     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 169     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 170     * channel to 1.0 at the end.
 171     */
 172    if (src_format != dst_format &&
 173       ((src_format != MESA_FORMAT_ARGB8888 &&
 174         src_format != MESA_FORMAT_XRGB8888) ||
 175        (dst_format != MESA_FORMAT_ARGB8888 &&
 176         dst_format != MESA_FORMAT_XRGB8888))) {
 177       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 178                  "falling back.\n", __FUNCTION__,
 179                  _mesa_get_format_name(src_format),
 180                  _mesa_get_format_name(dst_format));
 181       return false;
 182    }
 183
 184    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 185     * Data Size Limitations):
 186     *
 187     *    The BLT engine is capable of transferring very large quantities of
 188     *    graphics data. Any graphics data read from and written to the
 189     *    destination is permitted to represent a number of pixels that
 190     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 191     *    at the destination. The maximum number of pixels that may be
 192     *    represented per scan line’s worth of graphics data depends on the
 193     *    color depth.
 194     *
 195     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 196     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 197     * pitches < 32k.
 198     *
 199     * As a result of these two limitations, we can only use the blitter to do
 200     * this copy when the region's pitch is less than 32k.
 201     */
 202    if (src_mt->region->pitch > 32768 ||
 203        dst_mt->region->pitch > 32768) {
 204       perf_debug("Falling back due to >32k pitch\n");
 205       return false;
 206    }
 207
 208    /* The blitter has no idea about HiZ or fast color clears, so we need to
 209     * resolve the miptrees before we do anything.
 210     */
 211    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 212    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 213    intel_miptree_resolve_color(brw, src_mt);
 214    intel_miptree_resolve_color(brw, dst_mt);
 215
 216    if (src_flip)
 217       src_y = src_mt->level[src_level].height - src_y - height;
 218
 219    if (dst_flip)
 220       dst_y = dst_mt->level[dst_level].height - dst_y - height;
 221
 222    int src_pitch = src_mt->region->pitch;
 223    if (src_flip != dst_flip)
 224       src_pitch = -src_pitch;
 225
 226    uint32_t src_image_x, src_image_y;
 227    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 228                                   &src_image_x, &src_image_y);
 229    src_x += src_image_x;
 230    src_y += src_image_y;
 231
 232    /* The blitter interprets the 16-bit src x/y as a signed 16-bit value,
 233     * where negative values are invalid.  The values we're working with are
 234     * unsigned, so make sure we don't overflow.
 235     */
 236    if (src_x >= 32768 || src_y >= 32768) {
 237       perf_debug("Falling back due to >=32k src offset (%d, %d)\n",
 238                  src_x, src_y);
 239       return false;
 240    }
 241
 242    uint32_t dst_image_x, dst_image_y;
 243    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 244                                   &dst_image_x, &dst_image_y);
 245    dst_x += dst_image_x;
 246    dst_y += dst_image_y;
 247
 248    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 249     * value.  The values we're working with are unsigned, so make sure we
 250     * don't overflow.
 251     */
 252    if (dst_x >= 32768 || dst_y >= 32768) {
 253       perf_debug("Falling back due to >=32k dst offset (%d, %d)\n",
 254                  dst_x, dst_y);
 255       return false;
 256    }
 257
 258    if (!intelEmitCopyBlit(brw,
 259                           src_mt->cpp,
 260                           src_pitch,
 261                           src_mt->region->bo, src_mt->offset,
 262                           src_mt->region->tiling,
 263                           dst_mt->region->pitch,
 264                           dst_mt->region->bo, dst_mt->offset,
 265                           dst_mt->region->tiling,
 266                           src_x, src_y,
 267                           dst_x, dst_y,
 268                           width, height,
 269                           logicop)) {
 270       return false;
 271    }
 272
 273    if (src_mt->format == MESA_FORMAT_XRGB8888 &&
 274        dst_mt->format == MESA_FORMAT_ARGB8888) {
 275       intel_miptree_set_alpha_to_one(brw, dst_mt,
 276                                      dst_x, dst_y,
 277                                      width, height);
 278    }
 279
 280    return true;
 281 }
 282
 283 /* Copy BitBlt
 284  */
 285 bool
 286 intelEmitCopyBlit(struct brw_context *brw,
 287                   GLuint cpp,
 288                   GLshort src_pitch,
 289                   drm_intel_bo *src_buffer,
 290                   GLuint src_offset,
 291                   uint32_t src_tiling,
 292                   GLshort dst_pitch,
 293                   drm_intel_bo *dst_buffer,
 294                   GLuint dst_offset,
 295                   uint32_t dst_tiling,
 296                   GLshort src_x, GLshort src_y,
 297                   GLshort dst_x, GLshort dst_y,
 298                   GLshort w, GLshort h,
 299                   GLenum logic_op)
 300 {
 301    GLuint CMD, BR13, pass = 0;
 302    int dst_y2 = dst_y + h;
 303    int dst_x2 = dst_x + w;
 304    drm_intel_bo *aper_array[3];
 305    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 306    bool src_y_tiled = src_tiling == I915_TILING_Y;
 307
 308    if (dst_tiling != I915_TILING_NONE) {
 309       if (dst_offset & 4095)
 310          return false;
 311    }
 312    if (src_tiling != I915_TILING_NONE) {
 313       if (src_offset & 4095)
 314          return false;
 315    }
 316    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 317       return false;
 318
 319    /* do space check before going any further */
 320    do {
 321        aper_array[0] = brw->batch.bo;
 322        aper_array[1] = dst_buffer;
 323        aper_array[2] = src_buffer;
 324
 325        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 326            intel_batchbuffer_flush(brw);
 327            pass++;
 328        } else
 329            break;
 330    } while (pass < 2);
 331
 332    if (pass >= 2)
 333       return false;
 334
 335    intel_batchbuffer_require_space(brw, 8 * 4, BLT_RING);
 336    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 337        __FUNCTION__,
 338        src_buffer, src_pitch, src_offset, src_x, src_y,
 339        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 340
 341    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 342     * the low bits.
 343     */
 344    if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
 345       return false;
 346
 347    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 348     * and multiply the coordinates.
 349     */
 350    if (cpp > 4) {
 351       if (cpp % 4 == 2) {
 352          dst_x *= cpp / 2;
 353          dst_x2 *= cpp / 2;
 354          src_x *= cpp / 2;
 355          cpp = 2;
 356       } else {
 357          assert(cpp % 4 == 0);
 358          dst_x *= cpp / 4;
 359          dst_x2 *= cpp / 4;
 360          src_x *= cpp / 4;
 361          cpp = 4;
 362       }
 363    }
 364
 365    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 366
 367    switch (cpp) {
 368    case 1:
 369    case 2:
 370       CMD = XY_SRC_COPY_BLT_CMD;
 371       break;
 372    case 4:
 373       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 374       break;
 375    default:
 376       return false;
 377    }
 378
 379    if (dst_tiling != I915_TILING_NONE) {
 380       CMD |= XY_DST_TILED;
 381       dst_pitch /= 4;
 382    }
 383    if (src_tiling != I915_TILING_NONE) {
 384       CMD |= XY_SRC_TILED;
 385       src_pitch /= 4;
 386    }
 387
 388    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 389       return true;
 390    }
 391
 392    assert(dst_x < dst_x2);
 393    assert(dst_y < dst_y2);
 394    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 395           (w * cpp) <= src_buffer->size);
 396    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 397           (w * cpp) <= dst_buffer->size);
 398
 399    BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled);
 400
 401    OUT_BATCH(CMD | (8 - 2));
 402    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 403    OUT_BATCH((dst_y << 16) | dst_x);
 404    OUT_BATCH((dst_y2 << 16) | dst_x2);
 405    OUT_RELOC(dst_buffer,
 406              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 407              dst_offset);
 408    OUT_BATCH((src_y << 16) | src_x);
 409    OUT_BATCH((uint16_t)src_pitch);
 410    OUT_RELOC(src_buffer, I915_GEM_DOMAIN_RENDER, 0, src_offset);
 411
 412    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 413
 414    intel_batchbuffer_emit_mi_flush(brw);
 415
 416    return true;
 417 }
 418
 419 bool
 420 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 421                                   GLuint cpp,
 422                                   GLubyte *src_bits, GLuint src_size,
 423                                   GLuint fg_color,
 424                                   GLshort dst_pitch,
 425                                   drm_intel_bo *dst_buffer,
 426                                   GLuint dst_offset,
 427                                   uint32_t dst_tiling,
 428                                   GLshort x, GLshort y,
 429                                   GLshort w, GLshort h,
 430                                   GLenum logic_op)
 431 {
 432    int dwords = ALIGN(src_size, 8) / 4;
 433    uint32_t opcode, br13, blit_cmd;
 434
 435    if (dst_tiling != I915_TILING_NONE) {
 436       if (dst_offset & 4095)
 437          return false;
 438       if (dst_tiling == I915_TILING_Y)
 439          return false;
 440    }
 441
 442    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 443    assert(dst_pitch > 0);
 444
 445    if (w < 0 || h < 0)
 446       return true;
 447
 448    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 449        __FUNCTION__,
 450        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 451
 452    intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, BLT_RING);
 453
 454    opcode = XY_SETUP_BLT_CMD;
 455    if (cpp == 4)
 456       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 457    if (dst_tiling != I915_TILING_NONE) {
 458       opcode |= XY_DST_TILED;
 459       dst_pitch /= 4;
 460    }
 461
 462    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 463    br13 |= br13_for_cpp(cpp);
 464
 465    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 466    if (dst_tiling != I915_TILING_NONE)
 467       blit_cmd |= XY_DST_TILED;
 468
 469    BEGIN_BATCH_BLT(8 + 3);
 470    OUT_BATCH(opcode | (8 - 2));
 471    OUT_BATCH(br13);
 472    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 473    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 474    OUT_RELOC(dst_buffer,
 475              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 476              dst_offset);
 477    OUT_BATCH(0); /* bg */
 478    OUT_BATCH(fg_color); /* fg */
 479    OUT_BATCH(0); /* pattern base addr */
 480
 481    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 482    OUT_BATCH((y << 16) | x);
 483    OUT_BATCH(((y + h) << 16) | (x + w));
 484    ADVANCE_BATCH();
 485
 486    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 487
 488    intel_batchbuffer_emit_mi_flush(brw);
 489
 490    return true;
 491 }
 492
 493 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 494  * rectangular blit covering a large space, then emit 1-scanline blit at the
 495  * end to cover the last if we need.
 496  */
 497 void
 498 intel_emit_linear_blit(struct brw_context *brw,
 499                        drm_intel_bo *dst_bo,
 500                        unsigned int dst_offset,
 501                        drm_intel_bo *src_bo,
 502                        unsigned int src_offset,
 503                        unsigned int size)
 504 {
 505    struct gl_context *ctx = &brw->ctx;
 506    GLuint pitch, height;
 507    bool ok;
 508
 509    /* The pitch given to the GPU must be DWORD aligned, and
 510     * we want width to match pitch. Max width is (1 << 15 - 1),
 511     * rounding that down to the nearest DWORD is 1 << 15 - 4
 512     */
 513    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 514    height = (pitch == 0) ? 1 : size / pitch;
 515    ok = intelEmitCopyBlit(brw, 1,
 516                           pitch, src_bo, src_offset, I915_TILING_NONE,
 517                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 518                           0, 0, /* src x/y */
 519                           0, 0, /* dst x/y */
 520                           pitch, height, /* w, h */
 521                           GL_COPY);
 522    if (!ok)
 523       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 524
 525    src_offset += pitch * height;
 526    dst_offset += pitch * height;
 527    size -= pitch * height;
 528    assert (size < (1 << 15));
 529    pitch = ALIGN(size, 4);
 530    if (size != 0) {
 531       ok = intelEmitCopyBlit(brw, 1,
 532                              pitch, src_bo, src_offset, I915_TILING_NONE,
 533                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 534                              0, 0, /* src x/y */
 535                              0, 0, /* dst x/y */
 536                              size, 1, /* w, h */
 537                              GL_COPY);
 538       if (!ok)
 539          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 540    }
 541 }
 542
 543 /**
 544  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 545  * into it from an XRGB8888 source.
 546  *
 547  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 548  * relative to the start of the miptree, not relative to a slice within the
 549  * miptree.
 550  */
 551 static void
 552 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 553                               struct intel_mipmap_tree *mt,
 554                               int x, int y, int width, int height)
 555 {
 556    struct intel_region *region = mt->region;
 557    uint32_t BR13, CMD;
 558    int pitch, cpp;
 559    drm_intel_bo *aper_array[2];
 560
 561    pitch = region->pitch;
 562    cpp = region->cpp;
 563
 564    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 565        __FUNCTION__, region->bo, pitch, x, y, width, height);
 566
 567    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 568    CMD = XY_COLOR_BLT_CMD;
 569    CMD |= XY_BLT_WRITE_ALPHA;
 570
 571    if (region->tiling != I915_TILING_NONE) {
 572       CMD |= XY_DST_TILED;
 573       pitch /= 4;
 574    }
 575    BR13 |= pitch;
 576
 577    /* do space check before going any further */
 578    aper_array[0] = brw->batch.bo;
 579    aper_array[1] = region->bo;
 580
 581    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 582                                              ARRAY_SIZE(aper_array)) != 0) {
 583       intel_batchbuffer_flush(brw);
 584    }
 585
 586    bool dst_y_tiled = region->tiling == I915_TILING_Y;
 587
 588    BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false);
 589    OUT_BATCH(CMD | (6 - 2));
 590    OUT_BATCH(BR13);
 591    OUT_BATCH((y << 16) | x);
 592    OUT_BATCH(((y + height) << 16) | (x + width));
 593    OUT_RELOC(region->bo,
 594              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 595              0);
 596    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 597    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 598
 599    intel_batchbuffer_emit_mi_flush(brw);
 600 }