src/mesa/drivers/dri/i965/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_defines.h"
  37 #include "intel_blit.h"
  38 #include "intel_buffers.h"
  39 #include "intel_fbo.h"
  40 #include "intel_reg.h"
  41 #include "intel_regions.h"
  42 #include "intel_batchbuffer.h"
  43 #include "intel_mipmap_tree.h"
  44
  45 #define FILE_DEBUG_FLAG DEBUG_BLIT
  46
  47 static void
  48 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  49                                struct intel_mipmap_tree *mt,
  50                                int x, int y, int width, int height);
  51
  52 static GLuint translate_raster_op(GLenum logicop)
  53 {
  54    switch(logicop) {
  55    case GL_CLEAR: return 0x00;
  56    case GL_AND: return 0x88;
  57    case GL_AND_REVERSE: return 0x44;
  58    case GL_COPY: return 0xCC;
  59    case GL_AND_INVERTED: return 0x22;
  60    case GL_NOOP: return 0xAA;
  61    case GL_XOR: return 0x66;
  62    case GL_OR: return 0xEE;
  63    case GL_NOR: return 0x11;
  64    case GL_EQUIV: return 0x99;
  65    case GL_INVERT: return 0x55;
  66    case GL_OR_REVERSE: return 0xDD;
  67    case GL_COPY_INVERTED: return 0x33;
  68    case GL_OR_INVERTED: return 0xBB;
  69    case GL_NAND: return 0x77;
  70    case GL_SET: return 0xFF;
  71    default: return 0;
  72    }
  73 }
  74
  75 static uint32_t
  76 br13_for_cpp(int cpp)
  77 {
  78    switch (cpp) {
  79    case 4:
  80       return BR13_8888;
  81       break;
  82    case 2:
  83       return BR13_565;
  84       break;
  85    case 1:
  86       return BR13_8;
  87       break;
  88    default:
  89       assert(0);
  90       return 0;
  91    }
  92 }
  93
  94 /**
  95  * Emits the packet for switching the blitter from X to Y tiled or back.
  96  *
  97  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  98  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  99  * part of the power context, not a render context, and if the batchbuffer was
 100  * to get flushed between setting and blitting, or blitting and restoring, our
 101  * tiling state would leak into other unsuspecting applications (like the X
 102  * server).
 103  */
 104 static void
 105 set_blitter_tiling(struct brw_context *brw,
 106                    bool dst_y_tiled, bool src_y_tiled)
 107 {
 108    assert(brw->gen >= 6);
 109
 110    /* Idle the blitter before we update how tiling is interpreted. */
 111    OUT_BATCH(MI_FLUSH_DW);
 112    OUT_BATCH(0);
 113    OUT_BATCH(0);
 114    OUT_BATCH(0);
 115
 116    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 117    OUT_BATCH(BCS_SWCTRL);
 118    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 119              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 120              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 121 }
 122
 123 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
 124       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 125       if (dst_y_tiled || src_y_tiled)                                   \
 126          set_blitter_tiling(brw, dst_y_tiled, src_y_tiled);             \
 127    } while (0)
 128
 129 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
 130       if (dst_y_tiled || src_y_tiled)                                   \
 131          set_blitter_tiling(brw, false, false);                         \
 132       ADVANCE_BATCH();                                                  \
 133    } while (0)
 134
 135 /**
 136  * Implements a rectangular block transfer (blit) of pixels between two
 137  * miptrees.
 138  *
 139  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 140  * but limited, pitches and sizes allowed.
 141  *
 142  * The src/dst coordinates are relative to the given level/slice of the
 143  * miptree.
 144  *
 145  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 146  * will be inverted (including scanline order) when copying.  This is common
 147  * in GL when copying between window system and user-created
 148  * renderbuffers/textures.
 149  */
 150 bool
 151 intel_miptree_blit(struct brw_context *brw,
 152                    struct intel_mipmap_tree *src_mt,
 153                    int src_level, int src_slice,
 154                    uint32_t src_x, uint32_t src_y, bool src_flip,
 155                    struct intel_mipmap_tree *dst_mt,
 156                    int dst_level, int dst_slice,
 157                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 158                    uint32_t width, uint32_t height,
 159                    GLenum logicop)
 160 {
 161    /* The blitter doesn't understand multisampling at all. */
 162    if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
 163       return false;
 164
 165    /* No sRGB decode or encode is done by the hardware blitter, which is
 166     * consistent with what we want in the callers (glCopyTexSubImage(),
 167     * glBlitFramebuffer(), texture validation, etc.).
 168     */
 169    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 170    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 171
 172    /* The blitter doesn't support doing any format conversions.  We do also
 173     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 174     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 175     * channel to 1.0 at the end.
 176     */
 177    if (src_format != dst_format &&
 178       ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 179         src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
 180        (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 181         dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
 182       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 183                  "falling back.\n", __FUNCTION__,
 184                  _mesa_get_format_name(src_format),
 185                  _mesa_get_format_name(dst_format));
 186       return false;
 187    }
 188
 189    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 190     * Data Size Limitations):
 191     *
 192     *    The BLT engine is capable of transferring very large quantities of
 193     *    graphics data. Any graphics data read from and written to the
 194     *    destination is permitted to represent a number of pixels that
 195     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 196     *    at the destination. The maximum number of pixels that may be
 197     *    represented per scan line’s worth of graphics data depends on the
 198     *    color depth.
 199     *
 200     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 201     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 202     * pitches < 32k.
 203     *
 204     * As a result of these two limitations, we can only use the blitter to do
 205     * this copy when the region's pitch is less than 32k.
 206     */
 207    if (src_mt->region->pitch >= 32768 ||
 208        dst_mt->region->pitch >= 32768) {
 209       perf_debug("Falling back due to >=32k pitch\n");
 210       return false;
 211    }
 212
 213    /* The blitter has no idea about HiZ or fast color clears, so we need to
 214     * resolve the miptrees before we do anything.
 215     */
 216    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 217    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 218    intel_miptree_resolve_color(brw, src_mt);
 219    intel_miptree_resolve_color(brw, dst_mt);
 220
 221    if (src_flip)
 222       src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
 223
 224    if (dst_flip)
 225       dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
 226
 227    int src_pitch = src_mt->region->pitch;
 228    if (src_flip != dst_flip)
 229       src_pitch = -src_pitch;
 230
 231    uint32_t src_image_x, src_image_y;
 232    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 233                                   &src_image_x, &src_image_y);
 234    src_x += src_image_x;
 235    src_y += src_image_y;
 236
 237    /* The blitter interprets the 16-bit src x/y as a signed 16-bit value,
 238     * where negative values are invalid.  The values we're working with are
 239     * unsigned, so make sure we don't overflow.
 240     */
 241    if (src_x >= 32768 || src_y >= 32768) {
 242       perf_debug("Falling back due to >=32k src offset (%d, %d)\n",
 243                  src_x, src_y);
 244       return false;
 245    }
 246
 247    uint32_t dst_image_x, dst_image_y;
 248    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 249                                   &dst_image_x, &dst_image_y);
 250    dst_x += dst_image_x;
 251    dst_y += dst_image_y;
 252
 253    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 254     * value.  The values we're working with are unsigned, so make sure we
 255     * don't overflow.
 256     */
 257    if (dst_x >= 32768 || dst_y >= 32768) {
 258       perf_debug("Falling back due to >=32k dst offset (%d, %d)\n",
 259                  dst_x, dst_y);
 260       return false;
 261    }
 262
 263    if (!intelEmitCopyBlit(brw,
 264                           src_mt->cpp,
 265                           src_pitch,
 266                           src_mt->region->bo, src_mt->offset,
 267                           src_mt->region->tiling,
 268                           dst_mt->region->pitch,
 269                           dst_mt->region->bo, dst_mt->offset,
 270                           dst_mt->region->tiling,
 271                           src_x, src_y,
 272                           dst_x, dst_y,
 273                           width, height,
 274                           logicop)) {
 275       return false;
 276    }
 277
 278    if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM &&
 279        dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) {
 280       intel_miptree_set_alpha_to_one(brw, dst_mt,
 281                                      dst_x, dst_y,
 282                                      width, height);
 283    }
 284
 285    return true;
 286 }
 287
 288 /* Copy BitBlt
 289  */
 290 bool
 291 intelEmitCopyBlit(struct brw_context *brw,
 292                   GLuint cpp,
 293                   GLshort src_pitch,
 294                   drm_intel_bo *src_buffer,
 295                   GLuint src_offset,
 296                   uint32_t src_tiling,
 297                   GLshort dst_pitch,
 298                   drm_intel_bo *dst_buffer,
 299                   GLuint dst_offset,
 300                   uint32_t dst_tiling,
 301                   GLshort src_x, GLshort src_y,
 302                   GLshort dst_x, GLshort dst_y,
 303                   GLshort w, GLshort h,
 304                   GLenum logic_op)
 305 {
 306    GLuint CMD, BR13, pass = 0;
 307    int dst_y2 = dst_y + h;
 308    int dst_x2 = dst_x + w;
 309    drm_intel_bo *aper_array[3];
 310    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 311    bool src_y_tiled = src_tiling == I915_TILING_Y;
 312
 313    if (dst_tiling != I915_TILING_NONE) {
 314       if (dst_offset & 4095)
 315          return false;
 316    }
 317    if (src_tiling != I915_TILING_NONE) {
 318       if (src_offset & 4095)
 319          return false;
 320    }
 321    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 322       return false;
 323
 324    /* do space check before going any further */
 325    do {
 326        aper_array[0] = brw->batch.bo;
 327        aper_array[1] = dst_buffer;
 328        aper_array[2] = src_buffer;
 329
 330        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 331            intel_batchbuffer_flush(brw);
 332            pass++;
 333        } else
 334            break;
 335    } while (pass < 2);
 336
 337    if (pass >= 2)
 338       return false;
 339
 340    intel_batchbuffer_require_space(brw, 8 * 4, BLT_RING);
 341    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 342        __FUNCTION__,
 343        src_buffer, src_pitch, src_offset, src_x, src_y,
 344        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 345
 346    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 347     * the low bits.
 348     */
 349    if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
 350       return false;
 351
 352    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 353     * and multiply the coordinates.
 354     */
 355    if (cpp > 4) {
 356       if (cpp % 4 == 2) {
 357          dst_x *= cpp / 2;
 358          dst_x2 *= cpp / 2;
 359          src_x *= cpp / 2;
 360          cpp = 2;
 361       } else {
 362          assert(cpp % 4 == 0);
 363          dst_x *= cpp / 4;
 364          dst_x2 *= cpp / 4;
 365          src_x *= cpp / 4;
 366          cpp = 4;
 367       }
 368    }
 369
 370    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 371
 372    switch (cpp) {
 373    case 1:
 374    case 2:
 375       CMD = XY_SRC_COPY_BLT_CMD;
 376       break;
 377    case 4:
 378       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 379       break;
 380    default:
 381       return false;
 382    }
 383
 384    if (dst_tiling != I915_TILING_NONE) {
 385       CMD |= XY_DST_TILED;
 386       dst_pitch /= 4;
 387    }
 388    if (src_tiling != I915_TILING_NONE) {
 389       CMD |= XY_SRC_TILED;
 390       src_pitch /= 4;
 391    }
 392
 393    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 394       return true;
 395    }
 396
 397    assert(dst_x < dst_x2);
 398    assert(dst_y < dst_y2);
 399    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 400           (w * cpp) <= src_buffer->size);
 401    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 402           (w * cpp) <= dst_buffer->size);
 403
 404    unsigned length = brw->gen >= 8 ? 10 : 8;
 405
 406    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 407    OUT_BATCH(CMD | (length - 2));
 408    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 409    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 410    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 411    if (brw->gen >= 8) {
 412       OUT_RELOC64(dst_buffer,
 413                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 414                   dst_offset);
 415    } else {
 416       OUT_RELOC(dst_buffer,
 417                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 418                 dst_offset);
 419    }
 420    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 421    OUT_BATCH((uint16_t)src_pitch);
 422    if (brw->gen >= 8) {
 423       OUT_RELOC64(src_buffer,
 424                   I915_GEM_DOMAIN_RENDER, 0,
 425                   src_offset);
 426    } else {
 427       OUT_RELOC(src_buffer,
 428                 I915_GEM_DOMAIN_RENDER, 0,
 429                 src_offset);
 430    }
 431
 432    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 433
 434    intel_batchbuffer_emit_mi_flush(brw);
 435
 436    return true;
 437 }
 438
 439 bool
 440 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 441                                   GLuint cpp,
 442                                   GLubyte *src_bits, GLuint src_size,
 443                                   GLuint fg_color,
 444                                   GLshort dst_pitch,
 445                                   drm_intel_bo *dst_buffer,
 446                                   GLuint dst_offset,
 447                                   uint32_t dst_tiling,
 448                                   GLshort x, GLshort y,
 449                                   GLshort w, GLshort h,
 450                                   GLenum logic_op)
 451 {
 452    int dwords = ALIGN(src_size, 8) / 4;
 453    uint32_t opcode, br13, blit_cmd;
 454
 455    if (dst_tiling != I915_TILING_NONE) {
 456       if (dst_offset & 4095)
 457          return false;
 458       if (dst_tiling == I915_TILING_Y)
 459          return false;
 460    }
 461
 462    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 463    assert(dst_pitch > 0);
 464
 465    if (w < 0 || h < 0)
 466       return true;
 467
 468    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 469        __FUNCTION__,
 470        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 471
 472    intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, BLT_RING);
 473
 474    opcode = XY_SETUP_BLT_CMD;
 475    if (cpp == 4)
 476       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 477    if (dst_tiling != I915_TILING_NONE) {
 478       opcode |= XY_DST_TILED;
 479       dst_pitch /= 4;
 480    }
 481
 482    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 483    br13 |= br13_for_cpp(cpp);
 484
 485    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 486    if (dst_tiling != I915_TILING_NONE)
 487       blit_cmd |= XY_DST_TILED;
 488
 489    unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
 490
 491    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 492    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 493    OUT_BATCH(br13);
 494    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 495    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 496    if (brw->gen >= 8) {
 497       OUT_RELOC64(dst_buffer,
 498                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 499                   dst_offset);
 500    } else {
 501       OUT_RELOC(dst_buffer,
 502                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 503                 dst_offset);
 504    }
 505    OUT_BATCH(0); /* bg */
 506    OUT_BATCH(fg_color); /* fg */
 507    OUT_BATCH(0); /* pattern base addr */
 508    if (brw->gen >= 8)
 509       OUT_BATCH(0);
 510
 511    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 512    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 513    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 514    ADVANCE_BATCH();
 515
 516    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 517
 518    intel_batchbuffer_emit_mi_flush(brw);
 519
 520    return true;
 521 }
 522
 523 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 524  * rectangular blit covering a large space, then emit 1-scanline blit at the
 525  * end to cover the last if we need.
 526  */
 527 void
 528 intel_emit_linear_blit(struct brw_context *brw,
 529                        drm_intel_bo *dst_bo,
 530                        unsigned int dst_offset,
 531                        drm_intel_bo *src_bo,
 532                        unsigned int src_offset,
 533                        unsigned int size)
 534 {
 535    struct gl_context *ctx = &brw->ctx;
 536    GLuint pitch, height;
 537    bool ok;
 538
 539    /* The pitch given to the GPU must be DWORD aligned, and
 540     * we want width to match pitch. Max width is (1 << 15 - 1),
 541     * rounding that down to the nearest DWORD is 1 << 15 - 4
 542     */
 543    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 544    height = (pitch == 0) ? 1 : size / pitch;
 545    ok = intelEmitCopyBlit(brw, 1,
 546                           pitch, src_bo, src_offset, I915_TILING_NONE,
 547                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 548                           0, 0, /* src x/y */
 549                           0, 0, /* dst x/y */
 550                           pitch, height, /* w, h */
 551                           GL_COPY);
 552    if (!ok)
 553       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 554
 555    src_offset += pitch * height;
 556    dst_offset += pitch * height;
 557    size -= pitch * height;
 558    assert (size < (1 << 15));
 559    pitch = ALIGN(size, 4);
 560    if (size != 0) {
 561       ok = intelEmitCopyBlit(brw, 1,
 562                              pitch, src_bo, src_offset, I915_TILING_NONE,
 563                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 564                              0, 0, /* src x/y */
 565                              0, 0, /* dst x/y */
 566                              size, 1, /* w, h */
 567                              GL_COPY);
 568       if (!ok)
 569          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 570    }
 571 }
 572
 573 /**
 574  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 575  * into it from an XRGB8888 source.
 576  *
 577  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 578  * relative to the start of the miptree, not relative to a slice within the
 579  * miptree.
 580  */
 581 static void
 582 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 583                               struct intel_mipmap_tree *mt,
 584                               int x, int y, int width, int height)
 585 {
 586    struct intel_region *region = mt->region;
 587    uint32_t BR13, CMD;
 588    int pitch, cpp;
 589    drm_intel_bo *aper_array[2];
 590
 591    pitch = region->pitch;
 592    cpp = region->cpp;
 593
 594    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 595        __FUNCTION__, region->bo, pitch, x, y, width, height);
 596
 597    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 598    CMD = XY_COLOR_BLT_CMD;
 599    CMD |= XY_BLT_WRITE_ALPHA;
 600
 601    if (region->tiling != I915_TILING_NONE) {
 602       CMD |= XY_DST_TILED;
 603       pitch /= 4;
 604    }
 605    BR13 |= pitch;
 606
 607    /* do space check before going any further */
 608    aper_array[0] = brw->batch.bo;
 609    aper_array[1] = region->bo;
 610
 611    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 612                                              ARRAY_SIZE(aper_array)) != 0) {
 613       intel_batchbuffer_flush(brw);
 614    }
 615
 616    unsigned length = brw->gen >= 8 ? 7 : 6;
 617    bool dst_y_tiled = region->tiling == I915_TILING_Y;
 618
 619    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 620    OUT_BATCH(CMD | (length - 2));
 621    OUT_BATCH(BR13);
 622    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 623    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
 624    if (brw->gen >= 8) {
 625       OUT_RELOC64(region->bo,
 626                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 627                   0);
 628    } else {
 629       OUT_RELOC(region->bo,
 630                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 631                 0);
 632    }
 633    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 634    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 635
 636    intel_batchbuffer_emit_mi_flush(brw);
 637 }