src/mesa/drivers/dri/i965/intel_extensions.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/version.h"
  29
  30 #include "brw_context.h"
  31 #include "intel_batchbuffer.h"
  32 #include "intel_reg.h"
  33 #include "utils.h"
  34
  35 /**
  36  * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
  37  *
  38  * Some combinations of hardware and kernel versions allow this feature,
  39  * while others don't.  Instead of trying to enumerate every case, just
  40  * try and write a register and see if works.
  41  */
  42 static bool
  43 can_do_pipelined_register_writes(struct brw_context *brw)
  44 {
  45    /* Supposedly, Broadwell just works. */
  46    if (brw->gen >= 8)
  47       return true;
  48
  49    /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
  50     * statistics registers), and we already reset it to zero before using it.
  51     */
  52    const int reg = GEN7_SO_WRITE_OFFSET(0);
  53    const int expected_value = 0x1337d0d0;
  54    const int offset = 100;
  55
  56    /* The register we picked only exists on Gen7+. */
  57    assert(brw->gen == 7);
  58
  59    uint32_t *data;
  60    /* Set a value in a BO to a known quantity.  The workaround BO already
  61     * exists and doesn't contain anything important, so we may as well use it.
  62     */
  63    drm_intel_bo_map(brw->batch.workaround_bo, true);
  64    data = brw->batch.workaround_bo->virtual;
  65    data[offset] = 0xffffffff;
  66    drm_intel_bo_unmap(brw->batch.workaround_bo);
  67
  68    /* Write the register. */
  69    BEGIN_BATCH(3);
  70    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  71    OUT_BATCH(reg);
  72    OUT_BATCH(expected_value);
  73    ADVANCE_BATCH();
  74
  75    intel_batchbuffer_emit_mi_flush(brw);
  76
  77    /* Save the register's value back to the buffer. */
  78    BEGIN_BATCH(3);
  79    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
  80    OUT_BATCH(reg);
  81    OUT_RELOC(brw->batch.workaround_bo,
  82              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  83              offset * sizeof(uint32_t));
  84    ADVANCE_BATCH();
  85
  86    intel_batchbuffer_flush(brw);
  87
  88    /* Check whether the value got written. */
  89    drm_intel_bo_map(brw->batch.workaround_bo, false);
  90    bool success = data[offset] == expected_value;
  91    drm_intel_bo_unmap(brw->batch.workaround_bo);
  92
  93    return success;
  94 }
  95
  96 static bool
  97 can_write_oacontrol(struct brw_context *brw)
  98 {
  99    if (brw->gen < 6 || brw->gen >= 8)
 100       return false;
 101
 102    /* Set "Select Context ID" to a particular address (which is likely not a
 103     * context), but leave all counting disabled.  This should be harmless.
 104     */
 105    const int expected_value = 0x31337000;
 106    const int offset = 110;
 107
 108    uint32_t *data;
 109    /* Set a value in a BO to a known quantity.  The workaround BO already
 110     * exists and doesn't contain anything important, so we may as well use it.
 111     */
 112    drm_intel_bo_map(brw->batch.workaround_bo, true);
 113    data = brw->batch.workaround_bo->virtual;
 114    data[offset] = 0xffffffff;
 115    drm_intel_bo_unmap(brw->batch.workaround_bo);
 116
 117    /* Write OACONTROL. */
 118    BEGIN_BATCH(3);
 119    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 120    OUT_BATCH(OACONTROL);
 121    OUT_BATCH(expected_value);
 122    ADVANCE_BATCH();
 123
 124    intel_batchbuffer_emit_mi_flush(brw);
 125
 126    /* Save the register's value back to the buffer. */
 127    BEGIN_BATCH(3);
 128    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
 129    OUT_BATCH(OACONTROL);
 130    OUT_RELOC(brw->batch.workaround_bo,
 131              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 132              offset * sizeof(uint32_t));
 133    ADVANCE_BATCH();
 134
 135    intel_batchbuffer_emit_mi_flush(brw);
 136
 137    /* Set OACONTROL back to zero (everything off). */
 138    BEGIN_BATCH(3);
 139    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 140    OUT_BATCH(OACONTROL);
 141    OUT_BATCH(0);
 142    ADVANCE_BATCH();
 143
 144    intel_batchbuffer_flush(brw);
 145
 146    /* Check whether the value got written. */
 147    drm_intel_bo_map(brw->batch.workaround_bo, false);
 148    bool success = data[offset] == expected_value;
 149    drm_intel_bo_unmap(brw->batch.workaround_bo);
 150
 151    return success;
 152 }
 153
 154 /**
 155  * Initializes potential list of extensions if ctx == NULL, or actually enables
 156  * extensions for a context.
 157  */
 158 void
 159 intelInitExtensions(struct gl_context *ctx)
 160 {
 161    struct brw_context *brw = brw_context(ctx);
 162
 163    assert(brw->gen >= 4);
 164
 165    ctx->Extensions.ARB_depth_buffer_float = true;
 166    ctx->Extensions.ARB_depth_clamp = true;
 167    ctx->Extensions.ARB_depth_texture = true;
 168    ctx->Extensions.ARB_draw_elements_base_vertex = true;
 169    ctx->Extensions.ARB_draw_instanced = true;
 170    ctx->Extensions.ARB_ES2_compatibility = true;
 171    ctx->Extensions.ARB_explicit_attrib_location = true;
 172    ctx->Extensions.ARB_fragment_coord_conventions = true;
 173    ctx->Extensions.ARB_fragment_program = true;
 174    ctx->Extensions.ARB_fragment_program_shadow = true;
 175    ctx->Extensions.ARB_fragment_shader = true;
 176    ctx->Extensions.ARB_framebuffer_object = true;
 177    ctx->Extensions.ARB_half_float_pixel = true;
 178    ctx->Extensions.ARB_half_float_vertex = true;
 179    ctx->Extensions.ARB_instanced_arrays = true;
 180    ctx->Extensions.ARB_internalformat_query = true;
 181    ctx->Extensions.ARB_map_buffer_range = true;
 182    ctx->Extensions.ARB_occlusion_query = true;
 183    ctx->Extensions.ARB_occlusion_query2 = true;
 184    ctx->Extensions.ARB_point_sprite = true;
 185    ctx->Extensions.ARB_seamless_cube_map = true;
 186    ctx->Extensions.ARB_shader_bit_encoding = true;
 187    ctx->Extensions.ARB_shader_texture_lod = true;
 188    ctx->Extensions.ARB_shadow = true;
 189    ctx->Extensions.ARB_sync = true;
 190    ctx->Extensions.ARB_texture_border_clamp = true;
 191    ctx->Extensions.ARB_texture_compression_rgtc = true;
 192    ctx->Extensions.ARB_texture_cube_map = true;
 193    ctx->Extensions.ARB_texture_env_combine = true;
 194    ctx->Extensions.ARB_texture_env_crossbar = true;
 195    ctx->Extensions.ARB_texture_env_dot3 = true;
 196    ctx->Extensions.ARB_texture_float = true;
 197    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
 198    ctx->Extensions.ARB_texture_non_power_of_two = true;
 199    ctx->Extensions.ARB_texture_rg = true;
 200    ctx->Extensions.ARB_texture_rgb10_a2ui = true;
 201    ctx->Extensions.ARB_vertex_program = true;
 202    ctx->Extensions.ARB_vertex_shader = true;
 203    ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
 204    ctx->Extensions.EXT_blend_color = true;
 205    ctx->Extensions.EXT_blend_equation_separate = true;
 206    ctx->Extensions.EXT_blend_func_separate = true;
 207    ctx->Extensions.EXT_blend_minmax = true;
 208    ctx->Extensions.EXT_draw_buffers2 = true;
 209    ctx->Extensions.EXT_framebuffer_blit = true;
 210    ctx->Extensions.EXT_framebuffer_sRGB = true;
 211    ctx->Extensions.EXT_gpu_program_parameters = true;
 212    ctx->Extensions.EXT_packed_depth_stencil = true;
 213    ctx->Extensions.EXT_packed_float = true;
 214    ctx->Extensions.EXT_pixel_buffer_object = true;
 215    ctx->Extensions.EXT_point_parameters = true;
 216    ctx->Extensions.EXT_provoking_vertex = true;
 217    ctx->Extensions.EXT_separate_shader_objects = true;
 218    ctx->Extensions.EXT_texture_array = true;
 219    ctx->Extensions.EXT_texture_env_dot3 = true;
 220    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 221    ctx->Extensions.EXT_texture_integer = true;
 222    ctx->Extensions.EXT_texture_shared_exponent = true;
 223    ctx->Extensions.EXT_texture_snorm = true;
 224    ctx->Extensions.EXT_texture_sRGB = true;
 225    ctx->Extensions.EXT_texture_sRGB_decode = true;
 226    ctx->Extensions.EXT_texture_swizzle = true;
 227    ctx->Extensions.EXT_stencil_two_side = true;
 228    ctx->Extensions.EXT_vertex_array_bgra = true;
 229    ctx->Extensions.AMD_seamless_cubemap_per_texture = true;
 230    ctx->Extensions.APPLE_object_purgeable = true;
 231    ctx->Extensions.ATI_envmap_bumpmap = true;
 232    ctx->Extensions.ATI_separate_stencil = true;
 233    ctx->Extensions.ATI_texture_env_combine3 = true;
 234    ctx->Extensions.MESA_pack_invert = true;
 235    ctx->Extensions.MESA_texture_array = true;
 236    ctx->Extensions.MESA_ycbcr_texture = true;
 237    ctx->Extensions.NV_conditional_render = true;
 238    ctx->Extensions.NV_primitive_restart = true;
 239    ctx->Extensions.NV_texture_env_combine4 = true;
 240    ctx->Extensions.NV_texture_rectangle = true;
 241    ctx->Extensions.TDFX_texture_compression_FXT1 = true;
 242    ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
 243    ctx->Extensions.OES_EGL_image = true;
 244    ctx->Extensions.OES_draw_texture = true;
 245    ctx->Extensions.OES_standard_derivatives = true;
 246    ctx->Extensions.OES_EGL_image_external = true;
 247
 248    if (brw->gen >= 7)
 249       ctx->Const.GLSLVersion = 330;
 250    else if (brw->gen >= 6)
 251       ctx->Const.GLSLVersion = 140;
 252    else
 253       ctx->Const.GLSLVersion = 120;
 254    _mesa_override_glsl_version(ctx);
 255
 256    if (brw->gen >= 6) {
 257       uint64_t dummy;
 258
 259       ctx->Extensions.EXT_framebuffer_multisample = true;
 260       ctx->Extensions.EXT_transform_feedback = true;
 261       ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
 262       ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
 263       ctx->Extensions.ARB_draw_buffers_blend = true;
 264       ctx->Extensions.ARB_ES3_compatibility = true;
 265       ctx->Extensions.ARB_uniform_buffer_object = true;
 266       ctx->Extensions.ARB_shading_language_420pack = true;
 267       ctx->Extensions.ARB_texture_buffer_object = true;
 268       ctx->Extensions.ARB_texture_buffer_object_rgb32 = true;
 269       ctx->Extensions.ARB_texture_buffer_range = true;
 270       ctx->Extensions.ARB_texture_cube_map_array = true;
 271       ctx->Extensions.OES_depth_texture_cube_map = true;
 272       ctx->Extensions.ARB_shading_language_packing = true;
 273       ctx->Extensions.ARB_texture_multisample = true;
 274       ctx->Extensions.ARB_sample_shading = true;
 275       ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true;
 276
 277       /* Test if the kernel has the ioctl. */
 278       if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0)
 279          ctx->Extensions.ARB_timer_query = true;
 280    }
 281
 282    if (brw->gen >= 5) {
 283       ctx->Extensions.ARB_texture_query_lod = true;
 284       ctx->Extensions.EXT_timer_query = true;
 285       ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
 286       ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;
 287    }
 288
 289    if (brw->gen >= 7) {
 290       ctx->Extensions.ARB_texture_gather = true;
 291       ctx->Extensions.ARB_conservative_depth = true;
 292       ctx->Extensions.AMD_vertex_shader_layer = true;
 293       if (can_do_pipelined_register_writes(brw)) {
 294          ctx->Extensions.ARB_transform_feedback2 = true;
 295          ctx->Extensions.ARB_transform_feedback3 = true;
 296          ctx->Extensions.ARB_transform_feedback_instanced = true;
 297          ctx->Extensions.ARB_draw_indirect = true;
 298       }
 299    }
 300
 301    if (brw->gen == 5 || can_write_oacontrol(brw))
 302       ctx->Extensions.AMD_performance_monitor = true;
 303
 304    if (ctx->API == API_OPENGL_CORE)
 305       ctx->Extensions.ARB_base_instance = true;
 306    if (ctx->API != API_OPENGL_CORE)
 307       ctx->Extensions.ARB_color_buffer_float = true;
 308
 309    if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
 310       ctx->Extensions.EXT_texture_compression_s3tc = true;
 311
 312    ctx->Extensions.ANGLE_texture_compression_dxt = true;
 313
 314    if (brw->gen >= 7)
 315       ctx->Extensions.ARB_shader_atomic_counters = true;
 316 }