2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
67 /* MCS compression only applies to multisampled miptrees */
68 if (mt
->surf
.samples
<= 1)
71 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
75 /* See isl_surf_get_mcs_surf for details. */
76 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(mt
->format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
106 intel_tiling_supports_ccs(const struct brw_context
*brw
,
107 enum isl_tiling tiling
)
109 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
111 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
112 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
114 * - Support is limited to tiled render targets.
116 * Gen9 changes the restriction to Y-tile only.
118 if (devinfo
->gen
>= 9)
119 return tiling
== ISL_TILING_Y0
;
120 else if (devinfo
->gen
>= 7)
121 return tiling
!= ISL_TILING_LINEAR
;
127 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
128 * can be used. This doesn't (and should not) inspect any of the properties of
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p326):
134 * - Support is for non-mip-mapped and non-array surface types only.
136 * And then later, on p327:
138 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
141 * From the Skylake documentation, it is made clear that X-tiling is no longer
144 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
148 intel_miptree_supports_ccs(struct brw_context
*brw
,
149 const struct intel_mipmap_tree
*mt
)
151 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
153 /* MCS support does not exist prior to Gen7 */
154 if (devinfo
->gen
< 7)
157 /* This function applies only to non-multisampled render targets. */
158 if (mt
->surf
.samples
> 1)
161 /* MCS is only supported for color buffers */
162 if (!_mesa_is_format_color_format(mt
->format
))
165 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
168 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
169 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
170 mt
->surf
.logical_level0_px
.depth
> 1;
173 /* Multisample surfaces with the CMS layout are not layered surfaces,
174 * yet still have physical_depth0 > 1. Assert that we don't
175 * accidentally reject a multisampled surface here. We should have
176 * rejected it earlier by explicitly checking the sample count.
178 assert(mt
->surf
.samples
== 1);
181 /* Handle the hardware restrictions...
183 * All GENs have the following restriction: "MCS buffer for non-MSRT is
184 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
186 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
187 * Non-MultiSampler Render Target Restrictions) Support is for
188 * non-mip-mapped and non-array surface types only.
190 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
195 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
200 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
203 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
204 * work for 3D textures until gen9 where the layout of 3D textures changes
205 * to match 2D array textures.
207 if (devinfo
->gen
<= 8 && mt
->surf
.dim
!= ISL_SURF_DIM_2D
)
210 /* There's no point in using an MCS buffer if the surface isn't in a
213 if (!brw
->mesa_format_supports_render
[mt
->format
])
220 intel_tiling_supports_hiz(const struct brw_context
*brw
,
221 enum isl_tiling tiling
)
223 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
225 if (devinfo
->gen
< 6)
228 return tiling
== ISL_TILING_Y0
;
232 intel_miptree_supports_hiz(const struct brw_context
*brw
,
233 const struct intel_mipmap_tree
*mt
)
238 switch (mt
->format
) {
239 case MESA_FORMAT_Z_FLOAT32
:
240 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
241 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
242 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
243 case MESA_FORMAT_Z_UNORM16
:
251 * Return true if the format that will be used to access the miptree is
252 * CCS_E-compatible with the miptree's linear/non-sRGB format.
254 * Why use the linear format? Well, although the miptree may be specified with
255 * an sRGB format, the usage of that color space/format can be toggled. Since
256 * our HW tends to support more linear formats than sRGB ones, we use this
257 * format variant for check for CCS_E compatibility.
260 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
261 const struct intel_mipmap_tree
*mt
,
262 enum isl_format access_format
)
264 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
266 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
267 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
268 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
272 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
273 const struct intel_mipmap_tree
*mt
)
275 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
277 if (devinfo
->gen
< 9)
280 /* For now compression is only enabled for integer formats even though
281 * there exist supported floating point formats also. This is a heuristic
282 * decision based on current public benchmarks. In none of the cases these
283 * formats provided any improvement but a few cases were seen to regress.
284 * Hence these are left to to be enabled in the future when they are known
287 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
290 if (!intel_miptree_supports_ccs(brw
, mt
))
293 /* Many window system buffers are sRGB even if they are never rendered as
294 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
295 * surface is used as sRGB, we fall back to CCS_D.
297 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
298 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
299 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
303 * Determine depth format corresponding to a depth+stencil format,
304 * for separate stencil.
307 intel_depth_format_for_depthstencil_format(mesa_format format
) {
309 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
310 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
311 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
312 return MESA_FORMAT_Z_FLOAT32
;
319 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
320 unsigned depth0
, struct intel_mipmap_level
*table
)
322 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
324 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
326 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
327 if (!table
[level
].slice
)
334 for (unsigned level
= first_level
; level
<= last_level
; level
++)
335 free(table
[level
].slice
);
341 needs_separate_stencil(const struct brw_context
*brw
,
342 struct intel_mipmap_tree
*mt
,
345 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
347 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
350 if (devinfo
->must_use_separate_stencil
)
353 return brw
->has_separate_stencil
&&
354 intel_miptree_supports_hiz(brw
, mt
);
358 * Choose the aux usage for this miptree. This function must be called fairly
359 * late in the miptree create process after we have a tiling.
362 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
363 struct intel_mipmap_tree
*mt
)
365 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
367 if (intel_miptree_supports_mcs(brw
, mt
)) {
368 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
369 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
370 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
371 intel_miptree_supports_ccs(brw
, mt
)) {
372 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
373 intel_miptree_supports_ccs_e(brw
, mt
)) {
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
378 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
379 intel_miptree_supports_hiz(brw
, mt
)) {
380 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
383 /* We can do fast-clear on all auxiliary surface types that are
384 * allocated through the normal texture creation paths.
386 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
387 mt
->supports_fast_clear
= true;
392 * Choose an appropriate uncompressed format for a requested
393 * compressed format, if unsupported.
396 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
398 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
400 /* No need to lower ETC formats on these platforms,
401 * they are supported natively.
403 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
407 case MESA_FORMAT_ETC1_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_SRGB8
:
412 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
413 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
414 return MESA_FORMAT_B8G8R8A8_SRGB
;
415 case MESA_FORMAT_ETC2_RGBA8_EAC
:
416 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
417 return MESA_FORMAT_R8G8B8A8_UNORM
;
418 case MESA_FORMAT_ETC2_R11_EAC
:
419 return MESA_FORMAT_R_UNORM16
;
420 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
421 return MESA_FORMAT_R_SNORM16
;
422 case MESA_FORMAT_ETC2_RG11_EAC
:
423 return MESA_FORMAT_R16G16_UNORM
;
424 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
425 return MESA_FORMAT_R16G16_SNORM
;
427 /* Non ETC1 / ETC2 format */
433 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
435 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
436 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
438 return mt
->surf
.logical_level0_px
.array_len
;
441 UNUSED
static unsigned
442 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
444 /* In case of physical dimensions one needs to consider also the layout.
445 * See isl_calc_phys_level0_extent_sa().
447 if (surf
->dim
!= ISL_SURF_DIM_3D
)
448 return surf
->phys_level0_sa
.array_len
;
450 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
451 return minify(surf
->phys_level0_sa
.array_len
, level
);
453 return minify(surf
->phys_level0_sa
.depth
, level
);
456 /** \brief Assert that the level and layer are valid for the miptree. */
458 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
466 assert(level
>= mt
->first_level
);
467 assert(level
<= mt
->last_level
);
468 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
471 static enum isl_aux_state
**
472 create_aux_state_map(struct intel_mipmap_tree
*mt
,
473 enum isl_aux_state initial
)
475 const uint32_t levels
= mt
->last_level
+ 1;
477 uint32_t total_slices
= 0;
478 for (uint32_t level
= 0; level
< levels
; level
++)
479 total_slices
+= brw_get_num_logical_layers(mt
, level
);
481 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
483 /* We're going to allocate a single chunk of data for both the per-level
484 * reference array and the arrays of aux_state. This makes cleanup
485 * significantly easier.
487 const size_t total_size
= per_level_array_size
+
488 total_slices
* sizeof(enum isl_aux_state
);
489 void *data
= malloc(total_size
);
493 enum isl_aux_state
**per_level_arr
= data
;
494 enum isl_aux_state
*s
= data
+ per_level_array_size
;
495 for (uint32_t level
= 0; level
< levels
; level
++) {
496 per_level_arr
[level
] = s
;
497 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
498 for (uint32_t a
= 0; a
< level_layers
; a
++)
501 assert((void *)s
== data
+ total_size
);
503 return per_level_arr
;
507 free_aux_state_map(enum isl_aux_state
**state
)
513 need_to_retile_as_linear(struct brw_context
*brw
, unsigned blt_pitch
,
514 enum isl_tiling tiling
, unsigned samples
)
519 if (tiling
== ISL_TILING_LINEAR
)
522 if (blt_pitch
>= 32768) {
523 perf_debug("blt pitch %u too large to blit, falling back to untiled",
532 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
533 enum isl_tiling tiling
)
535 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
537 /* If the BO is too large to fit in the aperture, we need to use the
538 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
539 * handle Y-tiling, so we need to fall back to X.
541 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
542 tiling
== ISL_TILING_Y0
)
548 static struct intel_mipmap_tree
*
549 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
550 unsigned first_level
, unsigned last_level
,
551 unsigned width0
, unsigned height0
, unsigned depth0
,
552 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
553 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
554 unsigned row_pitch
, struct brw_bo
*bo
)
556 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
560 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
568 if (target
== GL_TEXTURE_CUBE_MAP
||
569 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
570 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
572 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
574 _mesa_enum_to_string(target
),
575 _mesa_get_format_name(format
),
576 num_samples
, width0
, height0
, depth0
,
577 first_level
, last_level
, mt
);
579 struct isl_surf_init_info init_info
= {
580 .dim
= get_isl_surf_dim(target
),
581 .format
= translate_tex_format(brw
, format
, false),
584 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
585 .levels
= last_level
- first_level
+ 1,
586 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
587 .samples
= num_samples
,
588 .row_pitch
= row_pitch
,
589 .usage
= isl_usage_flags
,
590 .tiling_flags
= tiling_flags
,
593 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
596 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
597 * on gen7 platforms we also need to create Y-tiled copies of stencil for
598 * texturing since the hardware can't sample from W-tiled surfaces. For
599 * everything else, check for corner cases needing special treatment.
601 bool is_depth_stencil
=
602 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
603 if (!is_depth_stencil
) {
604 if (need_to_retile_as_linear(brw
, intel_miptree_blt_pitch(mt
),
605 mt
->surf
.tiling
, mt
->surf
.samples
)) {
606 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
607 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
609 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
610 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
611 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
616 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
617 * the size may not be multiple of row_pitch.
618 * See isl_apply_surface_padding().
620 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
621 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
624 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
627 isl_tiling_to_i915_tiling(
629 mt
->surf
.row_pitch
, alloc_flags
);
636 mt
->first_level
= first_level
;
637 mt
->last_level
= last_level
;
640 mt
->aux_state
= NULL
;
641 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
642 mt
->compressed
= _mesa_is_format_compressed(format
);
643 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
648 intel_miptree_release(&mt
);
653 make_separate_stencil_surface(struct brw_context
*brw
,
654 struct intel_mipmap_tree
*mt
)
656 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
657 0, mt
->surf
.levels
- 1,
658 mt
->surf
.logical_level0_px
.width
,
659 mt
->surf
.logical_level0_px
.height
,
660 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
661 mt
->surf
.logical_level0_px
.depth
:
662 mt
->surf
.logical_level0_px
.array_len
,
663 mt
->surf
.samples
, ISL_TILING_W_BIT
,
664 ISL_SURF_USAGE_STENCIL_BIT
|
665 ISL_SURF_USAGE_TEXTURE_BIT
,
666 BO_ALLOC_BUSY
, 0, NULL
);
671 mt
->stencil_mt
->r8stencil_needs_update
= true;
676 static struct intel_mipmap_tree
*
677 miptree_create(struct brw_context
*brw
,
686 enum intel_miptree_create_flags flags
)
688 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
689 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
691 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
692 if (devinfo
->gen
< 6 && _mesa_is_format_color_format(format
))
693 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
695 if (format
== MESA_FORMAT_S_UINT8
)
696 return make_surface(brw
, target
, format
, first_level
, last_level
,
697 width0
, height0
, depth0
, num_samples
,
699 ISL_SURF_USAGE_STENCIL_BIT
|
700 ISL_SURF_USAGE_TEXTURE_BIT
,
705 const GLenum base_format
= _mesa_get_format_base_format(format
);
706 if ((base_format
== GL_DEPTH_COMPONENT
||
707 base_format
== GL_DEPTH_STENCIL
)) {
708 /* Fix up the Z miptree format for how we're splitting out separate
709 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
711 const mesa_format depth_only_format
=
712 intel_depth_format_for_depthstencil_format(format
);
713 struct intel_mipmap_tree
*mt
= make_surface(
714 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
715 first_level
, last_level
,
716 width0
, height0
, depth0
, num_samples
, tiling_flags
,
717 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
718 BO_ALLOC_BUSY
, 0, NULL
);
720 if (needs_separate_stencil(brw
, mt
, format
) &&
721 !make_separate_stencil_surface(brw
, mt
)) {
722 intel_miptree_release(&mt
);
726 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
727 intel_miptree_choose_aux_usage(brw
, mt
);
732 mesa_format tex_format
= format
;
733 mesa_format etc_format
= MESA_FORMAT_NONE
;
734 uint32_t alloc_flags
= 0;
736 format
= intel_lower_compressed_format(brw
, format
);
738 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
740 if (flags
& MIPTREE_CREATE_BUSY
)
741 alloc_flags
|= BO_ALLOC_BUSY
;
743 struct intel_mipmap_tree
*mt
= make_surface(
745 first_level
, last_level
,
746 width0
, height0
, depth0
,
747 num_samples
, tiling_flags
,
748 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
749 ISL_SURF_USAGE_TEXTURE_BIT
,
750 alloc_flags
, 0, NULL
);
754 mt
->etc_format
= etc_format
;
756 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
757 intel_miptree_choose_aux_usage(brw
, mt
);
762 struct intel_mipmap_tree
*
763 intel_miptree_create(struct brw_context
*brw
,
772 enum intel_miptree_create_flags flags
)
774 assert(num_samples
> 0);
776 struct intel_mipmap_tree
*mt
= miptree_create(
778 first_level
, last_level
,
779 width0
, height0
, depth0
, num_samples
,
786 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
787 * compress clear color so we wait until an actual fast-clear to allocate
790 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
791 !intel_miptree_alloc_aux(brw
, mt
)) {
792 intel_miptree_release(&mt
);
799 struct intel_mipmap_tree
*
800 intel_miptree_create_for_bo(struct brw_context
*brw
,
808 enum isl_tiling tiling
,
809 enum intel_miptree_create_flags flags
)
811 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
812 struct intel_mipmap_tree
*mt
;
813 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
814 const GLenum base_format
= _mesa_get_format_base_format(format
);
816 if ((base_format
== GL_DEPTH_COMPONENT
||
817 base_format
== GL_DEPTH_STENCIL
)) {
818 const mesa_format depth_only_format
=
819 intel_depth_format_for_depthstencil_format(format
);
820 mt
= make_surface(brw
, target
,
821 devinfo
->gen
>= 6 ? depth_only_format
: format
,
822 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
823 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
828 brw_bo_reference(bo
);
830 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
831 intel_miptree_choose_aux_usage(brw
, mt
);
834 } else if (format
== MESA_FORMAT_S_UINT8
) {
835 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
836 0, 0, width
, height
, depth
, 1,
838 ISL_SURF_USAGE_STENCIL_BIT
|
839 ISL_SURF_USAGE_TEXTURE_BIT
,
844 assert(bo
->size
>= mt
->surf
.size
);
846 brw_bo_reference(bo
);
850 /* Nothing will be able to use this miptree with the BO if the offset isn't
853 if (tiling
!= ISL_TILING_LINEAR
)
854 assert(offset
% 4096 == 0);
856 /* miptrees can't handle negative pitch. If you need flipping of images,
857 * that's outside of the scope of the mt.
861 mt
= make_surface(brw
, target
, format
,
862 0, 0, width
, height
, depth
, 1,
864 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
865 ISL_SURF_USAGE_TEXTURE_BIT
,
870 brw_bo_reference(bo
);
874 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
875 intel_miptree_choose_aux_usage(brw
, mt
);
877 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
878 * only compress clear color so we wait until an actual fast-clear to
881 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
882 !intel_miptree_alloc_aux(brw
, mt
)) {
883 intel_miptree_release(&mt
);
891 static struct intel_mipmap_tree
*
892 miptree_create_for_planar_image(struct brw_context
*brw
,
893 __DRIimage
*image
, GLenum target
,
894 enum isl_tiling tiling
)
896 const struct intel_image_format
*f
= image
->planar_format
;
897 struct intel_mipmap_tree
*planar_mt
= NULL
;
899 for (int i
= 0; i
< f
->nplanes
; i
++) {
900 const int index
= f
->planes
[i
].buffer_index
;
901 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
902 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
903 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
904 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
906 /* Disable creation of the texture's aux buffers because the driver
907 * exposes no EGL API to manage them. That is, there is no API for
908 * resolving the aux buffer's content to the main buffer nor for
909 * invalidating the aux buffer's content.
911 struct intel_mipmap_tree
*mt
=
912 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
913 image
->offsets
[index
],
915 image
->strides
[index
],
917 MIPTREE_CREATE_NO_AUX
);
919 intel_miptree_release(&planar_mt
);
928 planar_mt
->plane
[i
- 1] = mt
;
931 planar_mt
->drm_modifier
= image
->modifier
;
937 create_ccs_buf_for_image(struct brw_context
*brw
,
939 struct intel_mipmap_tree
*mt
,
940 enum isl_aux_state initial_state
)
942 struct isl_surf temp_ccs_surf
;
944 /* CCS is only supported for very simple miptrees */
945 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
946 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
947 assert(mt
->surf
.samples
== 1);
948 assert(mt
->surf
.levels
== 1);
949 assert(mt
->surf
.logical_level0_px
.depth
== 1);
950 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
951 assert(mt
->first_level
== 0);
952 assert(mt
->last_level
== 0);
954 /* We shouldn't already have a CCS */
955 assert(!mt
->aux_buf
);
957 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
961 assert(image
->aux_offset
< image
->bo
->size
);
962 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
964 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
965 if (mt
->aux_buf
== NULL
)
968 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
969 if (!mt
->aux_state
) {
975 /* On gen10+ we start using an extra space in the aux buffer to store the
976 * indirect clear color. However, if we imported an image from the window
977 * system with CCS, we don't have the extra space at the end of the aux
978 * buffer. So create a new bo here that will store that clear color.
980 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
981 mt
->aux_buf
->clear_color_bo
=
982 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
983 brw
->isl_dev
.ss
.clear_color_state_size
,
984 BRW_MEMZONE_OTHER
, I915_TILING_NONE
, 0,
986 if (!mt
->aux_buf
->clear_color_bo
) {
993 mt
->aux_buf
->bo
= image
->bo
;
994 brw_bo_reference(image
->bo
);
996 mt
->aux_buf
->offset
= image
->aux_offset
;
997 mt
->aux_buf
->surf
= temp_ccs_surf
;
1002 struct intel_mipmap_tree
*
1003 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1004 __DRIimage
*image
, GLenum target
,
1006 bool allow_internal_aux
)
1008 uint32_t bo_tiling
, bo_swizzle
;
1009 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1011 const struct isl_drm_modifier_info
*mod_info
=
1012 isl_drm_modifier_get_info(image
->modifier
);
1014 const enum isl_tiling tiling
=
1015 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1017 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1018 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1020 if (image
->planar_format
)
1021 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1023 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1024 /* The texture storage paths in core Mesa detect if the driver does not
1025 * support the user-requested format, and then searches for a
1026 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1027 * do the fallbacks here for important formats.
1029 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1030 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1031 * the Chrome OS compositor consumes as dma_buf EGLImages.
1033 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1036 if (!brw
->ctx
.TextureFormatSupported
[format
])
1039 enum intel_miptree_create_flags mt_create_flags
= 0;
1041 /* If this image comes in from a window system, we have different
1042 * requirements than if it comes in via an EGL import operation. Window
1043 * system images can use any form of auxiliary compression we wish because
1044 * they get "flushed" before being handed off to the window system and we
1045 * have the opportunity to do resolves. Non window-system images, on the
1046 * other hand, have no resolve point so we can't have aux without a
1049 if (!allow_internal_aux
)
1050 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1052 /* If we have a modifier which specifies aux, don't create one yet */
1053 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1054 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1056 /* Disable creation of the texture's aux buffers because the driver exposes
1057 * no EGL API to manage them. That is, there is no API for resolving the aux
1058 * buffer's content to the main buffer nor for invalidating the aux buffer's
1061 struct intel_mipmap_tree
*mt
=
1062 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1063 image
->offset
, image
->width
, image
->height
, 1,
1064 image
->pitch
, tiling
, mt_create_flags
);
1068 mt
->target
= target
;
1069 mt
->level
[0].level_x
= image
->tile_x
;
1070 mt
->level
[0].level_y
= image
->tile_y
;
1071 mt
->drm_modifier
= image
->modifier
;
1073 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1074 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1075 * trouble resolving back to destination image due to alignment issues.
1077 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1078 if (!devinfo
->has_surface_tile_offset
) {
1079 uint32_t draw_x
, draw_y
;
1080 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1082 if (draw_x
!= 0 || draw_y
!= 0) {
1083 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1084 intel_miptree_release(&mt
);
1089 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1090 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1092 mt
->aux_usage
= mod_info
->aux_usage
;
1093 /* If we are a window system buffer, then we can support fast-clears
1094 * even if the modifier doesn't support them by doing a partial resolve
1095 * as part of the flush operation.
1097 mt
->supports_fast_clear
=
1098 allow_internal_aux
|| mod_info
->supports_clear_color
;
1100 /* We don't know the actual state of the surface when we get it but we
1101 * can make a pretty good guess based on the modifier. What we do know
1102 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1103 * a worst case of compression.
1105 enum isl_aux_state initial_state
=
1106 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1108 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1109 intel_miptree_release(&mt
);
1114 /* Don't assume coherency for imported EGLimages. We don't know what
1115 * external clients are going to do with it. They may scan it out.
1117 image
->bo
->cache_coherent
= false;
1123 * For a singlesample renderbuffer, this simply wraps the given BO with a
1126 * For a multisample renderbuffer, this wraps the window system's
1127 * (singlesample) BO with a singlesample miptree attached to the
1128 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1129 * that will contain the actual rendering (which is lazily resolved to
1130 * irb->singlesample_mt).
1133 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1134 struct intel_renderbuffer
*irb
,
1135 struct intel_mipmap_tree
*singlesample_mt
,
1136 uint32_t width
, uint32_t height
,
1139 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1140 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1141 mesa_format format
= rb
->Format
;
1142 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1144 /* Only the front and back buffers, which are color buffers, are allocated
1145 * through the image loader.
1147 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1148 _mesa_get_format_base_format(format
) == GL_RGBA
);
1150 assert(singlesample_mt
);
1152 if (num_samples
== 1) {
1153 intel_miptree_release(&irb
->mt
);
1154 irb
->mt
= singlesample_mt
;
1156 assert(!irb
->singlesample_mt
);
1158 intel_miptree_release(&irb
->singlesample_mt
);
1159 irb
->singlesample_mt
= singlesample_mt
;
1162 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1163 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1164 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1169 if (!multisample_mt
)
1172 irb
->need_downsample
= false;
1173 intel_miptree_release(&irb
->mt
);
1174 irb
->mt
= multisample_mt
;
1180 intel_miptree_release(&irb
->mt
);
1184 struct intel_mipmap_tree
*
1185 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1189 uint32_t num_samples
)
1191 struct intel_mipmap_tree
*mt
;
1193 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1195 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1196 width
, height
, depth
, num_samples
,
1197 MIPTREE_CREATE_BUSY
);
1204 intel_miptree_release(&mt
);
1209 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1210 struct intel_mipmap_tree
*src
)
1215 intel_miptree_release(dst
);
1219 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1226 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1228 if (aux_buf
== NULL
)
1231 brw_bo_unreference(aux_buf
->bo
);
1232 brw_bo_unreference(aux_buf
->clear_color_bo
);
1238 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1243 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1244 if (--(*mt
)->refcount
<= 0) {
1247 DBG("%s deleting %p\n", __func__
, *mt
);
1249 brw_bo_unreference((*mt
)->bo
);
1250 intel_miptree_release(&(*mt
)->stencil_mt
);
1251 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1252 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1253 free_aux_state_map((*mt
)->aux_state
);
1255 intel_miptree_release(&(*mt
)->plane
[0]);
1256 intel_miptree_release(&(*mt
)->plane
[1]);
1258 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1259 free((*mt
)->level
[i
].slice
);
1269 intel_get_image_dims(struct gl_texture_image
*image
,
1270 int *width
, int *height
, int *depth
)
1272 switch (image
->TexObject
->Target
) {
1273 case GL_TEXTURE_1D_ARRAY
:
1274 /* For a 1D Array texture the OpenGL API will treat the image height as
1275 * the number of array slices. For Intel hardware, we treat the 1D array
1276 * as a 2D Array with a height of 1. So, here we want to swap image
1279 assert(image
->Depth
== 1);
1280 *width
= image
->Width
;
1282 *depth
= image
->Height
;
1284 case GL_TEXTURE_CUBE_MAP
:
1285 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1286 * though we really have 6 slices.
1288 assert(image
->Depth
== 1);
1289 *width
= image
->Width
;
1290 *height
= image
->Height
;
1294 *width
= image
->Width
;
1295 *height
= image
->Height
;
1296 *depth
= image
->Depth
;
1302 * Can the image be pulled into a unified mipmap tree? This mirrors
1303 * the completeness test in a lot of ways.
1305 * Not sure whether I want to pass gl_texture_image here.
1308 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1309 struct gl_texture_image
*image
)
1311 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1312 GLuint level
= intelImage
->base
.Base
.Level
;
1313 int width
, height
, depth
;
1315 /* glTexImage* choose the texture object based on the target passed in, and
1316 * objects can't change targets over their lifetimes, so this should be
1319 assert(image
->TexObject
->Target
== mt
->target
);
1321 mesa_format mt_format
= mt
->format
;
1322 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1323 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1324 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1325 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1326 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1327 mt_format
= mt
->etc_format
;
1329 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1330 _mesa_get_srgb_format_linear(mt_format
))
1333 intel_get_image_dims(image
, &width
, &height
, &depth
);
1335 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1338 if (level
>= mt
->surf
.levels
)
1341 const unsigned level_depth
=
1342 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1343 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1344 mt
->surf
.logical_level0_px
.array_len
;
1346 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1347 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1348 depth
== level_depth
&&
1349 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1353 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1354 GLuint level
, GLuint slice
,
1355 GLuint
*x
, GLuint
*y
)
1357 if (level
== 0 && slice
== 0) {
1358 *x
= mt
->level
[0].level_x
;
1359 *y
= mt
->level
[0].level_y
;
1363 uint32_t x_offset_sa
, y_offset_sa
;
1365 /* Miptree itself can have an offset only if it represents a single
1366 * slice in an imported buffer object.
1367 * See intel_miptree_create_for_dri_image().
1369 assert(mt
->level
[0].level_x
== 0);
1370 assert(mt
->level
[0].level_y
== 0);
1372 /* Given level is relative to level zero while the miptree may be
1373 * represent just a subset of all levels starting from 'first_level'.
1375 assert(level
>= mt
->first_level
);
1376 level
-= mt
->first_level
;
1378 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1379 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1380 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1381 &x_offset_sa
, &y_offset_sa
);
1389 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1390 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1391 * and tile_h is set to 1.
1394 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1395 uint32_t *tile_w
, uint32_t *tile_h
)
1406 case ISL_TILING_LINEAR
:
1411 unreachable("not reached");
1417 * This function computes masks that may be used to select the bits of the X
1418 * and Y coordinates that indicate the offset within a tile. If the BO is
1419 * untiled, the masks are set to 0.
1422 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1423 uint32_t *mask_x
, uint32_t *mask_y
)
1425 uint32_t tile_w_bytes
, tile_h
;
1427 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1429 *mask_x
= tile_w_bytes
/ cpp
- 1;
1430 *mask_y
= tile_h
- 1;
1434 * Compute the offset (in bytes) from the start of the BO to the given x
1435 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1436 * multiples of the tile size.
1439 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1440 uint32_t x
, uint32_t y
)
1443 uint32_t pitch
= mt
->surf
.row_pitch
;
1445 switch (mt
->surf
.tiling
) {
1447 unreachable("not reached");
1448 case ISL_TILING_LINEAR
:
1449 return y
* pitch
+ x
* cpp
;
1451 assert((x
% (512 / cpp
)) == 0);
1452 assert((y
% 8) == 0);
1453 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1455 assert((x
% (128 / cpp
)) == 0);
1456 assert((y
% 32) == 0);
1457 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1462 * Rendering with tiled buffers requires that the base address of the buffer
1463 * be aligned to a page boundary. For renderbuffers, and sometimes with
1464 * textures, we may want the surface to point at a texture image level that
1465 * isn't at a page boundary.
1467 * This function returns an appropriately-aligned base offset
1468 * according to the tiling restrictions, plus any required x/y offset
1472 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1473 GLuint level
, GLuint slice
,
1478 uint32_t mask_x
, mask_y
;
1480 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1481 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1483 *tile_x
= x
& mask_x
;
1484 *tile_y
= y
& mask_y
;
1486 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1490 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1491 struct intel_mipmap_tree
*src_mt
,
1492 unsigned src_level
, unsigned src_layer
,
1493 struct intel_mipmap_tree
*dst_mt
,
1494 unsigned dst_level
, unsigned dst_layer
,
1495 unsigned width
, unsigned height
)
1498 ptrdiff_t src_stride
, dst_stride
;
1499 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1501 intel_miptree_map(brw
, src_mt
,
1502 src_level
, src_layer
,
1505 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1508 intel_miptree_map(brw
, dst_mt
,
1509 dst_level
, dst_layer
,
1512 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1516 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1517 _mesa_get_format_name(src_mt
->format
),
1518 src_mt
, src
, src_stride
,
1519 _mesa_get_format_name(dst_mt
->format
),
1520 dst_mt
, dst
, dst_stride
,
1523 int row_size
= cpp
* width
;
1524 if (src_stride
== row_size
&&
1525 dst_stride
== row_size
) {
1526 memcpy(dst
, src
, row_size
* height
);
1528 for (int i
= 0; i
< height
; i
++) {
1529 memcpy(dst
, src
, row_size
);
1535 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1536 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1538 /* Don't forget to copy the stencil data over, too. We could have skipped
1539 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1540 * shuffling the two data sources in/out of temporary storage instead of
1541 * the direct mapping we get this way.
1543 if (dst_mt
->stencil_mt
) {
1544 assert(src_mt
->stencil_mt
);
1545 intel_miptree_copy_slice_sw(brw
,
1546 src_mt
->stencil_mt
, src_level
, src_layer
,
1547 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1553 intel_miptree_copy_slice(struct brw_context
*brw
,
1554 struct intel_mipmap_tree
*src_mt
,
1555 unsigned src_level
, unsigned src_layer
,
1556 struct intel_mipmap_tree
*dst_mt
,
1557 unsigned dst_level
, unsigned dst_layer
)
1560 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1561 mesa_format format
= src_mt
->format
;
1562 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1563 src_level
- src_mt
->first_level
);
1564 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1565 src_level
- src_mt
->first_level
);
1567 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1568 src_level
- src_mt
->first_level
));
1570 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1571 _mesa_get_srgb_format_linear(dst_mt
->format
));
1573 DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
1574 _mesa_get_format_name(src_mt
->format
),
1575 src_mt
, src_level
, src_layer
,
1576 _mesa_get_format_name(dst_mt
->format
),
1577 dst_mt
, dst_level
, dst_layer
,
1580 if (devinfo
->gen
>= 6) {
1581 /* On gen6 and above, we just use blorp. It's faster than the blitter
1582 * and can handle everything without software fallbacks.
1584 brw_blorp_copy_miptrees(brw
,
1585 src_mt
, src_level
, src_layer
,
1586 dst_mt
, dst_level
, dst_layer
,
1587 0, 0, 0, 0, width
, height
);
1589 if (src_mt
->stencil_mt
) {
1590 assert(dst_mt
->stencil_mt
);
1591 brw_blorp_copy_miptrees(brw
,
1592 src_mt
->stencil_mt
, src_level
, src_layer
,
1593 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1594 0, 0, 0, 0, width
, height
);
1599 if (dst_mt
->compressed
) {
1601 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1602 height
= ALIGN_NPOT(height
, j
) / j
;
1603 width
= ALIGN_NPOT(width
, i
) / i
;
1606 /* Gen4-5 doesn't support separate stencil */
1607 assert(!src_mt
->stencil_mt
);
1609 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1610 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1612 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1615 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1616 _mesa_get_format_name(src_mt
->format
),
1617 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1618 _mesa_get_format_name(dst_mt
->format
),
1619 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1622 if (!intel_miptree_blit(brw
,
1623 src_mt
, src_level
, src_layer
, 0, 0, false,
1624 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1625 width
, height
, COLOR_LOGICOP_COPY
)) {
1626 perf_debug("miptree validate blit for %s failed\n",
1627 _mesa_get_format_name(format
));
1629 intel_miptree_copy_slice_sw(brw
,
1630 src_mt
, src_level
, src_layer
,
1631 dst_mt
, dst_level
, dst_layer
,
1637 * Copies the image's current data to the given miptree, and associates that
1638 * miptree with the image.
1641 intel_miptree_copy_teximage(struct brw_context
*brw
,
1642 struct intel_texture_image
*intelImage
,
1643 struct intel_mipmap_tree
*dst_mt
)
1645 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1646 struct intel_texture_object
*intel_obj
=
1647 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1648 int level
= intelImage
->base
.Base
.Level
;
1649 const unsigned face
= intelImage
->base
.Base
.Face
;
1650 unsigned start_layer
, end_layer
;
1652 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1654 assert(intelImage
->base
.Base
.Height
);
1656 end_layer
= intelImage
->base
.Base
.Height
- 1;
1657 } else if (face
> 0) {
1661 assert(intelImage
->base
.Base
.Depth
);
1663 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1666 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1667 intel_miptree_copy_slice(brw
,
1672 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1673 intel_obj
->needs_validate
= true;
1676 static struct intel_miptree_aux_buffer
*
1677 intel_alloc_aux_buffer(struct brw_context
*brw
,
1678 const struct isl_surf
*aux_surf
,
1680 uint8_t memset_value
)
1682 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1686 uint64_t size
= aux_surf
->size
;
1688 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1689 if (has_indirect_clear
) {
1690 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1691 * will set a pointer to a dword somewhere that contains the color. So,
1692 * allocate the space for the clear color value here on the aux buffer.
1694 buf
->clear_color_offset
= size
;
1695 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1698 /* If the buffer needs to be initialised (requiring the buffer to be
1699 * immediately mapped to cpu space for writing), do not use the gpu access
1700 * flag which can cause an unnecessary delay if the backing pages happened
1701 * to be just used by the GPU.
1703 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1704 const bool needs_memset
=
1705 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1706 const uint32_t alloc_flags
=
1707 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1709 /* ISL has stricter set of alignment rules then the drm allocator.
1710 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1711 * trying to recalculate based on different format block sizes.
1713 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1714 BRW_MEMZONE_OTHER
, I915_TILING_Y
,
1715 aux_surf
->row_pitch
, alloc_flags
);
1721 /* Initialize the bo to the desired value */
1723 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1725 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1727 intel_miptree_aux_buffer_free(buf
);
1731 /* Memset the aux_surf portion of the BO. */
1733 memset(map
, memset_value
, aux_surf
->size
);
1735 /* Zero the indirect clear color to match ::fast_clear_color. */
1736 if (has_indirect_clear
) {
1737 memset((char *)map
+ buf
->clear_color_offset
, 0,
1738 brw
->isl_dev
.ss
.clear_color_state_size
);
1741 brw_bo_unmap(buf
->bo
);
1744 if (has_indirect_clear
) {
1745 buf
->clear_color_bo
= buf
->bo
;
1746 brw_bo_reference(buf
->clear_color_bo
);
1749 buf
->surf
= *aux_surf
;
1756 * Helper for intel_miptree_alloc_aux() that sets
1757 * \c mt->level[level].has_hiz. Return true if and only if
1758 * \c has_hiz was set.
1761 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1762 struct intel_mipmap_tree
*mt
,
1765 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1767 assert(mt
->aux_buf
);
1768 assert(mt
->surf
.size
> 0);
1770 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1771 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1772 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1774 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1775 * and the height is 4 aligned. This allows our HiZ support
1776 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1777 * we can grow the width & height to allow the HiZ op to
1778 * force the proper size alignments.
1780 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1781 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1786 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1787 mt
->level
[level
].has_hiz
= true;
1793 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1795 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1796 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1797 * compress clear color so we wait until an actual fast-clear to allocate it.
1800 intel_miptree_alloc_aux(struct brw_context
*brw
,
1801 struct intel_mipmap_tree
*mt
)
1803 assert(mt
->aux_buf
== NULL
);
1805 /* Get the aux buf allocation parameters for this miptree. */
1806 enum isl_aux_state initial_state
;
1807 uint8_t memset_value
;
1808 struct isl_surf aux_surf
;
1809 MAYBE_UNUSED
bool aux_surf_ok
;
1811 switch (mt
->aux_usage
) {
1812 case ISL_AUX_USAGE_NONE
:
1816 case ISL_AUX_USAGE_HIZ
:
1817 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1818 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1820 case ISL_AUX_USAGE_MCS
:
1821 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1823 * When MCS buffer is enabled and bound to MSRT, it is required that
1824 * it is cleared prior to any rendering.
1826 * Since we don't use the MCS buffer for any purpose other than
1827 * rendering, it makes sense to just clear it immediately upon
1830 * Note: the clear value for MCS buffers is all 1's, so we memset to
1833 initial_state
= ISL_AUX_STATE_CLEAR
;
1834 memset_value
= 0xFF;
1835 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1837 case ISL_AUX_USAGE_CCS_D
:
1838 case ISL_AUX_USAGE_CCS_E
:
1839 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1840 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1843 * "If Software wants to enable Color Compression without Fast
1844 * clear, Software needs to initialize MCS with zeros."
1846 * A CCS value of 0 indicates that the corresponding block is in the
1847 * pass-through state which is what we want.
1849 * For CCS_D, do the same thing. On gen9+, this avoids having any
1850 * undefined bits in the aux buffer.
1852 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1855 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1859 /* We should have a valid aux_surf. */
1860 assert(aux_surf_ok
);
1862 /* No work is needed for a zero-sized auxiliary buffer. */
1863 if (aux_surf
.size
== 0)
1866 /* Create the aux_state for the auxiliary buffer. */
1867 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1868 if (mt
->aux_state
== NULL
)
1871 /* Allocate the auxiliary buffer. */
1872 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1873 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1875 if (mt
->aux_buf
== NULL
) {
1876 free_aux_state_map(mt
->aux_state
);
1877 mt
->aux_state
= NULL
;
1881 /* Perform aux_usage-specific initialization. */
1882 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1883 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1884 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1892 * Can the miptree sample using the hiz buffer?
1895 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1896 struct intel_mipmap_tree
*mt
)
1898 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1900 if (!devinfo
->has_sample_with_hiz
) {
1908 /* It seems the hardware won't fallback to the depth buffer if some of the
1909 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1910 * of the texture to be HiZ enabled.
1912 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1913 if (!intel_miptree_level_has_hiz(mt
, level
))
1917 /* If compressed multisampling is enabled, then we use it for the auxiliary
1920 * From the BDW PRM (Volume 2d: Command Reference: Structures
1921 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1923 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1924 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1926 * There is no such blurb for 1D textures, but there is sufficient evidence
1927 * that this is broken on SKL+.
1929 return (mt
->surf
.samples
== 1 &&
1930 mt
->target
!= GL_TEXTURE_3D
&&
1931 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1935 * Does the miptree slice have hiz enabled?
1938 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1940 intel_miptree_check_level_layer(mt
, level
, 0);
1941 return mt
->level
[level
].has_hiz
;
1944 static inline uint32_t
1945 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1946 uint32_t start_level
, uint32_t num_levels
)
1948 assert(start_level
>= mt
->first_level
);
1949 assert(start_level
<= mt
->last_level
);
1951 if (num_levels
== INTEL_REMAINING_LAYERS
)
1952 num_levels
= mt
->last_level
- start_level
+ 1;
1953 /* Check for overflow */
1954 assert(start_level
+ num_levels
>= start_level
);
1955 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1960 static inline uint32_t
1961 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1962 uint32_t start_layer
, uint32_t num_layers
)
1964 assert(level
<= mt
->last_level
);
1966 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1967 assert(start_layer
< total_num_layers
);
1968 if (num_layers
== INTEL_REMAINING_LAYERS
)
1969 num_layers
= total_num_layers
- start_layer
;
1970 /* Check for overflow */
1971 assert(start_layer
+ num_layers
>= start_layer
);
1972 assert(start_layer
+ num_layers
<= total_num_layers
);
1978 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1979 unsigned start_level
, unsigned num_levels
,
1980 unsigned start_layer
, unsigned num_layers
)
1982 assert(_mesa_is_format_color_format(mt
->format
));
1987 /* Clamp the level range to fit the miptree */
1988 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1990 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1991 const uint32_t level
= start_level
+ l
;
1992 const uint32_t level_layers
=
1993 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1994 for (unsigned a
= 0; a
< level_layers
; a
++) {
1995 enum isl_aux_state aux_state
=
1996 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1997 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1998 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2007 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2008 const struct intel_mipmap_tree
*mt
,
2009 unsigned level
, unsigned layer
)
2014 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2015 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2016 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2018 /* Compression of arrayed msaa surfaces is supported. */
2019 if (mt
->surf
.samples
> 1)
2022 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2023 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2025 mt
->surf
.logical_level0_px
.depth
== 1 &&
2026 mt
->surf
.logical_level0_px
.array_len
== 1));
2032 static enum isl_aux_op
2033 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2034 enum isl_aux_usage aux_usage
,
2035 bool fast_clear_supported
)
2037 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2039 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2041 assert(ccs_supported
== fast_clear_supported
);
2043 switch (aux_state
) {
2044 case ISL_AUX_STATE_CLEAR
:
2045 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2047 return ISL_AUX_OP_FULL_RESOLVE
;
2049 return ISL_AUX_OP_NONE
;
2051 case ISL_AUX_STATE_PASS_THROUGH
:
2052 return ISL_AUX_OP_NONE
;
2054 case ISL_AUX_STATE_RESOLVED
:
2055 case ISL_AUX_STATE_AUX_INVALID
:
2056 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2057 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2061 unreachable("Invalid aux state for CCS_D");
2064 static enum isl_aux_op
2065 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2066 enum isl_aux_usage aux_usage
,
2067 bool fast_clear_supported
)
2069 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2070 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2071 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2072 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2074 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2075 assert(fast_clear_supported
);
2077 switch (aux_state
) {
2078 case ISL_AUX_STATE_CLEAR
:
2079 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2080 if (fast_clear_supported
)
2081 return ISL_AUX_OP_NONE
;
2082 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2083 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2085 return ISL_AUX_OP_FULL_RESOLVE
;
2087 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2088 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2089 return ISL_AUX_OP_FULL_RESOLVE
;
2090 else if (!fast_clear_supported
)
2091 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2093 return ISL_AUX_OP_NONE
;
2095 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2096 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2097 return ISL_AUX_OP_FULL_RESOLVE
;
2099 return ISL_AUX_OP_NONE
;
2101 case ISL_AUX_STATE_PASS_THROUGH
:
2102 return ISL_AUX_OP_NONE
;
2104 case ISL_AUX_STATE_RESOLVED
:
2105 case ISL_AUX_STATE_AUX_INVALID
:
2109 unreachable("Invalid aux state for CCS_E");
2113 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2114 struct intel_mipmap_tree
*mt
,
2115 uint32_t level
, uint32_t layer
,
2116 enum isl_aux_usage aux_usage
,
2117 bool fast_clear_supported
)
2119 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2121 enum isl_aux_op resolve_op
;
2122 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2123 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2124 fast_clear_supported
);
2126 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2127 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2128 fast_clear_supported
);
2131 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2132 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2133 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2135 switch (resolve_op
) {
2136 case ISL_AUX_OP_FULL_RESOLVE
:
2137 /* The CCS full resolve operation destroys the CCS and sets it to the
2138 * pass-through state. (You can also think of this as being both a
2139 * resolve and an ambiguate in one operation.)
2141 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2142 ISL_AUX_STATE_PASS_THROUGH
);
2145 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2146 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2147 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2151 unreachable("Invalid resolve op");
2157 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2158 struct intel_mipmap_tree
*mt
,
2159 uint32_t level
, uint32_t layer
,
2160 enum isl_aux_usage aux_usage
)
2162 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2163 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2164 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2166 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2168 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2169 switch (aux_state
) {
2170 case ISL_AUX_STATE_CLEAR
:
2171 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2172 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2173 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2175 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2176 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2177 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2178 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2179 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2180 ISL_AUX_STATE_PARTIAL_CLEAR
);
2184 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2185 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2186 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2187 break; /* Nothing to do */
2189 case ISL_AUX_STATE_PASS_THROUGH
:
2190 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2191 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2192 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2198 case ISL_AUX_STATE_RESOLVED
:
2199 case ISL_AUX_STATE_AUX_INVALID
:
2200 unreachable("Invalid aux state for CCS_E");
2203 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2204 /* CCS_D is a bit simpler */
2205 switch (aux_state
) {
2206 case ISL_AUX_STATE_CLEAR
:
2207 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2208 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2209 ISL_AUX_STATE_PARTIAL_CLEAR
);
2212 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2213 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2214 break; /* Nothing to do */
2216 case ISL_AUX_STATE_PASS_THROUGH
:
2220 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2221 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2222 case ISL_AUX_STATE_RESOLVED
:
2223 case ISL_AUX_STATE_AUX_INVALID
:
2224 unreachable("Invalid aux state for CCS_D");
2230 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2231 struct intel_mipmap_tree
*mt
,
2233 enum isl_aux_usage aux_usage
,
2234 bool fast_clear_supported
)
2236 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2238 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2239 case ISL_AUX_STATE_CLEAR
:
2240 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2241 if (!fast_clear_supported
) {
2242 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2243 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2244 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2248 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2249 break; /* Nothing to do */
2251 case ISL_AUX_STATE_RESOLVED
:
2252 case ISL_AUX_STATE_PASS_THROUGH
:
2253 case ISL_AUX_STATE_AUX_INVALID
:
2254 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2255 unreachable("Invalid aux state for MCS");
2260 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2261 struct intel_mipmap_tree
*mt
,
2263 enum isl_aux_usage aux_usage
)
2265 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2267 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2268 case ISL_AUX_STATE_CLEAR
:
2269 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2270 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2273 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2274 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2275 break; /* Nothing to do */
2277 case ISL_AUX_STATE_RESOLVED
:
2278 case ISL_AUX_STATE_PASS_THROUGH
:
2279 case ISL_AUX_STATE_AUX_INVALID
:
2280 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2281 unreachable("Invalid aux state for MCS");
2286 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2287 struct intel_mipmap_tree
*mt
,
2288 uint32_t level
, uint32_t layer
,
2289 enum isl_aux_usage aux_usage
,
2290 bool fast_clear_supported
)
2292 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2294 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2295 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2296 case ISL_AUX_STATE_CLEAR
:
2297 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2298 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2299 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2302 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2303 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2304 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2307 case ISL_AUX_STATE_PASS_THROUGH
:
2308 case ISL_AUX_STATE_RESOLVED
:
2311 case ISL_AUX_STATE_AUX_INVALID
:
2312 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2313 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2316 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2317 unreachable("Invalid HiZ state");
2320 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2321 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2324 case ISL_AUX_OP_FULL_RESOLVE
:
2325 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2326 ISL_AUX_STATE_RESOLVED
);
2329 case ISL_AUX_OP_AMBIGUATE
:
2330 /* The HiZ resolve operation is actually an ambiguate */
2331 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2332 ISL_AUX_STATE_PASS_THROUGH
);
2336 unreachable("Invalid HiZ op");
2342 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2343 struct intel_mipmap_tree
*mt
,
2344 uint32_t level
, uint32_t layer
,
2345 enum isl_aux_usage aux_usage
)
2347 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2349 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2350 case ISL_AUX_STATE_CLEAR
:
2351 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2352 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2353 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2356 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2357 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2358 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2359 break; /* Nothing to do */
2361 case ISL_AUX_STATE_RESOLVED
:
2362 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2363 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2364 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2366 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2367 ISL_AUX_STATE_AUX_INVALID
);
2371 case ISL_AUX_STATE_PASS_THROUGH
:
2372 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2373 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2374 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2378 case ISL_AUX_STATE_AUX_INVALID
:
2379 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2382 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2383 unreachable("Invalid HiZ state");
2388 intel_miptree_prepare_access(struct brw_context
*brw
,
2389 struct intel_mipmap_tree
*mt
,
2390 uint32_t start_level
, uint32_t num_levels
,
2391 uint32_t start_layer
, uint32_t num_layers
,
2392 enum isl_aux_usage aux_usage
,
2393 bool fast_clear_supported
)
2395 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2397 switch (mt
->aux_usage
) {
2398 case ISL_AUX_USAGE_NONE
:
2402 case ISL_AUX_USAGE_MCS
:
2403 assert(mt
->aux_buf
);
2404 assert(start_level
== 0 && num_levels
== 1);
2405 const uint32_t level_layers
=
2406 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2407 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2408 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2409 aux_usage
, fast_clear_supported
);
2413 case ISL_AUX_USAGE_CCS_D
:
2414 case ISL_AUX_USAGE_CCS_E
:
2418 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2419 const uint32_t level
= start_level
+ l
;
2420 const uint32_t level_layers
=
2421 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2422 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2423 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2425 aux_usage
, fast_clear_supported
);
2430 case ISL_AUX_USAGE_HIZ
:
2431 assert(mt
->aux_buf
);
2432 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2433 const uint32_t level
= start_level
+ l
;
2434 if (!intel_miptree_level_has_hiz(mt
, level
))
2437 const uint32_t level_layers
=
2438 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2439 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2440 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2441 aux_usage
, fast_clear_supported
);
2447 unreachable("Invalid aux usage");
2452 intel_miptree_finish_write(struct brw_context
*brw
,
2453 struct intel_mipmap_tree
*mt
, uint32_t level
,
2454 uint32_t start_layer
, uint32_t num_layers
,
2455 enum isl_aux_usage aux_usage
)
2457 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2458 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2460 switch (mt
->aux_usage
) {
2461 case ISL_AUX_USAGE_NONE
:
2462 if (mt
->format
== MESA_FORMAT_S_UINT8
&& devinfo
->gen
<= 7)
2463 mt
->r8stencil_needs_update
= true;
2466 case ISL_AUX_USAGE_MCS
:
2467 assert(mt
->aux_buf
);
2468 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2469 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2474 case ISL_AUX_USAGE_CCS_D
:
2475 case ISL_AUX_USAGE_CCS_E
:
2479 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2480 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2485 case ISL_AUX_USAGE_HIZ
:
2486 if (!intel_miptree_level_has_hiz(mt
, level
))
2489 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2490 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2496 unreachable("Invavlid aux usage");
2501 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2502 uint32_t level
, uint32_t layer
)
2504 intel_miptree_check_level_layer(mt
, level
, layer
);
2506 if (_mesa_is_format_color_format(mt
->format
)) {
2507 assert(mt
->aux_buf
!= NULL
);
2508 assert(mt
->surf
.samples
== 1 ||
2509 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2510 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2511 unreachable("Cannot get aux state for stencil");
2513 assert(intel_miptree_level_has_hiz(mt
, level
));
2516 return mt
->aux_state
[level
][layer
];
2520 intel_miptree_set_aux_state(struct brw_context
*brw
,
2521 struct intel_mipmap_tree
*mt
, uint32_t level
,
2522 uint32_t start_layer
, uint32_t num_layers
,
2523 enum isl_aux_state aux_state
)
2525 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2527 if (_mesa_is_format_color_format(mt
->format
)) {
2528 assert(mt
->aux_buf
!= NULL
);
2529 assert(mt
->surf
.samples
== 1 ||
2530 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2531 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2532 unreachable("Cannot get aux state for stencil");
2534 assert(intel_miptree_level_has_hiz(mt
, level
));
2537 for (unsigned a
= 0; a
< num_layers
; a
++) {
2538 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2539 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2540 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2545 /* On Gen9 color buffers may be compressed by the hardware (lossless
2546 * compression). There are, however, format restrictions and care needs to be
2547 * taken that the sampler engine is capable for re-interpreting a buffer with
2548 * format different the buffer was originally written with.
2550 * For example, SRGB formats are not compressible and the sampler engine isn't
2551 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2552 * color buffer needs to be resolved so that the sampling surface can be
2553 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2557 can_texture_with_ccs(struct brw_context
*brw
,
2558 struct intel_mipmap_tree
*mt
,
2559 enum isl_format view_format
)
2561 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2564 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2566 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2567 isl_format_get_layout(view_format
)->name
,
2568 _mesa_get_format_name(mt
->format
));
2576 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2577 struct intel_mipmap_tree
*mt
,
2578 enum isl_format view_format
)
2580 switch (mt
->aux_usage
) {
2581 case ISL_AUX_USAGE_HIZ
:
2582 if (intel_miptree_sample_with_hiz(brw
, mt
))
2583 return ISL_AUX_USAGE_HIZ
;
2586 case ISL_AUX_USAGE_MCS
:
2587 return ISL_AUX_USAGE_MCS
;
2589 case ISL_AUX_USAGE_CCS_D
:
2590 case ISL_AUX_USAGE_CCS_E
:
2592 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2593 return ISL_AUX_USAGE_NONE
;
2596 /* If we don't have any unresolved color, report an aux usage of
2597 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2598 * aux surface and we can save some bandwidth.
2600 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2601 0, INTEL_REMAINING_LAYERS
))
2602 return ISL_AUX_USAGE_NONE
;
2604 if (can_texture_with_ccs(brw
, mt
, view_format
))
2605 return ISL_AUX_USAGE_CCS_E
;
2612 return ISL_AUX_USAGE_NONE
;
2616 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2618 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2619 * values so sRGB curve application was a no-op for all fast-clearable
2622 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2623 * values, the hardware interprets the floats, not as what would be
2624 * returned from the sampler (or written by the shader), but as being
2625 * between format conversion and sRGB curve application. This means that
2626 * we can switch between sRGB and UNORM without having to whack the clear
2629 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2633 intel_miptree_prepare_texture(struct brw_context
*brw
,
2634 struct intel_mipmap_tree
*mt
,
2635 enum isl_format view_format
,
2636 uint32_t start_level
, uint32_t num_levels
,
2637 uint32_t start_layer
, uint32_t num_layers
)
2639 enum isl_aux_usage aux_usage
=
2640 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2641 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2643 /* Clear color is specified as ints or floats and the conversion is done by
2644 * the sampler. If we have a texture view, we would have to perform the
2645 * clear color conversion manually. Just disable clear color.
2647 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2648 clear_supported
= false;
2650 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2651 start_layer
, num_layers
,
2652 aux_usage
, clear_supported
);
2656 intel_miptree_prepare_image(struct brw_context
*brw
,
2657 struct intel_mipmap_tree
*mt
)
2659 /* The data port doesn't understand any compression */
2660 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2661 0, INTEL_REMAINING_LAYERS
,
2662 ISL_AUX_USAGE_NONE
, false);
2666 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2667 struct intel_mipmap_tree
*mt
,
2668 enum isl_format render_format
,
2670 bool draw_aux_disabled
)
2672 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2674 if (draw_aux_disabled
)
2675 return ISL_AUX_USAGE_NONE
;
2677 switch (mt
->aux_usage
) {
2678 case ISL_AUX_USAGE_MCS
:
2679 assert(mt
->aux_buf
);
2680 return ISL_AUX_USAGE_MCS
;
2682 case ISL_AUX_USAGE_CCS_D
:
2683 case ISL_AUX_USAGE_CCS_E
:
2685 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2686 return ISL_AUX_USAGE_NONE
;
2689 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2690 * formats. However, there are issues with blending where it doesn't
2691 * properly apply the sRGB curve to the clear color when blending.
2693 if (devinfo
->gen
>= 9 && blend_enabled
&&
2694 isl_format_is_srgb(render_format
) &&
2695 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2696 return ISL_AUX_USAGE_NONE
;
2698 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2699 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2701 return ISL_AUX_USAGE_CCS_E
;
2703 /* Otherwise, we have to fall back to CCS_D */
2704 return ISL_AUX_USAGE_CCS_D
;
2707 return ISL_AUX_USAGE_NONE
;
2712 intel_miptree_prepare_render(struct brw_context
*brw
,
2713 struct intel_mipmap_tree
*mt
, uint32_t level
,
2714 uint32_t start_layer
, uint32_t layer_count
,
2715 enum isl_aux_usage aux_usage
)
2717 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2718 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2722 intel_miptree_finish_render(struct brw_context
*brw
,
2723 struct intel_mipmap_tree
*mt
, uint32_t level
,
2724 uint32_t start_layer
, uint32_t layer_count
,
2725 enum isl_aux_usage aux_usage
)
2727 assert(_mesa_is_format_color_format(mt
->format
));
2729 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2734 intel_miptree_prepare_depth(struct brw_context
*brw
,
2735 struct intel_mipmap_tree
*mt
, uint32_t level
,
2736 uint32_t start_layer
, uint32_t layer_count
)
2738 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2739 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2743 intel_miptree_finish_depth(struct brw_context
*brw
,
2744 struct intel_mipmap_tree
*mt
, uint32_t level
,
2745 uint32_t start_layer
, uint32_t layer_count
,
2748 if (depth_written
) {
2749 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2750 mt
->aux_buf
!= NULL
);
2755 intel_miptree_prepare_external(struct brw_context
*brw
,
2756 struct intel_mipmap_tree
*mt
)
2758 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2759 bool supports_fast_clear
= false;
2761 const struct isl_drm_modifier_info
*mod_info
=
2762 isl_drm_modifier_get_info(mt
->drm_modifier
);
2764 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2765 /* CCS_E is the only supported aux for external images and it's only
2766 * supported on very simple images.
2768 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2769 assert(_mesa_is_format_color_format(mt
->format
));
2770 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2771 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2772 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2773 assert(mt
->surf
.samples
== 1);
2774 assert(mt
->aux_buf
!= NULL
);
2776 aux_usage
= mod_info
->aux_usage
;
2777 supports_fast_clear
= mod_info
->supports_clear_color
;
2780 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2781 0, INTEL_REMAINING_LAYERS
,
2782 aux_usage
, supports_fast_clear
);
2786 intel_miptree_finish_external(struct brw_context
*brw
,
2787 struct intel_mipmap_tree
*mt
)
2792 /* We don't know the actual aux state of the aux surface. The previous
2793 * owner could have given it to us in a number of different states.
2794 * Because we don't know the aux state, we reset the aux state to the
2795 * least common denominator of possible valid states.
2797 enum isl_aux_state default_aux_state
=
2798 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2799 assert(mt
->last_level
== mt
->first_level
);
2800 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2805 * Make it possible to share the BO backing the given miptree with another
2806 * process or another miptree.
2808 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2809 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2810 * ensure that no MCS buffer gets allocated in the future.
2812 * HiZ is similarly unsafe with shared buffers.
2815 intel_miptree_make_shareable(struct brw_context
*brw
,
2816 struct intel_mipmap_tree
*mt
)
2818 /* MCS buffers are also used for multisample buffers, but we can't resolve
2819 * away a multisample MCS buffer because it's an integral part of how the
2820 * pixel data is stored. Fortunately this code path should never be
2821 * reached for multisample buffers.
2823 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2824 mt
->surf
.samples
== 1);
2826 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2827 0, INTEL_REMAINING_LAYERS
,
2828 ISL_AUX_USAGE_NONE
, false);
2831 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2834 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2835 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2836 mt
->level
[l
].has_hiz
= false;
2839 free(mt
->aux_state
);
2840 mt
->aux_state
= NULL
;
2841 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2844 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2845 mt
->supports_fast_clear
= false;
2850 * \brief Get pointer offset into stencil buffer.
2852 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2853 * must decode the tile's layout in software.
2856 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2858 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2860 * Even though the returned offset is always positive, the return type is
2862 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2863 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2866 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2868 uint32_t tile_size
= 4096;
2869 uint32_t tile_width
= 64;
2870 uint32_t tile_height
= 64;
2871 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2873 uint32_t tile_x
= x
/ tile_width
;
2874 uint32_t tile_y
= y
/ tile_height
;
2876 /* The byte's address relative to the tile's base addres. */
2877 uint32_t byte_x
= x
% tile_width
;
2878 uint32_t byte_y
= y
% tile_height
;
2880 uintptr_t u
= tile_y
* row_size
2881 + tile_x
* tile_size
2882 + 512 * (byte_x
/ 8)
2884 + 32 * ((byte_y
/ 4) % 2)
2885 + 16 * ((byte_x
/ 4) % 2)
2886 + 8 * ((byte_y
/ 2) % 2)
2887 + 4 * ((byte_x
/ 2) % 2)
2892 /* adjust for bit6 swizzling */
2893 if (((byte_x
/ 8) % 2) == 1) {
2894 if (((byte_y
/ 8) % 2) == 0) {
2906 intel_miptree_updownsample(struct brw_context
*brw
,
2907 struct intel_mipmap_tree
*src
,
2908 struct intel_mipmap_tree
*dst
)
2910 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2911 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2912 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2913 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2915 brw_blorp_blit_miptrees(brw
,
2916 src
, 0 /* level */, 0 /* layer */,
2917 src
->format
, SWIZZLE_XYZW
,
2918 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2921 GL_NEAREST
, false, false /*mirror x, y*/,
2924 if (src
->stencil_mt
) {
2925 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2926 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2927 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2928 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2930 brw_blorp_blit_miptrees(brw
,
2931 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2932 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2933 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2934 dst
->stencil_mt
->format
,
2937 GL_NEAREST
, false, false /*mirror x, y*/,
2938 false, false /* decode/encode srgb */);
2943 intel_update_r8stencil(struct brw_context
*brw
,
2944 struct intel_mipmap_tree
*mt
)
2946 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2948 assert(devinfo
->gen
>= 7);
2949 struct intel_mipmap_tree
*src
=
2950 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2951 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2954 assert(src
->surf
.size
> 0);
2956 if (!mt
->r8stencil_mt
) {
2957 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2958 mt
->r8stencil_mt
= make_surface(
2961 MESA_FORMAT_R_UINT8
,
2962 src
->first_level
, src
->last_level
,
2963 src
->surf
.logical_level0_px
.width
,
2964 src
->surf
.logical_level0_px
.height
,
2965 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2966 src
->surf
.logical_level0_px
.depth
:
2967 src
->surf
.logical_level0_px
.array_len
,
2970 ISL_SURF_USAGE_TEXTURE_BIT
,
2971 BO_ALLOC_BUSY
, 0, NULL
);
2972 assert(mt
->r8stencil_mt
);
2975 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2977 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2978 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2979 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2980 src
->surf
.phys_level0_sa
.array_len
;
2982 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2983 brw_blorp_copy_miptrees(brw
,
2987 minify(src
->surf
.logical_level0_px
.width
,
2989 minify(src
->surf
.logical_level0_px
.height
,
2994 brw_cache_flush_for_read(brw
, dst
->bo
);
2995 src
->r8stencil_needs_update
= false;
2999 intel_miptree_map_raw(struct brw_context
*brw
,
3000 struct intel_mipmap_tree
*mt
,
3003 struct brw_bo
*bo
= mt
->bo
;
3005 if (brw_batch_references(&brw
->batch
, bo
))
3006 intel_batchbuffer_flush(brw
);
3008 return brw_bo_map(brw
, bo
, mode
);
3012 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3014 brw_bo_unmap(mt
->bo
);
3018 intel_miptree_unmap_gtt(struct brw_context
*brw
,
3019 struct intel_mipmap_tree
*mt
,
3020 struct intel_miptree_map
*map
,
3021 unsigned int level
, unsigned int slice
)
3023 intel_miptree_unmap_raw(mt
);
3027 intel_miptree_map_gtt(struct brw_context
*brw
,
3028 struct intel_mipmap_tree
*mt
,
3029 struct intel_miptree_map
*map
,
3030 unsigned int level
, unsigned int slice
)
3032 unsigned int bw
, bh
;
3034 unsigned int image_x
, image_y
;
3035 intptr_t x
= map
->x
;
3036 intptr_t y
= map
->y
;
3038 /* For compressed formats, the stride is the number of bytes per
3039 * row of blocks. intel_miptree_get_image_offset() already does
3042 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3043 assert(y
% bh
== 0);
3044 assert(x
% bw
== 0);
3048 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3049 map
->mode
& GL_MAP_WRITE_BIT
);
3051 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3058 /* Note that in the case of cube maps, the caller must have passed the
3059 * slice number referencing the face.
3061 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3065 map
->stride
= mt
->surf
.row_pitch
;
3066 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3069 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3070 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3071 map
->x
, map
->y
, map
->w
, map
->h
,
3072 mt
, _mesa_get_format_name(mt
->format
),
3073 x
, y
, map
->ptr
, map
->stride
);
3075 map
->unmap
= intel_miptree_unmap_gtt
;
3079 intel_miptree_unmap_blit(struct brw_context
*brw
,
3080 struct intel_mipmap_tree
*mt
,
3081 struct intel_miptree_map
*map
,
3085 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3086 struct gl_context
*ctx
= &brw
->ctx
;
3088 intel_miptree_unmap_raw(map
->linear_mt
);
3090 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3091 if (devinfo
->gen
>= 6) {
3092 brw_blorp_copy_miptrees(brw
, map
->linear_mt
, 0, 0,
3094 0, 0, map
->x
, map
->y
, map
->w
, map
->h
);
3096 bool ok
= intel_miptree_copy(brw
,
3097 map
->linear_mt
, 0, 0, 0, 0,
3098 mt
, level
, slice
, map
->x
, map
->y
,
3100 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3104 intel_miptree_release(&map
->linear_mt
);
3108 intel_miptree_map_blit(struct brw_context
*brw
,
3109 struct intel_mipmap_tree
*mt
,
3110 struct intel_miptree_map
*map
,
3111 unsigned int level
, unsigned int slice
)
3113 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3114 map
->linear_mt
= make_surface(brw
, GL_TEXTURE_2D
, mt
->format
,
3115 0, 0, map
->w
, map
->h
, 1, 1,
3116 ISL_TILING_LINEAR_BIT
,
3117 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
3118 ISL_SURF_USAGE_TEXTURE_BIT
,
3121 if (!map
->linear_mt
) {
3122 fprintf(stderr
, "Failed to allocate blit temporary\n");
3125 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3127 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3128 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3129 * invalidate is set, since we'll be writing the whole rectangle from our
3130 * temporary buffer back out.
3132 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3133 if (devinfo
->gen
>= 6) {
3134 brw_blorp_copy_miptrees(brw
, mt
, level
, slice
,
3135 map
->linear_mt
, 0, 0,
3136 map
->x
, map
->y
, 0, 0, map
->w
, map
->h
);
3138 if (!intel_miptree_copy(brw
,
3139 mt
, level
, slice
, map
->x
, map
->y
,
3140 map
->linear_mt
, 0, 0, 0, 0,
3142 fprintf(stderr
, "Failed to blit\n");
3148 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3150 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3151 map
->x
, map
->y
, map
->w
, map
->h
,
3152 mt
, _mesa_get_format_name(mt
->format
),
3153 level
, slice
, map
->ptr
, map
->stride
);
3155 map
->unmap
= intel_miptree_unmap_blit
;
3159 intel_miptree_release(&map
->linear_mt
);
3165 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3167 #if defined(USE_SSE41)
3169 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3170 struct intel_mipmap_tree
*mt
,
3171 struct intel_miptree_map
*map
,
3175 _mesa_align_free(map
->buffer
);
3181 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3182 struct intel_mipmap_tree
*mt
,
3183 struct intel_miptree_map
*map
,
3184 unsigned int level
, unsigned int slice
)
3186 assert(map
->mode
& GL_MAP_READ_BIT
);
3187 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3189 intel_miptree_access_raw(brw
, mt
, level
, slice
, false);
3191 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3192 map
->x
, map
->y
, map
->w
, map
->h
,
3193 mt
, _mesa_get_format_name(mt
->format
),
3194 level
, slice
, map
->ptr
, map
->stride
);
3196 /* Map the original image */
3199 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3203 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3209 src
+= image_y
* mt
->surf
.row_pitch
;
3210 src
+= image_x
* mt
->cpp
;
3212 /* Due to the pixel offsets for the particular image being mapped, our
3213 * src pointer may not be 16-byte aligned. However, if the pitch is
3214 * divisible by 16, then the amount by which it's misaligned will remain
3215 * consistent from row to row.
3217 assert((mt
->surf
.row_pitch
% 16) == 0);
3218 const int misalignment
= ((uintptr_t) src
) & 15;
3220 /* Create an untiled temporary buffer for the mapping. */
3221 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3223 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3225 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3226 /* Offset the destination so it has the same misalignment as src. */
3227 map
->ptr
= map
->buffer
+ misalignment
;
3229 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3231 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3232 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3233 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3235 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3238 intel_miptree_unmap_raw(mt
);
3240 map
->unmap
= intel_miptree_unmap_movntdqa
;
3245 intel_miptree_unmap_s8(struct brw_context
*brw
,
3246 struct intel_mipmap_tree
*mt
,
3247 struct intel_miptree_map
*map
,
3251 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3252 unsigned int image_x
, image_y
;
3253 uint8_t *untiled_s8_map
= map
->ptr
;
3254 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3256 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3258 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3259 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3260 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3261 image_x
+ x
+ map
->x
,
3262 image_y
+ y
+ map
->y
,
3263 brw
->has_swizzling
);
3264 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3268 intel_miptree_unmap_raw(mt
);
3275 intel_miptree_map_s8(struct brw_context
*brw
,
3276 struct intel_mipmap_tree
*mt
,
3277 struct intel_miptree_map
*map
,
3278 unsigned int level
, unsigned int slice
)
3280 map
->stride
= map
->w
;
3281 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3285 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3286 map
->mode
& GL_MAP_WRITE_BIT
);
3288 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3289 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3290 * invalidate is set, since we'll be writing the whole rectangle from our
3291 * temporary buffer back out.
3293 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3294 uint8_t *untiled_s8_map
= map
->ptr
;
3295 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3296 unsigned int image_x
, image_y
;
3298 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3300 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3301 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3302 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3303 x
+ image_x
+ map
->x
,
3304 y
+ image_y
+ map
->y
,
3305 brw
->has_swizzling
);
3306 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3310 intel_miptree_unmap_raw(mt
);
3312 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3313 map
->x
, map
->y
, map
->w
, map
->h
,
3314 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3316 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3317 map
->x
, map
->y
, map
->w
, map
->h
,
3318 mt
, map
->ptr
, map
->stride
);
3321 map
->unmap
= intel_miptree_unmap_s8
;
3325 intel_miptree_unmap_etc(struct brw_context
*brw
,
3326 struct intel_mipmap_tree
*mt
,
3327 struct intel_miptree_map
*map
,
3333 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3338 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3339 + image_y
* mt
->surf
.row_pitch
3340 + image_x
* mt
->cpp
;
3342 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3343 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3344 map
->ptr
, map
->stride
,
3347 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3348 map
->ptr
, map
->stride
,
3349 map
->w
, map
->h
, mt
->etc_format
, true);
3351 intel_miptree_unmap_raw(mt
);
3356 intel_miptree_map_etc(struct brw_context
*brw
,
3357 struct intel_mipmap_tree
*mt
,
3358 struct intel_miptree_map
*map
,
3362 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3363 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3364 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3367 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3368 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3370 intel_miptree_access_raw(brw
, mt
, level
, slice
, true);
3372 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3373 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3374 map
->w
, map
->h
, 1));
3375 map
->ptr
= map
->buffer
;
3376 map
->unmap
= intel_miptree_unmap_etc
;
3380 * Mapping functions for packed depth/stencil miptrees backed by real separate
3381 * miptrees for depth and stencil.
3383 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3384 * separate from the depth buffer. Yet at the GL API level, we have to expose
3385 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3386 * be able to map that memory for texture storage and glReadPixels-type
3387 * operations. We give Mesa core that access by mallocing a temporary and
3388 * copying the data between the actual backing store and the temporary.
3391 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3392 struct intel_mipmap_tree
*mt
,
3393 struct intel_miptree_map
*map
,
3397 struct intel_mipmap_tree
*z_mt
= mt
;
3398 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3399 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3401 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3402 uint32_t *packed_map
= map
->ptr
;
3403 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3404 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3405 unsigned int s_image_x
, s_image_y
;
3406 unsigned int z_image_x
, z_image_y
;
3408 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3409 &s_image_x
, &s_image_y
);
3410 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3411 &z_image_x
, &z_image_y
);
3413 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3414 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3415 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3416 x
+ s_image_x
+ map
->x
,
3417 y
+ s_image_y
+ map
->y
,
3418 brw
->has_swizzling
);
3419 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3420 (z_mt
->surf
.row_pitch
/ 4) +
3421 (x
+ z_image_x
+ map
->x
));
3423 if (map_z32f_x24s8
) {
3424 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3425 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3427 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3428 s_map
[s_offset
] = packed
>> 24;
3429 z_map
[z_offset
] = packed
;
3434 intel_miptree_unmap_raw(s_mt
);
3435 intel_miptree_unmap_raw(z_mt
);
3437 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3439 map
->x
, map
->y
, map
->w
, map
->h
,
3440 z_mt
, _mesa_get_format_name(z_mt
->format
),
3441 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3442 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3443 map
->ptr
, map
->stride
);
3450 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3451 struct intel_mipmap_tree
*mt
,
3452 struct intel_miptree_map
*map
,
3453 unsigned int level
, unsigned int slice
)
3455 struct intel_mipmap_tree
*z_mt
= mt
;
3456 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3457 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3458 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3460 map
->stride
= map
->w
* packed_bpp
;
3461 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3465 intel_miptree_access_raw(brw
, z_mt
, level
, slice
,
3466 map
->mode
& GL_MAP_WRITE_BIT
);
3467 intel_miptree_access_raw(brw
, s_mt
, level
, slice
,
3468 map
->mode
& GL_MAP_WRITE_BIT
);
3470 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3471 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3472 * invalidate is set, since we'll be writing the whole rectangle from our
3473 * temporary buffer back out.
3475 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3476 uint32_t *packed_map
= map
->ptr
;
3477 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3478 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3479 unsigned int s_image_x
, s_image_y
;
3480 unsigned int z_image_x
, z_image_y
;
3482 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3483 &s_image_x
, &s_image_y
);
3484 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3485 &z_image_x
, &z_image_y
);
3487 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3488 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3489 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3490 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3493 brw
->has_swizzling
);
3494 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3495 (z_mt
->surf
.row_pitch
/ 4) +
3496 (map_x
+ z_image_x
));
3497 uint8_t s
= s_map
[s_offset
];
3498 uint32_t z
= z_map
[z_offset
];
3500 if (map_z32f_x24s8
) {
3501 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3502 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3504 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3509 intel_miptree_unmap_raw(s_mt
);
3510 intel_miptree_unmap_raw(z_mt
);
3512 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3514 map
->x
, map
->y
, map
->w
, map
->h
,
3515 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3516 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3517 map
->ptr
, map
->stride
);
3519 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3520 map
->x
, map
->y
, map
->w
, map
->h
,
3521 mt
, map
->ptr
, map
->stride
);
3524 map
->unmap
= intel_miptree_unmap_depthstencil
;
3528 * Create and attach a map to the miptree at (level, slice). Return the
3531 static struct intel_miptree_map
*
3532 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3541 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3546 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3547 mt
->level
[level
].slice
[slice
].map
= map
;
3559 * Release the map at (level, slice).
3562 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3566 struct intel_miptree_map
**map
;
3568 map
= &mt
->level
[level
].slice
[slice
].map
;
3574 can_blit_slice(struct intel_mipmap_tree
*mt
,
3575 unsigned int level
, unsigned int slice
)
3577 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3578 if (intel_miptree_blt_pitch(mt
) >= 32768)
3585 use_intel_mipree_map_blit(struct brw_context
*brw
,
3586 struct intel_mipmap_tree
*mt
,
3591 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3593 if (devinfo
->has_llc
&&
3594 /* It's probably not worth swapping to the blit ring because of
3595 * all the overhead involved.
3597 !(mode
& GL_MAP_WRITE_BIT
) &&
3599 (mt
->surf
.tiling
== ISL_TILING_X
||
3600 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3601 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3602 /* Fast copy blit on skl+ supports all tiling formats. */
3603 devinfo
->gen
>= 9) &&
3604 can_blit_slice(mt
, level
, slice
))
3607 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3608 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3609 assert(can_blit_slice(mt
, level
, slice
));
3617 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3618 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3619 * arithmetic overflow.
3621 * If you call this function and use \a out_stride, then you're doing pointer
3622 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3623 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3624 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3625 * which usually have type uint32_t or GLuint.
3628 intel_miptree_map(struct brw_context
*brw
,
3629 struct intel_mipmap_tree
*mt
,
3638 ptrdiff_t *out_stride
)
3640 struct intel_miptree_map
*map
;
3642 assert(mt
->surf
.samples
== 1);
3644 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3651 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3652 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3653 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3654 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3655 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3656 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3657 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3658 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3659 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3660 #if defined(USE_SSE41)
3661 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3662 !mt
->compressed
&& cpu_has_sse4_1
&&
3663 (mt
->surf
.row_pitch
% 16 == 0)) {
3664 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3667 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3670 *out_ptr
= map
->ptr
;
3671 *out_stride
= map
->stride
;
3673 if (map
->ptr
== NULL
)
3674 intel_miptree_release_map(mt
, level
, slice
);
3678 intel_miptree_unmap(struct brw_context
*brw
,
3679 struct intel_mipmap_tree
*mt
,
3683 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3685 assert(mt
->surf
.samples
== 1);
3690 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3691 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3694 map
->unmap(brw
, mt
, map
, level
, slice
);
3696 intel_miptree_release_map(mt
, level
, slice
);
3700 get_isl_surf_dim(GLenum target
)
3704 case GL_TEXTURE_1D_ARRAY
:
3705 return ISL_SURF_DIM_1D
;
3708 case GL_TEXTURE_2D_ARRAY
:
3709 case GL_TEXTURE_RECTANGLE
:
3710 case GL_TEXTURE_CUBE_MAP
:
3711 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3712 case GL_TEXTURE_2D_MULTISAMPLE
:
3713 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3714 case GL_TEXTURE_EXTERNAL_OES
:
3715 return ISL_SURF_DIM_2D
;
3718 return ISL_SURF_DIM_3D
;
3721 unreachable("Invalid texture target");
3725 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3726 enum isl_tiling tiling
, GLenum target
)
3730 case GL_TEXTURE_1D_ARRAY
:
3731 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3732 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3735 case GL_TEXTURE_2D_ARRAY
:
3736 case GL_TEXTURE_RECTANGLE
:
3737 case GL_TEXTURE_2D_MULTISAMPLE
:
3738 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3739 case GL_TEXTURE_EXTERNAL_OES
:
3740 return ISL_DIM_LAYOUT_GEN4_2D
;
3742 case GL_TEXTURE_CUBE_MAP
:
3743 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3744 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3745 ISL_DIM_LAYOUT_GEN4_2D
);
3748 return (devinfo
->gen
>= 9 ?
3749 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3752 unreachable("Invalid texture target");
3756 intel_miptree_set_clear_color(struct brw_context
*brw
,
3757 struct intel_mipmap_tree
*mt
,
3758 union isl_color_value clear_color
)
3760 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3761 mt
->fast_clear_color
= clear_color
;
3762 if (mt
->aux_buf
->clear_color_bo
) {
3763 /* We can't update the clear color while the hardware is still using
3764 * the previous one for a resolve or sampling from it. Make sure that
3765 * there are no pending commands at this point.
3767 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3768 for (int i
= 0; i
< 4; i
++) {
3769 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3770 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3771 mt
->fast_clear_color
.u32
[i
]);
3773 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3775 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3781 union isl_color_value
3782 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3783 const struct intel_mipmap_tree
*mt
,
3784 enum isl_format view_format
, bool sampling
,
3785 struct brw_bo
**clear_color_bo
,
3786 uint32_t *clear_color_offset
)
3788 assert(mt
->aux_buf
);
3790 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3791 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3792 * we switch to using the inline clear color and do the sRGB color
3793 * conversion process defined in the OpenGL spec. The red, green, and
3794 * blue channels take part in gamma correction, while the alpha channel
3797 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3798 for (unsigned i
= 0; i
< 3; i
++) {
3799 srgb_decoded_value
.f32
[i
] =
3800 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3802 *clear_color_bo
= 0;
3803 *clear_color_offset
= 0;
3804 return srgb_decoded_value
;
3806 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3807 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3808 return mt
->fast_clear_color
;