2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
67 /* MCS compression only applies to multisampled miptrees */
68 if (mt
->surf
.samples
<= 1)
71 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
75 /* See isl_surf_get_mcs_surf for details. */
76 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(mt
->format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
106 intel_tiling_supports_ccs(const struct brw_context
*brw
,
107 enum isl_tiling tiling
)
109 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
111 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
112 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
114 * - Support is limited to tiled render targets.
116 * Gen9 changes the restriction to Y-tile only.
118 if (devinfo
->gen
>= 9)
119 return tiling
== ISL_TILING_Y0
;
120 else if (devinfo
->gen
>= 7)
121 return tiling
!= ISL_TILING_LINEAR
;
127 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
128 * can be used. This doesn't (and should not) inspect any of the properties of
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p326):
134 * - Support is for non-mip-mapped and non-array surface types only.
136 * And then later, on p327:
138 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
141 * From the Skylake documentation, it is made clear that X-tiling is no longer
144 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
148 intel_miptree_supports_ccs(struct brw_context
*brw
,
149 const struct intel_mipmap_tree
*mt
)
151 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
153 /* MCS support does not exist prior to Gen7 */
154 if (devinfo
->gen
< 7)
157 /* This function applies only to non-multisampled render targets. */
158 if (mt
->surf
.samples
> 1)
161 /* MCS is only supported for color buffers */
162 if (!_mesa_is_format_color_format(mt
->format
))
165 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
168 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
169 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
170 mt
->surf
.logical_level0_px
.depth
> 1;
173 /* Multisample surfaces with the CMS layout are not layered surfaces,
174 * yet still have physical_depth0 > 1. Assert that we don't
175 * accidentally reject a multisampled surface here. We should have
176 * rejected it earlier by explicitly checking the sample count.
178 assert(mt
->surf
.samples
== 1);
181 /* Handle the hardware restrictions...
183 * All GENs have the following restriction: "MCS buffer for non-MSRT is
184 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
186 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
187 * Non-MultiSampler Render Target Restrictions) Support is for
188 * non-mip-mapped and non-array surface types only.
190 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
195 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
200 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
203 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
204 * work for 3D textures until gen9 where the layout of 3D textures changes
205 * to match 2D array textures.
207 if (devinfo
->gen
<= 8 && mt
->surf
.dim
!= ISL_SURF_DIM_2D
)
210 /* There's no point in using an MCS buffer if the surface isn't in a
213 if (!brw
->mesa_format_supports_render
[mt
->format
])
220 intel_tiling_supports_hiz(const struct brw_context
*brw
,
221 enum isl_tiling tiling
)
223 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
225 if (devinfo
->gen
< 6)
228 return tiling
== ISL_TILING_Y0
;
232 intel_miptree_supports_hiz(const struct brw_context
*brw
,
233 const struct intel_mipmap_tree
*mt
)
238 switch (mt
->format
) {
239 case MESA_FORMAT_Z_FLOAT32
:
240 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
241 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
242 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
243 case MESA_FORMAT_Z_UNORM16
:
251 * Return true if the format that will be used to access the miptree is
252 * CCS_E-compatible with the miptree's linear/non-sRGB format.
254 * Why use the linear format? Well, although the miptree may be specified with
255 * an sRGB format, the usage of that color space/format can be toggled. Since
256 * our HW tends to support more linear formats than sRGB ones, we use this
257 * format variant for check for CCS_E compatibility.
260 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
261 const struct intel_mipmap_tree
*mt
,
262 enum isl_format access_format
)
264 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
266 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
267 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
268 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
272 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
273 const struct intel_mipmap_tree
*mt
)
275 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
277 if (devinfo
->gen
< 9)
280 /* For now compression is only enabled for integer formats even though
281 * there exist supported floating point formats also. This is a heuristic
282 * decision based on current public benchmarks. In none of the cases these
283 * formats provided any improvement but a few cases were seen to regress.
284 * Hence these are left to to be enabled in the future when they are known
287 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
290 if (!intel_miptree_supports_ccs(brw
, mt
))
293 /* Many window system buffers are sRGB even if they are never rendered as
294 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
295 * surface is used as sRGB, we fall back to CCS_D.
297 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
298 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
299 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
303 * Determine depth format corresponding to a depth+stencil format,
304 * for separate stencil.
307 intel_depth_format_for_depthstencil_format(mesa_format format
) {
309 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
310 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
311 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
312 return MESA_FORMAT_Z_FLOAT32
;
319 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
320 unsigned depth0
, struct intel_mipmap_level
*table
)
322 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
324 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
326 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
327 if (!table
[level
].slice
)
334 for (unsigned level
= first_level
; level
<= last_level
; level
++)
335 free(table
[level
].slice
);
341 needs_separate_stencil(const struct brw_context
*brw
,
342 struct intel_mipmap_tree
*mt
,
345 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
347 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
350 if (devinfo
->must_use_separate_stencil
)
353 return brw
->has_separate_stencil
&&
354 intel_miptree_supports_hiz(brw
, mt
);
358 * Choose the aux usage for this miptree. This function must be called fairly
359 * late in the miptree create process after we have a tiling.
362 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
363 struct intel_mipmap_tree
*mt
)
365 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
367 if (intel_miptree_supports_mcs(brw
, mt
)) {
368 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
369 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
370 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
371 intel_miptree_supports_ccs(brw
, mt
)) {
372 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
373 intel_miptree_supports_ccs_e(brw
, mt
)) {
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
378 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
379 intel_miptree_supports_hiz(brw
, mt
)) {
380 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
383 /* We can do fast-clear on all auxiliary surface types that are
384 * allocated through the normal texture creation paths.
386 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
387 mt
->supports_fast_clear
= true;
392 * Choose an appropriate uncompressed format for a requested
393 * compressed format, if unsupported.
396 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
398 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
400 /* No need to lower ETC formats on these platforms,
401 * they are supported natively.
403 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
407 case MESA_FORMAT_ETC1_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_SRGB8
:
412 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
413 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
414 return MESA_FORMAT_B8G8R8A8_SRGB
;
415 case MESA_FORMAT_ETC2_RGBA8_EAC
:
416 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
417 return MESA_FORMAT_R8G8B8A8_UNORM
;
418 case MESA_FORMAT_ETC2_R11_EAC
:
419 return MESA_FORMAT_R_UNORM16
;
420 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
421 return MESA_FORMAT_R_SNORM16
;
422 case MESA_FORMAT_ETC2_RG11_EAC
:
423 return MESA_FORMAT_R16G16_UNORM
;
424 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
425 return MESA_FORMAT_R16G16_SNORM
;
427 /* Non ETC1 / ETC2 format */
433 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
435 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
436 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
438 return mt
->surf
.logical_level0_px
.array_len
;
441 UNUSED
static unsigned
442 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
444 /* In case of physical dimensions one needs to consider also the layout.
445 * See isl_calc_phys_level0_extent_sa().
447 if (surf
->dim
!= ISL_SURF_DIM_3D
)
448 return surf
->phys_level0_sa
.array_len
;
450 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
451 return minify(surf
->phys_level0_sa
.array_len
, level
);
453 return minify(surf
->phys_level0_sa
.depth
, level
);
456 /** \brief Assert that the level and layer are valid for the miptree. */
458 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
466 assert(level
>= mt
->first_level
);
467 assert(level
<= mt
->last_level
);
468 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
471 static enum isl_aux_state
**
472 create_aux_state_map(struct intel_mipmap_tree
*mt
,
473 enum isl_aux_state initial
)
475 const uint32_t levels
= mt
->last_level
+ 1;
477 uint32_t total_slices
= 0;
478 for (uint32_t level
= 0; level
< levels
; level
++)
479 total_slices
+= brw_get_num_logical_layers(mt
, level
);
481 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
483 /* We're going to allocate a single chunk of data for both the per-level
484 * reference array and the arrays of aux_state. This makes cleanup
485 * significantly easier.
487 const size_t total_size
= per_level_array_size
+
488 total_slices
* sizeof(enum isl_aux_state
);
489 void *data
= malloc(total_size
);
493 enum isl_aux_state
**per_level_arr
= data
;
494 enum isl_aux_state
*s
= data
+ per_level_array_size
;
495 for (uint32_t level
= 0; level
< levels
; level
++) {
496 per_level_arr
[level
] = s
;
497 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
498 for (uint32_t a
= 0; a
< level_layers
; a
++)
501 assert((void *)s
== data
+ total_size
);
503 return per_level_arr
;
507 free_aux_state_map(enum isl_aux_state
**state
)
513 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
514 enum isl_tiling tiling
, unsigned samples
)
519 if (tiling
== ISL_TILING_LINEAR
)
522 /* If the width is much smaller than a tile, don't bother tiling. */
526 if (ALIGN(row_pitch
, 512) >= 32768) {
527 perf_debug("row pitch %u too large to blit, falling back to untiled",
536 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
537 enum isl_tiling tiling
)
539 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
541 /* If the BO is too large to fit in the aperture, we need to use the
542 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
543 * handle Y-tiling, so we need to fall back to X.
545 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
546 tiling
== ISL_TILING_Y0
)
552 static struct intel_mipmap_tree
*
553 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
554 unsigned first_level
, unsigned last_level
,
555 unsigned width0
, unsigned height0
, unsigned depth0
,
556 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
557 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
558 unsigned row_pitch
, struct brw_bo
*bo
)
560 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
564 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
572 if (target
== GL_TEXTURE_CUBE_MAP
||
573 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
574 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
576 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
578 _mesa_enum_to_string(target
),
579 _mesa_get_format_name(format
),
580 num_samples
, width0
, height0
, depth0
,
581 first_level
, last_level
, mt
);
583 struct isl_surf_init_info init_info
= {
584 .dim
= get_isl_surf_dim(target
),
585 .format
= translate_tex_format(brw
, format
, false),
588 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
589 .levels
= last_level
- first_level
+ 1,
590 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
591 .samples
= num_samples
,
592 .row_pitch
= row_pitch
,
593 .usage
= isl_usage_flags
,
594 .tiling_flags
= tiling_flags
,
597 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
600 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
601 * on gen7 platforms we also need to create Y-tiled copies of stencil for
602 * texturing since the hardware can't sample from W-tiled surfaces. For
603 * everything else, check for corner cases needing special treatment.
605 bool is_depth_stencil
=
606 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
607 if (!is_depth_stencil
) {
608 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
609 mt
->surf
.tiling
, mt
->surf
.samples
)) {
610 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
611 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
613 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
614 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
615 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
620 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
621 * the size may not be multiple of row_pitch.
622 * See isl_apply_surface_padding().
624 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
625 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
628 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
631 isl_tiling_to_i915_tiling(
633 mt
->surf
.row_pitch
, alloc_flags
);
640 mt
->first_level
= first_level
;
641 mt
->last_level
= last_level
;
644 mt
->aux_state
= NULL
;
645 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
646 mt
->compressed
= _mesa_is_format_compressed(format
);
647 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
652 intel_miptree_release(&mt
);
657 make_separate_stencil_surface(struct brw_context
*brw
,
658 struct intel_mipmap_tree
*mt
)
660 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
661 0, mt
->surf
.levels
- 1,
662 mt
->surf
.logical_level0_px
.width
,
663 mt
->surf
.logical_level0_px
.height
,
664 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
665 mt
->surf
.logical_level0_px
.depth
:
666 mt
->surf
.logical_level0_px
.array_len
,
667 mt
->surf
.samples
, ISL_TILING_W_BIT
,
668 ISL_SURF_USAGE_STENCIL_BIT
|
669 ISL_SURF_USAGE_TEXTURE_BIT
,
670 BO_ALLOC_BUSY
, 0, NULL
);
675 mt
->stencil_mt
->r8stencil_needs_update
= true;
680 static struct intel_mipmap_tree
*
681 miptree_create(struct brw_context
*brw
,
690 enum intel_miptree_create_flags flags
)
692 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
694 if (format
== MESA_FORMAT_S_UINT8
)
695 return make_surface(brw
, target
, format
, first_level
, last_level
,
696 width0
, height0
, depth0
, num_samples
,
698 ISL_SURF_USAGE_STENCIL_BIT
|
699 ISL_SURF_USAGE_TEXTURE_BIT
,
704 const GLenum base_format
= _mesa_get_format_base_format(format
);
705 if ((base_format
== GL_DEPTH_COMPONENT
||
706 base_format
== GL_DEPTH_STENCIL
) &&
707 !(flags
& MIPTREE_CREATE_LINEAR
)) {
708 /* Fix up the Z miptree format for how we're splitting out separate
709 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
711 const mesa_format depth_only_format
=
712 intel_depth_format_for_depthstencil_format(format
);
713 struct intel_mipmap_tree
*mt
= make_surface(
714 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
715 first_level
, last_level
,
716 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
717 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
718 BO_ALLOC_BUSY
, 0, NULL
);
720 if (needs_separate_stencil(brw
, mt
, format
) &&
721 !make_separate_stencil_surface(brw
, mt
)) {
722 intel_miptree_release(&mt
);
726 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
727 intel_miptree_choose_aux_usage(brw
, mt
);
732 mesa_format tex_format
= format
;
733 mesa_format etc_format
= MESA_FORMAT_NONE
;
734 uint32_t alloc_flags
= 0;
736 format
= intel_lower_compressed_format(brw
, format
);
738 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
740 if (flags
& MIPTREE_CREATE_BUSY
)
741 alloc_flags
|= BO_ALLOC_BUSY
;
743 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
744 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
746 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
747 if (devinfo
->gen
< 6)
748 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
750 struct intel_mipmap_tree
*mt
= make_surface(
752 first_level
, last_level
,
753 width0
, height0
, depth0
,
754 num_samples
, tiling_flags
,
755 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
756 ISL_SURF_USAGE_TEXTURE_BIT
,
757 alloc_flags
, 0, NULL
);
761 mt
->etc_format
= etc_format
;
763 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
764 intel_miptree_choose_aux_usage(brw
, mt
);
769 struct intel_mipmap_tree
*
770 intel_miptree_create(struct brw_context
*brw
,
779 enum intel_miptree_create_flags flags
)
781 assert(num_samples
> 0);
783 struct intel_mipmap_tree
*mt
= miptree_create(
785 first_level
, last_level
,
786 width0
, height0
, depth0
, num_samples
,
793 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
794 * compress clear color so we wait until an actual fast-clear to allocate
797 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
798 !intel_miptree_alloc_aux(brw
, mt
)) {
799 intel_miptree_release(&mt
);
806 struct intel_mipmap_tree
*
807 intel_miptree_create_for_bo(struct brw_context
*brw
,
815 enum isl_tiling tiling
,
816 enum intel_miptree_create_flags flags
)
818 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
819 struct intel_mipmap_tree
*mt
;
820 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
821 const GLenum base_format
= _mesa_get_format_base_format(format
);
823 if ((base_format
== GL_DEPTH_COMPONENT
||
824 base_format
== GL_DEPTH_STENCIL
)) {
825 const mesa_format depth_only_format
=
826 intel_depth_format_for_depthstencil_format(format
);
827 mt
= make_surface(brw
, target
,
828 devinfo
->gen
>= 6 ? depth_only_format
: format
,
829 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
830 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
835 brw_bo_reference(bo
);
837 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
838 intel_miptree_choose_aux_usage(brw
, mt
);
841 } else if (format
== MESA_FORMAT_S_UINT8
) {
842 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
843 0, 0, width
, height
, depth
, 1,
845 ISL_SURF_USAGE_STENCIL_BIT
|
846 ISL_SURF_USAGE_TEXTURE_BIT
,
851 assert(bo
->size
>= mt
->surf
.size
);
853 brw_bo_reference(bo
);
857 /* Nothing will be able to use this miptree with the BO if the offset isn't
860 if (tiling
!= ISL_TILING_LINEAR
)
861 assert(offset
% 4096 == 0);
863 /* miptrees can't handle negative pitch. If you need flipping of images,
864 * that's outside of the scope of the mt.
868 /* The BO already has a tiling format and we shouldn't confuse the lower
869 * layers by making it try to find a tiling format again.
871 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
873 mt
= make_surface(brw
, target
, format
,
874 0, 0, width
, height
, depth
, 1,
876 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
877 ISL_SURF_USAGE_TEXTURE_BIT
,
882 brw_bo_reference(bo
);
886 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
887 intel_miptree_choose_aux_usage(brw
, mt
);
889 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
890 * only compress clear color so we wait until an actual fast-clear to
893 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
894 !intel_miptree_alloc_aux(brw
, mt
)) {
895 intel_miptree_release(&mt
);
903 static struct intel_mipmap_tree
*
904 miptree_create_for_planar_image(struct brw_context
*brw
,
905 __DRIimage
*image
, GLenum target
,
906 enum isl_tiling tiling
)
908 const struct intel_image_format
*f
= image
->planar_format
;
909 struct intel_mipmap_tree
*planar_mt
= NULL
;
911 for (int i
= 0; i
< f
->nplanes
; i
++) {
912 const int index
= f
->planes
[i
].buffer_index
;
913 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
914 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
915 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
916 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
918 /* Disable creation of the texture's aux buffers because the driver
919 * exposes no EGL API to manage them. That is, there is no API for
920 * resolving the aux buffer's content to the main buffer nor for
921 * invalidating the aux buffer's content.
923 struct intel_mipmap_tree
*mt
=
924 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
925 image
->offsets
[index
],
927 image
->strides
[index
],
929 MIPTREE_CREATE_NO_AUX
);
938 planar_mt
->plane
[i
- 1] = mt
;
941 planar_mt
->drm_modifier
= image
->modifier
;
947 create_ccs_buf_for_image(struct brw_context
*brw
,
949 struct intel_mipmap_tree
*mt
,
950 enum isl_aux_state initial_state
)
952 struct isl_surf temp_ccs_surf
;
954 /* CCS is only supported for very simple miptrees */
955 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
956 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
957 assert(mt
->surf
.samples
== 1);
958 assert(mt
->surf
.levels
== 1);
959 assert(mt
->surf
.logical_level0_px
.depth
== 1);
960 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
961 assert(mt
->first_level
== 0);
962 assert(mt
->last_level
== 0);
964 /* We shouldn't already have a CCS */
965 assert(!mt
->aux_buf
);
967 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
971 assert(image
->aux_offset
< image
->bo
->size
);
972 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
974 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
975 if (mt
->aux_buf
== NULL
)
978 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
979 if (!mt
->aux_state
) {
985 /* On gen10+ we start using an extra space in the aux buffer to store the
986 * indirect clear color. However, if we imported an image from the window
987 * system with CCS, we don't have the extra space at the end of the aux
988 * buffer. So create a new bo here that will store that clear color.
990 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
991 mt
->aux_buf
->clear_color_bo
=
992 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
993 brw
->isl_dev
.ss
.clear_color_state_size
,
994 BRW_MEMZONE_OTHER
, I915_TILING_NONE
, 0,
996 if (!mt
->aux_buf
->clear_color_bo
) {
1003 mt
->aux_buf
->bo
= image
->bo
;
1004 brw_bo_reference(image
->bo
);
1006 mt
->aux_buf
->offset
= image
->aux_offset
;
1007 mt
->aux_buf
->surf
= temp_ccs_surf
;
1012 struct intel_mipmap_tree
*
1013 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1014 __DRIimage
*image
, GLenum target
,
1016 bool is_winsys_image
)
1018 uint32_t bo_tiling
, bo_swizzle
;
1019 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1021 const struct isl_drm_modifier_info
*mod_info
=
1022 isl_drm_modifier_get_info(image
->modifier
);
1024 const enum isl_tiling tiling
=
1025 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1027 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1028 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1030 if (image
->planar_format
)
1031 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1033 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1034 /* The texture storage paths in core Mesa detect if the driver does not
1035 * support the user-requested format, and then searches for a
1036 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1037 * do the fallbacks here for important formats.
1039 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1040 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1041 * the Chrome OS compositor consumes as dma_buf EGLImages.
1043 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1046 if (!brw
->ctx
.TextureFormatSupported
[format
])
1049 enum intel_miptree_create_flags mt_create_flags
= 0;
1051 /* If this image comes in from a window system, we have different
1052 * requirements than if it comes in via an EGL import operation. Window
1053 * system images can use any form of auxiliary compression we wish because
1054 * they get "flushed" before being handed off to the window system and we
1055 * have the opportunity to do resolves. Non window-system images, on the
1056 * other hand, have no resolve point so we can't have aux without a
1059 if (!is_winsys_image
)
1060 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1062 /* If we have a modifier which specifies aux, don't create one yet */
1063 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1064 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1066 /* Disable creation of the texture's aux buffers because the driver exposes
1067 * no EGL API to manage them. That is, there is no API for resolving the aux
1068 * buffer's content to the main buffer nor for invalidating the aux buffer's
1071 struct intel_mipmap_tree
*mt
=
1072 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1073 image
->offset
, image
->width
, image
->height
, 1,
1074 image
->pitch
, tiling
, mt_create_flags
);
1078 mt
->target
= target
;
1079 mt
->level
[0].level_x
= image
->tile_x
;
1080 mt
->level
[0].level_y
= image
->tile_y
;
1081 mt
->drm_modifier
= image
->modifier
;
1083 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1084 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1085 * trouble resolving back to destination image due to alignment issues.
1087 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1088 if (!devinfo
->has_surface_tile_offset
) {
1089 uint32_t draw_x
, draw_y
;
1090 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1092 if (draw_x
!= 0 || draw_y
!= 0) {
1093 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1094 intel_miptree_release(&mt
);
1099 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1100 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1102 mt
->aux_usage
= mod_info
->aux_usage
;
1103 /* If we are a window system buffer, then we can support fast-clears
1104 * even if the modifier doesn't support them by doing a partial resolve
1105 * as part of the flush operation.
1107 mt
->supports_fast_clear
=
1108 is_winsys_image
|| mod_info
->supports_clear_color
;
1110 /* We don't know the actual state of the surface when we get it but we
1111 * can make a pretty good guess based on the modifier. What we do know
1112 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1113 * a worst case of compression.
1115 enum isl_aux_state initial_state
=
1116 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1118 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1119 intel_miptree_release(&mt
);
1124 /* Don't assume coherency for imported EGLimages. We don't know what
1125 * external clients are going to do with it. They may scan it out.
1127 image
->bo
->cache_coherent
= false;
1133 * For a singlesample renderbuffer, this simply wraps the given BO with a
1136 * For a multisample renderbuffer, this wraps the window system's
1137 * (singlesample) BO with a singlesample miptree attached to the
1138 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1139 * that will contain the actual rendering (which is lazily resolved to
1140 * irb->singlesample_mt).
1143 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1144 struct intel_renderbuffer
*irb
,
1145 struct intel_mipmap_tree
*singlesample_mt
,
1146 uint32_t width
, uint32_t height
,
1149 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1150 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1151 mesa_format format
= rb
->Format
;
1152 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1154 /* Only the front and back buffers, which are color buffers, are allocated
1155 * through the image loader.
1157 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1158 _mesa_get_format_base_format(format
) == GL_RGBA
);
1160 assert(singlesample_mt
);
1162 if (num_samples
== 1) {
1163 intel_miptree_release(&irb
->mt
);
1164 irb
->mt
= singlesample_mt
;
1166 assert(!irb
->singlesample_mt
);
1168 intel_miptree_release(&irb
->singlesample_mt
);
1169 irb
->singlesample_mt
= singlesample_mt
;
1172 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1173 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1174 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1179 if (!multisample_mt
)
1182 irb
->need_downsample
= false;
1183 intel_miptree_release(&irb
->mt
);
1184 irb
->mt
= multisample_mt
;
1190 intel_miptree_release(&irb
->mt
);
1194 struct intel_mipmap_tree
*
1195 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1199 uint32_t num_samples
)
1201 struct intel_mipmap_tree
*mt
;
1203 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1205 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1206 width
, height
, depth
, num_samples
,
1207 MIPTREE_CREATE_BUSY
);
1214 intel_miptree_release(&mt
);
1219 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1220 struct intel_mipmap_tree
*src
)
1225 intel_miptree_release(dst
);
1229 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1236 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1238 if (aux_buf
== NULL
)
1241 brw_bo_unreference(aux_buf
->bo
);
1242 brw_bo_unreference(aux_buf
->clear_color_bo
);
1248 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1253 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1254 if (--(*mt
)->refcount
<= 0) {
1257 DBG("%s deleting %p\n", __func__
, *mt
);
1259 brw_bo_unreference((*mt
)->bo
);
1260 intel_miptree_release(&(*mt
)->stencil_mt
);
1261 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1262 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1263 free_aux_state_map((*mt
)->aux_state
);
1265 intel_miptree_release(&(*mt
)->plane
[0]);
1266 intel_miptree_release(&(*mt
)->plane
[1]);
1268 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1269 free((*mt
)->level
[i
].slice
);
1279 intel_get_image_dims(struct gl_texture_image
*image
,
1280 int *width
, int *height
, int *depth
)
1282 switch (image
->TexObject
->Target
) {
1283 case GL_TEXTURE_1D_ARRAY
:
1284 /* For a 1D Array texture the OpenGL API will treat the image height as
1285 * the number of array slices. For Intel hardware, we treat the 1D array
1286 * as a 2D Array with a height of 1. So, here we want to swap image
1289 assert(image
->Depth
== 1);
1290 *width
= image
->Width
;
1292 *depth
= image
->Height
;
1294 case GL_TEXTURE_CUBE_MAP
:
1295 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1296 * though we really have 6 slices.
1298 assert(image
->Depth
== 1);
1299 *width
= image
->Width
;
1300 *height
= image
->Height
;
1304 *width
= image
->Width
;
1305 *height
= image
->Height
;
1306 *depth
= image
->Depth
;
1312 * Can the image be pulled into a unified mipmap tree? This mirrors
1313 * the completeness test in a lot of ways.
1315 * Not sure whether I want to pass gl_texture_image here.
1318 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1319 struct gl_texture_image
*image
)
1321 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1322 GLuint level
= intelImage
->base
.Base
.Level
;
1323 int width
, height
, depth
;
1325 /* glTexImage* choose the texture object based on the target passed in, and
1326 * objects can't change targets over their lifetimes, so this should be
1329 assert(image
->TexObject
->Target
== mt
->target
);
1331 mesa_format mt_format
= mt
->format
;
1332 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1333 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1334 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1335 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1336 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1337 mt_format
= mt
->etc_format
;
1339 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1340 _mesa_get_srgb_format_linear(mt_format
))
1343 intel_get_image_dims(image
, &width
, &height
, &depth
);
1345 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1348 if (level
>= mt
->surf
.levels
)
1351 const unsigned level_depth
=
1352 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1353 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1354 mt
->surf
.logical_level0_px
.array_len
;
1356 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1357 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1358 depth
== level_depth
&&
1359 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1363 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1364 GLuint level
, GLuint slice
,
1365 GLuint
*x
, GLuint
*y
)
1367 if (level
== 0 && slice
== 0) {
1368 *x
= mt
->level
[0].level_x
;
1369 *y
= mt
->level
[0].level_y
;
1373 uint32_t x_offset_sa
, y_offset_sa
;
1375 /* Miptree itself can have an offset only if it represents a single
1376 * slice in an imported buffer object.
1377 * See intel_miptree_create_for_dri_image().
1379 assert(mt
->level
[0].level_x
== 0);
1380 assert(mt
->level
[0].level_y
== 0);
1382 /* Given level is relative to level zero while the miptree may be
1383 * represent just a subset of all levels starting from 'first_level'.
1385 assert(level
>= mt
->first_level
);
1386 level
-= mt
->first_level
;
1388 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1389 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1390 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1391 &x_offset_sa
, &y_offset_sa
);
1399 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1400 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1401 * and tile_h is set to 1.
1404 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1405 uint32_t *tile_w
, uint32_t *tile_h
)
1416 case ISL_TILING_LINEAR
:
1421 unreachable("not reached");
1427 * This function computes masks that may be used to select the bits of the X
1428 * and Y coordinates that indicate the offset within a tile. If the BO is
1429 * untiled, the masks are set to 0.
1432 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1433 uint32_t *mask_x
, uint32_t *mask_y
)
1435 uint32_t tile_w_bytes
, tile_h
;
1437 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1439 *mask_x
= tile_w_bytes
/ cpp
- 1;
1440 *mask_y
= tile_h
- 1;
1444 * Compute the offset (in bytes) from the start of the BO to the given x
1445 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1446 * multiples of the tile size.
1449 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1450 uint32_t x
, uint32_t y
)
1453 uint32_t pitch
= mt
->surf
.row_pitch
;
1455 switch (mt
->surf
.tiling
) {
1457 unreachable("not reached");
1458 case ISL_TILING_LINEAR
:
1459 return y
* pitch
+ x
* cpp
;
1461 assert((x
% (512 / cpp
)) == 0);
1462 assert((y
% 8) == 0);
1463 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1465 assert((x
% (128 / cpp
)) == 0);
1466 assert((y
% 32) == 0);
1467 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1472 * Rendering with tiled buffers requires that the base address of the buffer
1473 * be aligned to a page boundary. For renderbuffers, and sometimes with
1474 * textures, we may want the surface to point at a texture image level that
1475 * isn't at a page boundary.
1477 * This function returns an appropriately-aligned base offset
1478 * according to the tiling restrictions, plus any required x/y offset
1482 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1483 GLuint level
, GLuint slice
,
1488 uint32_t mask_x
, mask_y
;
1490 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1491 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1493 *tile_x
= x
& mask_x
;
1494 *tile_y
= y
& mask_y
;
1496 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1500 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1501 struct intel_mipmap_tree
*src_mt
,
1502 unsigned src_level
, unsigned src_layer
,
1503 struct intel_mipmap_tree
*dst_mt
,
1504 unsigned dst_level
, unsigned dst_layer
,
1505 unsigned width
, unsigned height
)
1508 ptrdiff_t src_stride
, dst_stride
;
1509 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1511 intel_miptree_map(brw
, src_mt
,
1512 src_level
, src_layer
,
1515 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1518 intel_miptree_map(brw
, dst_mt
,
1519 dst_level
, dst_layer
,
1522 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1526 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1527 _mesa_get_format_name(src_mt
->format
),
1528 src_mt
, src
, src_stride
,
1529 _mesa_get_format_name(dst_mt
->format
),
1530 dst_mt
, dst
, dst_stride
,
1533 int row_size
= cpp
* width
;
1534 if (src_stride
== row_size
&&
1535 dst_stride
== row_size
) {
1536 memcpy(dst
, src
, row_size
* height
);
1538 for (int i
= 0; i
< height
; i
++) {
1539 memcpy(dst
, src
, row_size
);
1545 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1546 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1548 /* Don't forget to copy the stencil data over, too. We could have skipped
1549 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1550 * shuffling the two data sources in/out of temporary storage instead of
1551 * the direct mapping we get this way.
1553 if (dst_mt
->stencil_mt
) {
1554 assert(src_mt
->stencil_mt
);
1555 intel_miptree_copy_slice_sw(brw
,
1556 src_mt
->stencil_mt
, src_level
, src_layer
,
1557 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1563 intel_miptree_copy_slice(struct brw_context
*brw
,
1564 struct intel_mipmap_tree
*src_mt
,
1565 unsigned src_level
, unsigned src_layer
,
1566 struct intel_mipmap_tree
*dst_mt
,
1567 unsigned dst_level
, unsigned dst_layer
)
1570 mesa_format format
= src_mt
->format
;
1571 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1572 src_level
- src_mt
->first_level
);
1573 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1574 src_level
- src_mt
->first_level
);
1576 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1577 src_level
- src_mt
->first_level
));
1579 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1580 _mesa_get_srgb_format_linear(dst_mt
->format
));
1582 if (dst_mt
->compressed
) {
1584 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1585 height
= ALIGN_NPOT(height
, j
) / j
;
1586 width
= ALIGN_NPOT(width
, i
) / i
;
1589 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1590 * below won't apply since we can't do the depth's Y tiling or the
1591 * stencil's W tiling in the blitter.
1593 if (src_mt
->stencil_mt
) {
1594 intel_miptree_copy_slice_sw(brw
,
1595 src_mt
, src_level
, src_layer
,
1596 dst_mt
, dst_level
, dst_layer
,
1601 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1602 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1604 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1607 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1608 _mesa_get_format_name(src_mt
->format
),
1609 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1610 _mesa_get_format_name(dst_mt
->format
),
1611 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1614 if (!intel_miptree_blit(brw
,
1615 src_mt
, src_level
, src_layer
, 0, 0, false,
1616 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1617 width
, height
, COLOR_LOGICOP_COPY
)) {
1618 perf_debug("miptree validate blit for %s failed\n",
1619 _mesa_get_format_name(format
));
1621 intel_miptree_copy_slice_sw(brw
,
1622 src_mt
, src_level
, src_layer
,
1623 dst_mt
, dst_level
, dst_layer
,
1629 * Copies the image's current data to the given miptree, and associates that
1630 * miptree with the image.
1633 intel_miptree_copy_teximage(struct brw_context
*brw
,
1634 struct intel_texture_image
*intelImage
,
1635 struct intel_mipmap_tree
*dst_mt
)
1637 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1638 struct intel_texture_object
*intel_obj
=
1639 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1640 int level
= intelImage
->base
.Base
.Level
;
1641 const unsigned face
= intelImage
->base
.Base
.Face
;
1642 unsigned start_layer
, end_layer
;
1644 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1646 assert(intelImage
->base
.Base
.Height
);
1648 end_layer
= intelImage
->base
.Base
.Height
- 1;
1649 } else if (face
> 0) {
1653 assert(intelImage
->base
.Base
.Depth
);
1655 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1658 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1659 intel_miptree_copy_slice(brw
,
1664 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1665 intel_obj
->needs_validate
= true;
1668 static struct intel_miptree_aux_buffer
*
1669 intel_alloc_aux_buffer(struct brw_context
*brw
,
1670 const struct isl_surf
*aux_surf
,
1672 uint8_t memset_value
)
1674 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1678 uint64_t size
= aux_surf
->size
;
1680 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1681 if (has_indirect_clear
) {
1682 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1683 * will set a pointer to a dword somewhere that contains the color. So,
1684 * allocate the space for the clear color value here on the aux buffer.
1686 buf
->clear_color_offset
= size
;
1687 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1690 /* If the buffer needs to be initialised (requiring the buffer to be
1691 * immediately mapped to cpu space for writing), do not use the gpu access
1692 * flag which can cause an unnecessary delay if the backing pages happened
1693 * to be just used by the GPU.
1695 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1696 const bool needs_memset
=
1697 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1698 const uint32_t alloc_flags
=
1699 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1701 /* ISL has stricter set of alignment rules then the drm allocator.
1702 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1703 * trying to recalculate based on different format block sizes.
1705 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1706 BRW_MEMZONE_OTHER
, I915_TILING_Y
,
1707 aux_surf
->row_pitch
, alloc_flags
);
1713 /* Initialize the bo to the desired value */
1715 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1717 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1719 intel_miptree_aux_buffer_free(buf
);
1723 /* Memset the aux_surf portion of the BO. */
1725 memset(map
, memset_value
, aux_surf
->size
);
1727 /* Zero the indirect clear color to match ::fast_clear_color. */
1728 if (has_indirect_clear
) {
1729 memset((char *)map
+ buf
->clear_color_offset
, 0,
1730 brw
->isl_dev
.ss
.clear_color_state_size
);
1733 brw_bo_unmap(buf
->bo
);
1736 if (has_indirect_clear
) {
1737 buf
->clear_color_bo
= buf
->bo
;
1738 brw_bo_reference(buf
->clear_color_bo
);
1741 buf
->surf
= *aux_surf
;
1748 * Helper for intel_miptree_alloc_aux() that sets
1749 * \c mt->level[level].has_hiz. Return true if and only if
1750 * \c has_hiz was set.
1753 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1754 struct intel_mipmap_tree
*mt
,
1757 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1759 assert(mt
->aux_buf
);
1760 assert(mt
->surf
.size
> 0);
1762 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1763 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1764 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1766 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1767 * and the height is 4 aligned. This allows our HiZ support
1768 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1769 * we can grow the width & height to allow the HiZ op to
1770 * force the proper size alignments.
1772 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1773 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1778 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1779 mt
->level
[level
].has_hiz
= true;
1785 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1787 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1788 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1789 * compress clear color so we wait until an actual fast-clear to allocate it.
1792 intel_miptree_alloc_aux(struct brw_context
*brw
,
1793 struct intel_mipmap_tree
*mt
)
1795 assert(mt
->aux_buf
== NULL
);
1797 /* Get the aux buf allocation parameters for this miptree. */
1798 enum isl_aux_state initial_state
;
1799 uint8_t memset_value
;
1800 struct isl_surf aux_surf
;
1801 MAYBE_UNUSED
bool aux_surf_ok
;
1803 switch (mt
->aux_usage
) {
1804 case ISL_AUX_USAGE_NONE
:
1808 case ISL_AUX_USAGE_HIZ
:
1809 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1810 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1812 case ISL_AUX_USAGE_MCS
:
1813 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1815 * When MCS buffer is enabled and bound to MSRT, it is required that
1816 * it is cleared prior to any rendering.
1818 * Since we don't use the MCS buffer for any purpose other than
1819 * rendering, it makes sense to just clear it immediately upon
1822 * Note: the clear value for MCS buffers is all 1's, so we memset to
1825 initial_state
= ISL_AUX_STATE_CLEAR
;
1826 memset_value
= 0xFF;
1827 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1829 case ISL_AUX_USAGE_CCS_D
:
1830 case ISL_AUX_USAGE_CCS_E
:
1831 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1832 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1835 * "If Software wants to enable Color Compression without Fast
1836 * clear, Software needs to initialize MCS with zeros."
1838 * A CCS value of 0 indicates that the corresponding block is in the
1839 * pass-through state which is what we want.
1841 * For CCS_D, do the same thing. On gen9+, this avoids having any
1842 * undefined bits in the aux buffer.
1844 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1847 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1851 /* We should have a valid aux_surf. */
1852 assert(aux_surf_ok
);
1854 /* No work is needed for a zero-sized auxiliary buffer. */
1855 if (aux_surf
.size
== 0)
1858 /* Create the aux_state for the auxiliary buffer. */
1859 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1860 if (mt
->aux_state
== NULL
)
1863 /* Allocate the auxiliary buffer. */
1864 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1865 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1867 if (mt
->aux_buf
== NULL
) {
1868 free_aux_state_map(mt
->aux_state
);
1869 mt
->aux_state
= NULL
;
1873 /* Perform aux_usage-specific initialization. */
1874 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1875 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1876 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1884 * Can the miptree sample using the hiz buffer?
1887 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1888 struct intel_mipmap_tree
*mt
)
1890 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1892 if (!devinfo
->has_sample_with_hiz
) {
1900 /* It seems the hardware won't fallback to the depth buffer if some of the
1901 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1902 * of the texture to be HiZ enabled.
1904 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1905 if (!intel_miptree_level_has_hiz(mt
, level
))
1909 /* If compressed multisampling is enabled, then we use it for the auxiliary
1912 * From the BDW PRM (Volume 2d: Command Reference: Structures
1913 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1915 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1916 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1918 * There is no such blurb for 1D textures, but there is sufficient evidence
1919 * that this is broken on SKL+.
1921 return (mt
->surf
.samples
== 1 &&
1922 mt
->target
!= GL_TEXTURE_3D
&&
1923 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1927 * Does the miptree slice have hiz enabled?
1930 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1932 intel_miptree_check_level_layer(mt
, level
, 0);
1933 return mt
->level
[level
].has_hiz
;
1936 static inline uint32_t
1937 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1938 uint32_t start_level
, uint32_t num_levels
)
1940 assert(start_level
>= mt
->first_level
);
1941 assert(start_level
<= mt
->last_level
);
1943 if (num_levels
== INTEL_REMAINING_LAYERS
)
1944 num_levels
= mt
->last_level
- start_level
+ 1;
1945 /* Check for overflow */
1946 assert(start_level
+ num_levels
>= start_level
);
1947 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1952 static inline uint32_t
1953 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1954 uint32_t start_layer
, uint32_t num_layers
)
1956 assert(level
<= mt
->last_level
);
1958 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1959 assert(start_layer
< total_num_layers
);
1960 if (num_layers
== INTEL_REMAINING_LAYERS
)
1961 num_layers
= total_num_layers
- start_layer
;
1962 /* Check for overflow */
1963 assert(start_layer
+ num_layers
>= start_layer
);
1964 assert(start_layer
+ num_layers
<= total_num_layers
);
1970 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1971 unsigned start_level
, unsigned num_levels
,
1972 unsigned start_layer
, unsigned num_layers
)
1974 assert(_mesa_is_format_color_format(mt
->format
));
1979 /* Clamp the level range to fit the miptree */
1980 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1982 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1983 const uint32_t level
= start_level
+ l
;
1984 const uint32_t level_layers
=
1985 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1986 for (unsigned a
= 0; a
< level_layers
; a
++) {
1987 enum isl_aux_state aux_state
=
1988 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1989 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1990 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1999 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2000 const struct intel_mipmap_tree
*mt
,
2001 unsigned level
, unsigned layer
)
2006 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2007 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2008 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2010 /* Compression of arrayed msaa surfaces is supported. */
2011 if (mt
->surf
.samples
> 1)
2014 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2015 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2017 mt
->surf
.logical_level0_px
.depth
== 1 &&
2018 mt
->surf
.logical_level0_px
.array_len
== 1));
2024 static enum isl_aux_op
2025 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2026 enum isl_aux_usage aux_usage
,
2027 bool fast_clear_supported
)
2029 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2031 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2033 assert(ccs_supported
== fast_clear_supported
);
2035 switch (aux_state
) {
2036 case ISL_AUX_STATE_CLEAR
:
2037 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2039 return ISL_AUX_OP_FULL_RESOLVE
;
2041 return ISL_AUX_OP_NONE
;
2043 case ISL_AUX_STATE_PASS_THROUGH
:
2044 return ISL_AUX_OP_NONE
;
2046 case ISL_AUX_STATE_RESOLVED
:
2047 case ISL_AUX_STATE_AUX_INVALID
:
2048 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2049 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2053 unreachable("Invalid aux state for CCS_D");
2056 static enum isl_aux_op
2057 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2058 enum isl_aux_usage aux_usage
,
2059 bool fast_clear_supported
)
2061 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2062 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2063 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2064 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2066 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2067 assert(fast_clear_supported
);
2069 switch (aux_state
) {
2070 case ISL_AUX_STATE_CLEAR
:
2071 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2072 if (fast_clear_supported
)
2073 return ISL_AUX_OP_NONE
;
2074 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2075 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2077 return ISL_AUX_OP_FULL_RESOLVE
;
2079 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2080 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2081 return ISL_AUX_OP_FULL_RESOLVE
;
2082 else if (!fast_clear_supported
)
2083 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2085 return ISL_AUX_OP_NONE
;
2087 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2088 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2089 return ISL_AUX_OP_FULL_RESOLVE
;
2091 return ISL_AUX_OP_NONE
;
2093 case ISL_AUX_STATE_PASS_THROUGH
:
2094 return ISL_AUX_OP_NONE
;
2096 case ISL_AUX_STATE_RESOLVED
:
2097 case ISL_AUX_STATE_AUX_INVALID
:
2101 unreachable("Invalid aux state for CCS_E");
2105 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2106 struct intel_mipmap_tree
*mt
,
2107 uint32_t level
, uint32_t layer
,
2108 enum isl_aux_usage aux_usage
,
2109 bool fast_clear_supported
)
2111 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2113 enum isl_aux_op resolve_op
;
2114 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2115 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2116 fast_clear_supported
);
2118 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2119 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2120 fast_clear_supported
);
2123 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2124 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2125 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2127 switch (resolve_op
) {
2128 case ISL_AUX_OP_FULL_RESOLVE
:
2129 /* The CCS full resolve operation destroys the CCS and sets it to the
2130 * pass-through state. (You can also think of this as being both a
2131 * resolve and an ambiguate in one operation.)
2133 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2134 ISL_AUX_STATE_PASS_THROUGH
);
2137 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2138 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2139 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2143 unreachable("Invalid resolve op");
2149 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2150 struct intel_mipmap_tree
*mt
,
2151 uint32_t level
, uint32_t layer
,
2152 enum isl_aux_usage aux_usage
)
2154 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2155 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2156 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2158 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2160 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2161 switch (aux_state
) {
2162 case ISL_AUX_STATE_CLEAR
:
2163 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2164 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2165 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2167 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2168 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2169 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2170 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2171 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2172 ISL_AUX_STATE_PARTIAL_CLEAR
);
2176 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2177 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2178 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2179 break; /* Nothing to do */
2181 case ISL_AUX_STATE_PASS_THROUGH
:
2182 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2183 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2184 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2190 case ISL_AUX_STATE_RESOLVED
:
2191 case ISL_AUX_STATE_AUX_INVALID
:
2192 unreachable("Invalid aux state for CCS_E");
2195 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2196 /* CCS_D is a bit simpler */
2197 switch (aux_state
) {
2198 case ISL_AUX_STATE_CLEAR
:
2199 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2200 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2201 ISL_AUX_STATE_PARTIAL_CLEAR
);
2204 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2205 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2206 break; /* Nothing to do */
2208 case ISL_AUX_STATE_PASS_THROUGH
:
2212 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2213 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2214 case ISL_AUX_STATE_RESOLVED
:
2215 case ISL_AUX_STATE_AUX_INVALID
:
2216 unreachable("Invalid aux state for CCS_D");
2222 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2223 struct intel_mipmap_tree
*mt
,
2225 enum isl_aux_usage aux_usage
,
2226 bool fast_clear_supported
)
2228 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2230 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2231 case ISL_AUX_STATE_CLEAR
:
2232 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2233 if (!fast_clear_supported
) {
2234 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2235 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2236 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2240 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2241 break; /* Nothing to do */
2243 case ISL_AUX_STATE_RESOLVED
:
2244 case ISL_AUX_STATE_PASS_THROUGH
:
2245 case ISL_AUX_STATE_AUX_INVALID
:
2246 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2247 unreachable("Invalid aux state for MCS");
2252 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2253 struct intel_mipmap_tree
*mt
,
2255 enum isl_aux_usage aux_usage
)
2257 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2259 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2260 case ISL_AUX_STATE_CLEAR
:
2261 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2262 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2265 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2266 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2267 break; /* Nothing to do */
2269 case ISL_AUX_STATE_RESOLVED
:
2270 case ISL_AUX_STATE_PASS_THROUGH
:
2271 case ISL_AUX_STATE_AUX_INVALID
:
2272 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2273 unreachable("Invalid aux state for MCS");
2278 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2279 struct intel_mipmap_tree
*mt
,
2280 uint32_t level
, uint32_t layer
,
2281 enum isl_aux_usage aux_usage
,
2282 bool fast_clear_supported
)
2284 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2286 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2287 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2288 case ISL_AUX_STATE_CLEAR
:
2289 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2290 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2291 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2294 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2295 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2296 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2299 case ISL_AUX_STATE_PASS_THROUGH
:
2300 case ISL_AUX_STATE_RESOLVED
:
2303 case ISL_AUX_STATE_AUX_INVALID
:
2304 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2305 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2308 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2309 unreachable("Invalid HiZ state");
2312 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2313 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2316 case ISL_AUX_OP_FULL_RESOLVE
:
2317 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2318 ISL_AUX_STATE_RESOLVED
);
2321 case ISL_AUX_OP_AMBIGUATE
:
2322 /* The HiZ resolve operation is actually an ambiguate */
2323 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2324 ISL_AUX_STATE_PASS_THROUGH
);
2328 unreachable("Invalid HiZ op");
2334 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2335 struct intel_mipmap_tree
*mt
,
2336 uint32_t level
, uint32_t layer
,
2337 enum isl_aux_usage aux_usage
)
2339 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2341 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2342 case ISL_AUX_STATE_CLEAR
:
2343 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2344 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2345 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2348 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2349 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2350 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2351 break; /* Nothing to do */
2353 case ISL_AUX_STATE_RESOLVED
:
2354 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2355 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2356 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2358 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2359 ISL_AUX_STATE_AUX_INVALID
);
2363 case ISL_AUX_STATE_PASS_THROUGH
:
2364 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2365 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2366 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2370 case ISL_AUX_STATE_AUX_INVALID
:
2371 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2374 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2375 unreachable("Invalid HiZ state");
2380 intel_miptree_prepare_access(struct brw_context
*brw
,
2381 struct intel_mipmap_tree
*mt
,
2382 uint32_t start_level
, uint32_t num_levels
,
2383 uint32_t start_layer
, uint32_t num_layers
,
2384 enum isl_aux_usage aux_usage
,
2385 bool fast_clear_supported
)
2387 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2389 switch (mt
->aux_usage
) {
2390 case ISL_AUX_USAGE_NONE
:
2394 case ISL_AUX_USAGE_MCS
:
2395 assert(mt
->aux_buf
);
2396 assert(start_level
== 0 && num_levels
== 1);
2397 const uint32_t level_layers
=
2398 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2399 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2400 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2401 aux_usage
, fast_clear_supported
);
2405 case ISL_AUX_USAGE_CCS_D
:
2406 case ISL_AUX_USAGE_CCS_E
:
2410 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2411 const uint32_t level
= start_level
+ l
;
2412 const uint32_t level_layers
=
2413 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2414 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2415 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2417 aux_usage
, fast_clear_supported
);
2422 case ISL_AUX_USAGE_HIZ
:
2423 assert(mt
->aux_buf
);
2424 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2425 const uint32_t level
= start_level
+ l
;
2426 if (!intel_miptree_level_has_hiz(mt
, level
))
2429 const uint32_t level_layers
=
2430 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2431 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2432 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2433 aux_usage
, fast_clear_supported
);
2439 unreachable("Invalid aux usage");
2444 intel_miptree_finish_write(struct brw_context
*brw
,
2445 struct intel_mipmap_tree
*mt
, uint32_t level
,
2446 uint32_t start_layer
, uint32_t num_layers
,
2447 enum isl_aux_usage aux_usage
)
2449 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2451 switch (mt
->aux_usage
) {
2452 case ISL_AUX_USAGE_NONE
:
2456 case ISL_AUX_USAGE_MCS
:
2457 assert(mt
->aux_buf
);
2458 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2459 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2464 case ISL_AUX_USAGE_CCS_D
:
2465 case ISL_AUX_USAGE_CCS_E
:
2469 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2470 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2475 case ISL_AUX_USAGE_HIZ
:
2476 if (!intel_miptree_level_has_hiz(mt
, level
))
2479 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2480 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2486 unreachable("Invavlid aux usage");
2491 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2492 uint32_t level
, uint32_t layer
)
2494 intel_miptree_check_level_layer(mt
, level
, layer
);
2496 if (_mesa_is_format_color_format(mt
->format
)) {
2497 assert(mt
->aux_buf
!= NULL
);
2498 assert(mt
->surf
.samples
== 1 ||
2499 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2500 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2501 unreachable("Cannot get aux state for stencil");
2503 assert(intel_miptree_level_has_hiz(mt
, level
));
2506 return mt
->aux_state
[level
][layer
];
2510 intel_miptree_set_aux_state(struct brw_context
*brw
,
2511 struct intel_mipmap_tree
*mt
, uint32_t level
,
2512 uint32_t start_layer
, uint32_t num_layers
,
2513 enum isl_aux_state aux_state
)
2515 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2517 if (_mesa_is_format_color_format(mt
->format
)) {
2518 assert(mt
->aux_buf
!= NULL
);
2519 assert(mt
->surf
.samples
== 1 ||
2520 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2521 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2522 unreachable("Cannot get aux state for stencil");
2524 assert(intel_miptree_level_has_hiz(mt
, level
));
2527 for (unsigned a
= 0; a
< num_layers
; a
++) {
2528 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2529 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2530 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2535 /* On Gen9 color buffers may be compressed by the hardware (lossless
2536 * compression). There are, however, format restrictions and care needs to be
2537 * taken that the sampler engine is capable for re-interpreting a buffer with
2538 * format different the buffer was originally written with.
2540 * For example, SRGB formats are not compressible and the sampler engine isn't
2541 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2542 * color buffer needs to be resolved so that the sampling surface can be
2543 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2547 can_texture_with_ccs(struct brw_context
*brw
,
2548 struct intel_mipmap_tree
*mt
,
2549 enum isl_format view_format
)
2551 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2554 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2556 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2557 isl_format_get_layout(view_format
)->name
,
2558 _mesa_get_format_name(mt
->format
));
2566 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2567 struct intel_mipmap_tree
*mt
,
2568 enum isl_format view_format
)
2570 switch (mt
->aux_usage
) {
2571 case ISL_AUX_USAGE_HIZ
:
2572 if (intel_miptree_sample_with_hiz(brw
, mt
))
2573 return ISL_AUX_USAGE_HIZ
;
2576 case ISL_AUX_USAGE_MCS
:
2577 return ISL_AUX_USAGE_MCS
;
2579 case ISL_AUX_USAGE_CCS_D
:
2580 case ISL_AUX_USAGE_CCS_E
:
2582 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2583 return ISL_AUX_USAGE_NONE
;
2586 /* If we don't have any unresolved color, report an aux usage of
2587 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2588 * aux surface and we can save some bandwidth.
2590 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2591 0, INTEL_REMAINING_LAYERS
))
2592 return ISL_AUX_USAGE_NONE
;
2594 if (can_texture_with_ccs(brw
, mt
, view_format
))
2595 return ISL_AUX_USAGE_CCS_E
;
2602 return ISL_AUX_USAGE_NONE
;
2606 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2608 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2609 * values so sRGB curve application was a no-op for all fast-clearable
2612 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2613 * values, the hardware interprets the floats, not as what would be
2614 * returned from the sampler (or written by the shader), but as being
2615 * between format conversion and sRGB curve application. This means that
2616 * we can switch between sRGB and UNORM without having to whack the clear
2619 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2623 intel_miptree_prepare_texture(struct brw_context
*brw
,
2624 struct intel_mipmap_tree
*mt
,
2625 enum isl_format view_format
,
2626 uint32_t start_level
, uint32_t num_levels
,
2627 uint32_t start_layer
, uint32_t num_layers
)
2629 enum isl_aux_usage aux_usage
=
2630 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2631 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2633 /* Clear color is specified as ints or floats and the conversion is done by
2634 * the sampler. If we have a texture view, we would have to perform the
2635 * clear color conversion manually. Just disable clear color.
2637 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2638 clear_supported
= false;
2640 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2641 start_layer
, num_layers
,
2642 aux_usage
, clear_supported
);
2646 intel_miptree_prepare_image(struct brw_context
*brw
,
2647 struct intel_mipmap_tree
*mt
)
2649 /* The data port doesn't understand any compression */
2650 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2651 0, INTEL_REMAINING_LAYERS
,
2652 ISL_AUX_USAGE_NONE
, false);
2656 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2657 struct intel_mipmap_tree
*mt
,
2658 enum isl_format render_format
,
2660 bool draw_aux_disabled
)
2662 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2664 if (draw_aux_disabled
)
2665 return ISL_AUX_USAGE_NONE
;
2667 switch (mt
->aux_usage
) {
2668 case ISL_AUX_USAGE_MCS
:
2669 assert(mt
->aux_buf
);
2670 return ISL_AUX_USAGE_MCS
;
2672 case ISL_AUX_USAGE_CCS_D
:
2673 case ISL_AUX_USAGE_CCS_E
:
2675 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2676 return ISL_AUX_USAGE_NONE
;
2679 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2680 * formats. However, there are issues with blending where it doesn't
2681 * properly apply the sRGB curve to the clear color when blending.
2683 if (devinfo
->gen
>= 9 && blend_enabled
&&
2684 isl_format_is_srgb(render_format
) &&
2685 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2686 return ISL_AUX_USAGE_NONE
;
2688 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2689 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2691 return ISL_AUX_USAGE_CCS_E
;
2693 /* Otherwise, we have to fall back to CCS_D */
2694 return ISL_AUX_USAGE_CCS_D
;
2697 return ISL_AUX_USAGE_NONE
;
2702 intel_miptree_prepare_render(struct brw_context
*brw
,
2703 struct intel_mipmap_tree
*mt
, uint32_t level
,
2704 uint32_t start_layer
, uint32_t layer_count
,
2705 enum isl_aux_usage aux_usage
)
2707 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2708 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2712 intel_miptree_finish_render(struct brw_context
*brw
,
2713 struct intel_mipmap_tree
*mt
, uint32_t level
,
2714 uint32_t start_layer
, uint32_t layer_count
,
2715 enum isl_aux_usage aux_usage
)
2717 assert(_mesa_is_format_color_format(mt
->format
));
2719 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2724 intel_miptree_prepare_depth(struct brw_context
*brw
,
2725 struct intel_mipmap_tree
*mt
, uint32_t level
,
2726 uint32_t start_layer
, uint32_t layer_count
)
2728 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2729 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2733 intel_miptree_finish_depth(struct brw_context
*brw
,
2734 struct intel_mipmap_tree
*mt
, uint32_t level
,
2735 uint32_t start_layer
, uint32_t layer_count
,
2738 if (depth_written
) {
2739 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2740 mt
->aux_buf
!= NULL
);
2745 intel_miptree_prepare_external(struct brw_context
*brw
,
2746 struct intel_mipmap_tree
*mt
)
2748 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2749 bool supports_fast_clear
= false;
2751 const struct isl_drm_modifier_info
*mod_info
=
2752 isl_drm_modifier_get_info(mt
->drm_modifier
);
2754 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2755 /* CCS_E is the only supported aux for external images and it's only
2756 * supported on very simple images.
2758 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2759 assert(_mesa_is_format_color_format(mt
->format
));
2760 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2761 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2762 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2763 assert(mt
->surf
.samples
== 1);
2764 assert(mt
->aux_buf
!= NULL
);
2766 aux_usage
= mod_info
->aux_usage
;
2767 supports_fast_clear
= mod_info
->supports_clear_color
;
2770 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2771 0, INTEL_REMAINING_LAYERS
,
2772 aux_usage
, supports_fast_clear
);
2776 intel_miptree_finish_external(struct brw_context
*brw
,
2777 struct intel_mipmap_tree
*mt
)
2782 /* We don't know the actual aux state of the aux surface. The previous
2783 * owner could have given it to us in a number of different states.
2784 * Because we don't know the aux state, we reset the aux state to the
2785 * least common denominator of possible valid states.
2787 enum isl_aux_state default_aux_state
=
2788 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2789 assert(mt
->last_level
== mt
->first_level
);
2790 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2795 * Make it possible to share the BO backing the given miptree with another
2796 * process or another miptree.
2798 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2799 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2800 * ensure that no MCS buffer gets allocated in the future.
2802 * HiZ is similarly unsafe with shared buffers.
2805 intel_miptree_make_shareable(struct brw_context
*brw
,
2806 struct intel_mipmap_tree
*mt
)
2808 /* MCS buffers are also used for multisample buffers, but we can't resolve
2809 * away a multisample MCS buffer because it's an integral part of how the
2810 * pixel data is stored. Fortunately this code path should never be
2811 * reached for multisample buffers.
2813 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2814 mt
->surf
.samples
== 1);
2816 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2817 0, INTEL_REMAINING_LAYERS
,
2818 ISL_AUX_USAGE_NONE
, false);
2821 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2824 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2825 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2826 mt
->level
[l
].has_hiz
= false;
2829 free(mt
->aux_state
);
2830 mt
->aux_state
= NULL
;
2831 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2834 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2835 mt
->supports_fast_clear
= false;
2840 * \brief Get pointer offset into stencil buffer.
2842 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2843 * must decode the tile's layout in software.
2846 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2848 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2850 * Even though the returned offset is always positive, the return type is
2852 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2853 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2856 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2858 uint32_t tile_size
= 4096;
2859 uint32_t tile_width
= 64;
2860 uint32_t tile_height
= 64;
2861 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2863 uint32_t tile_x
= x
/ tile_width
;
2864 uint32_t tile_y
= y
/ tile_height
;
2866 /* The byte's address relative to the tile's base addres. */
2867 uint32_t byte_x
= x
% tile_width
;
2868 uint32_t byte_y
= y
% tile_height
;
2870 uintptr_t u
= tile_y
* row_size
2871 + tile_x
* tile_size
2872 + 512 * (byte_x
/ 8)
2874 + 32 * ((byte_y
/ 4) % 2)
2875 + 16 * ((byte_x
/ 4) % 2)
2876 + 8 * ((byte_y
/ 2) % 2)
2877 + 4 * ((byte_x
/ 2) % 2)
2882 /* adjust for bit6 swizzling */
2883 if (((byte_x
/ 8) % 2) == 1) {
2884 if (((byte_y
/ 8) % 2) == 0) {
2896 intel_miptree_updownsample(struct brw_context
*brw
,
2897 struct intel_mipmap_tree
*src
,
2898 struct intel_mipmap_tree
*dst
)
2900 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2901 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2902 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2903 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2905 brw_blorp_blit_miptrees(brw
,
2906 src
, 0 /* level */, 0 /* layer */,
2907 src
->format
, SWIZZLE_XYZW
,
2908 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2911 GL_NEAREST
, false, false /*mirror x, y*/,
2914 if (src
->stencil_mt
) {
2915 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2916 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2917 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2918 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2920 brw_blorp_blit_miptrees(brw
,
2921 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2922 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2923 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2924 dst
->stencil_mt
->format
,
2927 GL_NEAREST
, false, false /*mirror x, y*/,
2928 false, false /* decode/encode srgb */);
2933 intel_update_r8stencil(struct brw_context
*brw
,
2934 struct intel_mipmap_tree
*mt
)
2936 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2938 assert(devinfo
->gen
>= 7);
2939 struct intel_mipmap_tree
*src
=
2940 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2941 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2944 assert(src
->surf
.size
> 0);
2946 if (!mt
->r8stencil_mt
) {
2947 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2948 mt
->r8stencil_mt
= make_surface(
2951 MESA_FORMAT_R_UINT8
,
2952 src
->first_level
, src
->last_level
,
2953 src
->surf
.logical_level0_px
.width
,
2954 src
->surf
.logical_level0_px
.height
,
2955 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2956 src
->surf
.logical_level0_px
.depth
:
2957 src
->surf
.logical_level0_px
.array_len
,
2960 ISL_SURF_USAGE_TEXTURE_BIT
,
2961 BO_ALLOC_BUSY
, 0, NULL
);
2962 assert(mt
->r8stencil_mt
);
2965 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2967 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2968 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2969 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2970 src
->surf
.phys_level0_sa
.array_len
;
2972 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2973 brw_blorp_copy_miptrees(brw
,
2977 minify(src
->surf
.logical_level0_px
.width
,
2979 minify(src
->surf
.logical_level0_px
.height
,
2984 brw_cache_flush_for_read(brw
, dst
->bo
);
2985 src
->r8stencil_needs_update
= false;
2989 intel_miptree_map_raw(struct brw_context
*brw
,
2990 struct intel_mipmap_tree
*mt
,
2993 struct brw_bo
*bo
= mt
->bo
;
2995 if (brw_batch_references(&brw
->batch
, bo
))
2996 intel_batchbuffer_flush(brw
);
2998 return brw_bo_map(brw
, bo
, mode
);
3002 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3004 brw_bo_unmap(mt
->bo
);
3008 intel_miptree_unmap_gtt(struct brw_context
*brw
,
3009 struct intel_mipmap_tree
*mt
,
3010 struct intel_miptree_map
*map
,
3011 unsigned int level
, unsigned int slice
)
3013 intel_miptree_unmap_raw(mt
);
3017 intel_miptree_map_gtt(struct brw_context
*brw
,
3018 struct intel_mipmap_tree
*mt
,
3019 struct intel_miptree_map
*map
,
3020 unsigned int level
, unsigned int slice
)
3022 unsigned int bw
, bh
;
3024 unsigned int image_x
, image_y
;
3025 intptr_t x
= map
->x
;
3026 intptr_t y
= map
->y
;
3028 /* For compressed formats, the stride is the number of bytes per
3029 * row of blocks. intel_miptree_get_image_offset() already does
3032 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3033 assert(y
% bh
== 0);
3034 assert(x
% bw
== 0);
3038 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3045 /* Note that in the case of cube maps, the caller must have passed the
3046 * slice number referencing the face.
3048 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3052 map
->stride
= mt
->surf
.row_pitch
;
3053 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3056 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3057 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3058 map
->x
, map
->y
, map
->w
, map
->h
,
3059 mt
, _mesa_get_format_name(mt
->format
),
3060 x
, y
, map
->ptr
, map
->stride
);
3062 map
->unmap
= intel_miptree_unmap_gtt
;
3066 intel_miptree_unmap_blit(struct brw_context
*brw
,
3067 struct intel_mipmap_tree
*mt
,
3068 struct intel_miptree_map
*map
,
3072 struct gl_context
*ctx
= &brw
->ctx
;
3074 intel_miptree_unmap_raw(map
->linear_mt
);
3076 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3077 bool ok
= intel_miptree_copy(brw
,
3078 map
->linear_mt
, 0, 0, 0, 0,
3079 mt
, level
, slice
, map
->x
, map
->y
,
3081 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3084 intel_miptree_release(&map
->linear_mt
);
3088 intel_miptree_map_blit(struct brw_context
*brw
,
3089 struct intel_mipmap_tree
*mt
,
3090 struct intel_miptree_map
*map
,
3091 unsigned int level
, unsigned int slice
)
3093 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3094 /* first_level */ 0,
3098 MIPTREE_CREATE_LINEAR
);
3100 if (!map
->linear_mt
) {
3101 fprintf(stderr
, "Failed to allocate blit temporary\n");
3104 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3106 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3107 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3108 * invalidate is set, since we'll be writing the whole rectangle from our
3109 * temporary buffer back out.
3111 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3112 if (!intel_miptree_copy(brw
,
3113 mt
, level
, slice
, map
->x
, map
->y
,
3114 map
->linear_mt
, 0, 0, 0, 0,
3116 fprintf(stderr
, "Failed to blit\n");
3121 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3123 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3124 map
->x
, map
->y
, map
->w
, map
->h
,
3125 mt
, _mesa_get_format_name(mt
->format
),
3126 level
, slice
, map
->ptr
, map
->stride
);
3128 map
->unmap
= intel_miptree_unmap_blit
;
3132 intel_miptree_release(&map
->linear_mt
);
3138 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3140 #if defined(USE_SSE41)
3142 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3143 struct intel_mipmap_tree
*mt
,
3144 struct intel_miptree_map
*map
,
3148 _mesa_align_free(map
->buffer
);
3154 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3155 struct intel_mipmap_tree
*mt
,
3156 struct intel_miptree_map
*map
,
3157 unsigned int level
, unsigned int slice
)
3159 assert(map
->mode
& GL_MAP_READ_BIT
);
3160 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3162 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3163 map
->x
, map
->y
, map
->w
, map
->h
,
3164 mt
, _mesa_get_format_name(mt
->format
),
3165 level
, slice
, map
->ptr
, map
->stride
);
3167 /* Map the original image */
3170 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3174 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3180 src
+= image_y
* mt
->surf
.row_pitch
;
3181 src
+= image_x
* mt
->cpp
;
3183 /* Due to the pixel offsets for the particular image being mapped, our
3184 * src pointer may not be 16-byte aligned. However, if the pitch is
3185 * divisible by 16, then the amount by which it's misaligned will remain
3186 * consistent from row to row.
3188 assert((mt
->surf
.row_pitch
% 16) == 0);
3189 const int misalignment
= ((uintptr_t) src
) & 15;
3191 /* Create an untiled temporary buffer for the mapping. */
3192 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3194 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3196 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3197 /* Offset the destination so it has the same misalignment as src. */
3198 map
->ptr
= map
->buffer
+ misalignment
;
3200 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3202 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3203 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3204 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3206 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3209 intel_miptree_unmap_raw(mt
);
3211 map
->unmap
= intel_miptree_unmap_movntdqa
;
3216 intel_miptree_unmap_s8(struct brw_context
*brw
,
3217 struct intel_mipmap_tree
*mt
,
3218 struct intel_miptree_map
*map
,
3222 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3223 unsigned int image_x
, image_y
;
3224 uint8_t *untiled_s8_map
= map
->ptr
;
3225 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3227 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3229 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3230 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3231 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3232 image_x
+ x
+ map
->x
,
3233 image_y
+ y
+ map
->y
,
3234 brw
->has_swizzling
);
3235 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3239 intel_miptree_unmap_raw(mt
);
3246 intel_miptree_map_s8(struct brw_context
*brw
,
3247 struct intel_mipmap_tree
*mt
,
3248 struct intel_miptree_map
*map
,
3249 unsigned int level
, unsigned int slice
)
3251 map
->stride
= map
->w
;
3252 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3256 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3257 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3258 * invalidate is set, since we'll be writing the whole rectangle from our
3259 * temporary buffer back out.
3261 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3262 uint8_t *untiled_s8_map
= map
->ptr
;
3263 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3264 unsigned int image_x
, image_y
;
3266 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3268 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3269 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3270 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3271 x
+ image_x
+ map
->x
,
3272 y
+ image_y
+ map
->y
,
3273 brw
->has_swizzling
);
3274 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3278 intel_miptree_unmap_raw(mt
);
3280 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3281 map
->x
, map
->y
, map
->w
, map
->h
,
3282 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3284 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3285 map
->x
, map
->y
, map
->w
, map
->h
,
3286 mt
, map
->ptr
, map
->stride
);
3289 map
->unmap
= intel_miptree_unmap_s8
;
3293 intel_miptree_unmap_etc(struct brw_context
*brw
,
3294 struct intel_mipmap_tree
*mt
,
3295 struct intel_miptree_map
*map
,
3301 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3306 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3307 + image_y
* mt
->surf
.row_pitch
3308 + image_x
* mt
->cpp
;
3310 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3311 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3312 map
->ptr
, map
->stride
,
3315 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3316 map
->ptr
, map
->stride
,
3317 map
->w
, map
->h
, mt
->etc_format
);
3319 intel_miptree_unmap_raw(mt
);
3324 intel_miptree_map_etc(struct brw_context
*brw
,
3325 struct intel_mipmap_tree
*mt
,
3326 struct intel_miptree_map
*map
,
3330 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3331 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3332 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3335 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3336 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3338 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3339 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3340 map
->w
, map
->h
, 1));
3341 map
->ptr
= map
->buffer
;
3342 map
->unmap
= intel_miptree_unmap_etc
;
3346 * Mapping functions for packed depth/stencil miptrees backed by real separate
3347 * miptrees for depth and stencil.
3349 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3350 * separate from the depth buffer. Yet at the GL API level, we have to expose
3351 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3352 * be able to map that memory for texture storage and glReadPixels-type
3353 * operations. We give Mesa core that access by mallocing a temporary and
3354 * copying the data between the actual backing store and the temporary.
3357 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3358 struct intel_mipmap_tree
*mt
,
3359 struct intel_miptree_map
*map
,
3363 struct intel_mipmap_tree
*z_mt
= mt
;
3364 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3365 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3367 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3368 uint32_t *packed_map
= map
->ptr
;
3369 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3370 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3371 unsigned int s_image_x
, s_image_y
;
3372 unsigned int z_image_x
, z_image_y
;
3374 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3375 &s_image_x
, &s_image_y
);
3376 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3377 &z_image_x
, &z_image_y
);
3379 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3380 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3381 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3382 x
+ s_image_x
+ map
->x
,
3383 y
+ s_image_y
+ map
->y
,
3384 brw
->has_swizzling
);
3385 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3386 (z_mt
->surf
.row_pitch
/ 4) +
3387 (x
+ z_image_x
+ map
->x
));
3389 if (map_z32f_x24s8
) {
3390 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3391 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3393 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3394 s_map
[s_offset
] = packed
>> 24;
3395 z_map
[z_offset
] = packed
;
3400 intel_miptree_unmap_raw(s_mt
);
3401 intel_miptree_unmap_raw(z_mt
);
3403 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3405 map
->x
, map
->y
, map
->w
, map
->h
,
3406 z_mt
, _mesa_get_format_name(z_mt
->format
),
3407 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3408 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3409 map
->ptr
, map
->stride
);
3416 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3417 struct intel_mipmap_tree
*mt
,
3418 struct intel_miptree_map
*map
,
3419 unsigned int level
, unsigned int slice
)
3421 struct intel_mipmap_tree
*z_mt
= mt
;
3422 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3423 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3424 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3426 map
->stride
= map
->w
* packed_bpp
;
3427 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3431 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3432 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3433 * invalidate is set, since we'll be writing the whole rectangle from our
3434 * temporary buffer back out.
3436 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3437 uint32_t *packed_map
= map
->ptr
;
3438 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3439 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3440 unsigned int s_image_x
, s_image_y
;
3441 unsigned int z_image_x
, z_image_y
;
3443 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3444 &s_image_x
, &s_image_y
);
3445 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3446 &z_image_x
, &z_image_y
);
3448 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3449 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3450 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3451 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3454 brw
->has_swizzling
);
3455 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3456 (z_mt
->surf
.row_pitch
/ 4) +
3457 (map_x
+ z_image_x
));
3458 uint8_t s
= s_map
[s_offset
];
3459 uint32_t z
= z_map
[z_offset
];
3461 if (map_z32f_x24s8
) {
3462 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3463 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3465 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3470 intel_miptree_unmap_raw(s_mt
);
3471 intel_miptree_unmap_raw(z_mt
);
3473 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3475 map
->x
, map
->y
, map
->w
, map
->h
,
3476 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3477 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3478 map
->ptr
, map
->stride
);
3480 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3481 map
->x
, map
->y
, map
->w
, map
->h
,
3482 mt
, map
->ptr
, map
->stride
);
3485 map
->unmap
= intel_miptree_unmap_depthstencil
;
3489 * Create and attach a map to the miptree at (level, slice). Return the
3492 static struct intel_miptree_map
*
3493 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3502 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3507 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3508 mt
->level
[level
].slice
[slice
].map
= map
;
3520 * Release the map at (level, slice).
3523 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3527 struct intel_miptree_map
**map
;
3529 map
= &mt
->level
[level
].slice
[slice
].map
;
3535 can_blit_slice(struct intel_mipmap_tree
*mt
,
3536 unsigned int level
, unsigned int slice
)
3538 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3539 if (mt
->surf
.row_pitch
>= 32768)
3546 use_intel_mipree_map_blit(struct brw_context
*brw
,
3547 struct intel_mipmap_tree
*mt
,
3552 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3554 if (devinfo
->has_llc
&&
3555 /* It's probably not worth swapping to the blit ring because of
3556 * all the overhead involved.
3558 !(mode
& GL_MAP_WRITE_BIT
) &&
3560 (mt
->surf
.tiling
== ISL_TILING_X
||
3561 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3562 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3563 /* Fast copy blit on skl+ supports all tiling formats. */
3564 devinfo
->gen
>= 9) &&
3565 can_blit_slice(mt
, level
, slice
))
3568 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3569 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3570 assert(can_blit_slice(mt
, level
, slice
));
3578 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3579 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3580 * arithmetic overflow.
3582 * If you call this function and use \a out_stride, then you're doing pointer
3583 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3584 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3585 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3586 * which usually have type uint32_t or GLuint.
3589 intel_miptree_map(struct brw_context
*brw
,
3590 struct intel_mipmap_tree
*mt
,
3599 ptrdiff_t *out_stride
)
3601 struct intel_miptree_map
*map
;
3603 assert(mt
->surf
.samples
== 1);
3605 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3612 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3613 map
->mode
& GL_MAP_WRITE_BIT
);
3615 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3616 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3617 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3618 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3619 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3620 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3621 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3622 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3623 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3624 #if defined(USE_SSE41)
3625 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3626 !mt
->compressed
&& cpu_has_sse4_1
&&
3627 (mt
->surf
.row_pitch
% 16 == 0)) {
3628 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3631 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3634 *out_ptr
= map
->ptr
;
3635 *out_stride
= map
->stride
;
3637 if (map
->ptr
== NULL
)
3638 intel_miptree_release_map(mt
, level
, slice
);
3642 intel_miptree_unmap(struct brw_context
*brw
,
3643 struct intel_mipmap_tree
*mt
,
3647 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3649 assert(mt
->surf
.samples
== 1);
3654 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3655 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3658 map
->unmap(brw
, mt
, map
, level
, slice
);
3660 intel_miptree_release_map(mt
, level
, slice
);
3664 get_isl_surf_dim(GLenum target
)
3668 case GL_TEXTURE_1D_ARRAY
:
3669 return ISL_SURF_DIM_1D
;
3672 case GL_TEXTURE_2D_ARRAY
:
3673 case GL_TEXTURE_RECTANGLE
:
3674 case GL_TEXTURE_CUBE_MAP
:
3675 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3676 case GL_TEXTURE_2D_MULTISAMPLE
:
3677 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3678 case GL_TEXTURE_EXTERNAL_OES
:
3679 return ISL_SURF_DIM_2D
;
3682 return ISL_SURF_DIM_3D
;
3685 unreachable("Invalid texture target");
3689 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3690 enum isl_tiling tiling
, GLenum target
)
3694 case GL_TEXTURE_1D_ARRAY
:
3695 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3696 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3699 case GL_TEXTURE_2D_ARRAY
:
3700 case GL_TEXTURE_RECTANGLE
:
3701 case GL_TEXTURE_2D_MULTISAMPLE
:
3702 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3703 case GL_TEXTURE_EXTERNAL_OES
:
3704 return ISL_DIM_LAYOUT_GEN4_2D
;
3706 case GL_TEXTURE_CUBE_MAP
:
3707 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3708 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3709 ISL_DIM_LAYOUT_GEN4_2D
);
3712 return (devinfo
->gen
>= 9 ?
3713 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3716 unreachable("Invalid texture target");
3720 intel_miptree_set_clear_color(struct brw_context
*brw
,
3721 struct intel_mipmap_tree
*mt
,
3722 union isl_color_value clear_color
)
3724 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3725 mt
->fast_clear_color
= clear_color
;
3726 if (mt
->aux_buf
->clear_color_bo
) {
3727 /* We can't update the clear color while the hardware is still using
3728 * the previous one for a resolve or sampling from it. Make sure that
3729 * there are no pending commands at this point.
3731 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3732 for (int i
= 0; i
< 4; i
++) {
3733 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3734 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3735 mt
->fast_clear_color
.u32
[i
]);
3737 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3739 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3745 union isl_color_value
3746 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3747 const struct intel_mipmap_tree
*mt
,
3748 enum isl_format view_format
, bool sampling
,
3749 struct brw_bo
**clear_color_bo
,
3750 uint32_t *clear_color_offset
)
3752 assert(mt
->aux_buf
);
3754 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3755 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3756 * we switch to using the inline clear color and do the sRGB color
3757 * conversion process defined in the OpenGL spec. The red, green, and
3758 * blue channels take part in gamma correction, while the alpha channel
3761 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3762 for (unsigned i
= 0; i
< 3; i
++) {
3763 srgb_decoded_value
.f32
[i
] =
3764 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3766 *clear_color_bo
= 0;
3767 *clear_color_offset
= 0;
3768 return srgb_decoded_value
;
3770 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3771 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3772 return mt
->fast_clear_color
;