src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "blorp/blorp.h"
  52 #include "brw_bufmgr.h"
  53 #include "brw_context.h"
  54 #include <GL/internal/dri_interface.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 struct brw_context;
  61 struct intel_renderbuffer;
  62
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91
  92    void (*unmap)(struct brw_context *brw,
  93                  struct intel_mipmap_tree *mt,
  94                  struct intel_miptree_map *map,
  95                  unsigned int level,
  96                  unsigned int slice);
  97 };
  98
  99 /**
 100  * Describes the location of each texture image within a miptree.
 101  */
 102 struct intel_mipmap_level
 103 {
 104    /** Offset to this miptree level, used in computing x_offset. */
 105    GLuint level_x;
 106    /** Offset to this miptree level, used in computing y_offset. */
 107    GLuint level_y;
 108
 109    /**
 110     * \brief Is HiZ enabled for this level?
 111     *
 112     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 113     * allocated and (2) the HiZ memory for the slices in this level reside at
 114     * \c mt->hiz_mt->level[l].
 115     */
 116    bool has_hiz;
 117
 118    /**
 119     * \brief List of 2D images in this mipmap level.
 120     *
 121     * This may be a list of cube faces, array slices in 2D array texture, or
 122     * layers in a 3D texture. The list's length is \c depth.
 123     */
 124    struct intel_mipmap_slice {
 125       /**
 126        * Mapping information. Persistent for the duration of
 127        * intel_miptree_map/unmap on this slice.
 128        */
 129       struct intel_miptree_map *map;
 130    } *slice;
 131 };
 132
 133 /**
 134  * Miptree aux buffer. These buffers are associated with a miptree, but the
 135  * format is managed by the hardware.
 136  *
 137  * For Gen7+, we always give the hardware the start of the buffer, and let it
 138  * handle all accesses to the buffer. Therefore we don't need the full miptree
 139  * layout structure for this buffer.
 140  */
 141 struct intel_miptree_aux_buffer
 142 {
 143    struct isl_surf surf;
 144
 145    /**
 146     * Buffer object containing the pixel data.
 147     *
 148     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 149     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 150     */
 151    struct brw_bo *bo;
 152
 153    /**
 154     * Offset into bo where the surface starts.
 155     *
 156     * @see intel_mipmap_aux_buffer::bo
 157     *
 158     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 159     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 160     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 161     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 162     */
 163    uint32_t offset;
 164
 165    /**
 166     * Buffer object containing the indirect clear color.
 167     *
 168     * @see create_ccs_buf_for_image
 169     * @see RENDER_SURFACE_STATE.ClearValueAddress
 170     */
 171    struct brw_bo *clear_color_bo;
 172
 173    /**
 174     * Offset into bo where the clear color can be found.
 175     *
 176     * @see create_ccs_buf_for_image
 177     * @see RENDER_SURFACE_STATE.ClearValueAddress
 178     */
 179    uint32_t clear_color_offset;
 180 };
 181
 182 struct intel_mipmap_tree
 183 {
 184    struct isl_surf surf;
 185
 186    /**
 187     * Buffer object containing the surface.
 188     *
 189     * @see intel_mipmap_tree::offset
 190     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 191     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 192     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 193     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 194     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 195     */
 196    struct brw_bo *bo;
 197
 198    /**
 199     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 200     *
 201     * @see RENDER_SURFACE_STATE.SurfaceType
 202     * @see RENDER_SURFACE_STATE.SurfaceArray
 203     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 204     */
 205    GLenum target;
 206
 207    /**
 208     * Generally, this is just the same as the gl_texture_image->TexFormat or
 209     * gl_renderbuffer->Format.
 210     *
 211     * However, for textures and renderbuffers with packed depth/stencil formats
 212     * on hardware where we want or need to use separate stencil, there will be
 213     * two miptrees for storing the data.  If the depthstencil texture or rb is
 214     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 215     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 216     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 217     *
 218     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 219     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 220     *
 221     * @see RENDER_SURFACE_STATE.SurfaceFormat
 222     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 223     */
 224    mesa_format format;
 225
 226    /**
 227     * This variable stores the value of ETC compressed texture format
 228     *
 229     * @see RENDER_SURFACE_STATE.SurfaceFormat
 230     */
 231    mesa_format etc_format;
 232
 233    GLuint first_level;
 234    GLuint last_level;
 235
 236    /** Bytes per pixel (or bytes per block if compressed) */
 237    GLuint cpp;
 238
 239    bool compressed;
 240
 241    /* Includes image offset tables: */
 242    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 243
 244    /**
 245     * Offset into bo where the surface starts.
 246     *
 247     * @see intel_mipmap_tree::bo
 248     *
 249     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 250     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 251     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 252     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 253     */
 254    uint32_t offset;
 255
 256    /**
 257     * \brief The type of auxiliary compression used by this miptree.
 258     *
 259     * This describes the type of auxiliary compression that is intended to be
 260     * used by this miptree.  An aux usage of ISL_AUX_USAGE_NONE means that
 261     * auxiliary compression is permanently disabled.  An aux usage other than
 262     * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
 263     * been allocated nor does it imply that auxiliary compression will always
 264     * be enabled for this surface.  For instance, with CCS_D, we may allocate
 265     * the CCS on-the-fly and it may not be used for texturing if the miptree
 266     * is fully resolved.
 267     */
 268    enum isl_aux_usage aux_usage;
 269
 270    /**
 271     * \brief Whether or not this miptree supports fast clears.
 272     */
 273    bool supports_fast_clear;
 274
 275    /**
 276     * \brief Maps miptree slices to their current aux state
 277     *
 278     * This two-dimensional array is indexed as [level][layer] and stores an
 279     * aux state for each slice.
 280     */
 281    enum isl_aux_state **aux_state;
 282
 283    /**
 284     * \brief Stencil miptree for depthstencil textures.
 285     *
 286     * This miptree is used for depthstencil textures and renderbuffers that
 287     * require separate stencil.  It always has the true copy of the stencil
 288     * bits, regardless of mt->format.
 289     *
 290     * \see 3DSTATE_STENCIL_BUFFER
 291     * \see intel_miptree_map_depthstencil()
 292     * \see intel_miptree_unmap_depthstencil()
 293     */
 294    struct intel_mipmap_tree *stencil_mt;
 295
 296    /**
 297     * \brief Stencil texturing miptree for sampling from a stencil texture
 298     *
 299     * Some hardware doesn't support sampling from the stencil texture as
 300     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 301     * blit the texture into a new texture that can be sampled.
 302     *
 303     * \see intel_update_r8stencil()
 304     */
 305    struct intel_mipmap_tree *r8stencil_mt;
 306    bool r8stencil_needs_update;
 307
 308    /**
 309     * \brief CCS, MCS, or HiZ auxiliary buffer.
 310     *
 311     * NULL if no auxiliary buffer is in use for this surface.
 312     *
 313     * For single-sampled color miptrees:
 314     *    This buffer contains the Color Control Surface, which stores the
 315     *    necessary information to implement lossless color compression (CCS_E)
 316     *    and "fast color clear" (CCS_D) behaviour.
 317     *
 318     * For multi-sampled color miptrees:
 319     *    This buffer contains the Multisample Control Surface, which stores the
 320     *    necessary information to implement compressed MSAA
 321     *    (INTEL_MSAA_FORMAT_CMS).
 322     *
 323     * For depth miptrees:
 324     *    This buffer contains the Hierarchical Depth Buffer, which stores the
 325     *    necessary information to implement lossless depth compression and fast
 326     *    depth clear behavior.
 327     *
 328     *    To determine if HiZ is enabled, do not check this pointer. Instead,
 329     *    use intel_miptree_level_has_hiz().
 330     */
 331    struct intel_miptree_aux_buffer *aux_buf;
 332
 333    /**
 334     * Planes 1 and 2 in case this is a planar surface.
 335     */
 336    struct intel_mipmap_tree *plane[2];
 337
 338    /**
 339     * Fast clear color for this surface.  For depth surfaces, the clear value
 340     * is stored as a float32 in the red component.
 341     */
 342    union isl_color_value fast_clear_color;
 343
 344    /**
 345     * For external surfaces, this is DRM format modifier that was used to
 346     * create or import the surface.  For internal surfaces, this will always
 347     * be DRM_FORMAT_MOD_INVALID.
 348     */
 349    uint64_t drm_modifier;
 350
 351    /* These are also refcounted:
 352     */
 353    GLuint refcount;
 354 };
 355
 356 bool
 357 intel_miptree_alloc_ccs(struct brw_context *brw,
 358                         struct intel_mipmap_tree *mt);
 359
 360 enum intel_miptree_create_flags {
 361    /** No miptree create flags */
 362    MIPTREE_CREATE_DEFAULT  = 0,
 363
 364    /** Miptree creation should try to allocate a currently busy BO
 365     *
 366     * This may be advantageous if we know the next thing to touch the BO will
 367     * be the GPU because the BO will likely already be in the GTT and maybe
 368     * even in some caches.  If there is a chance that the next thing to touch
 369     * the miptree BO will be the CPU, this flag should not be set.
 370     */
 371    MIPTREE_CREATE_BUSY     = 1 << 0,
 372
 373    /** Create a linear (not tiled) miptree */
 374    MIPTREE_CREATE_LINEAR   = 1 << 1,
 375
 376    /** Create the miptree with auxiliary compression disabled
 377     *
 378     * This does not prevent the caller of intel_miptree_create from coming
 379     * along later and turning auxiliary compression back on but it does mean
 380     * that the miptree will be created with mt->aux_usage == NONE.
 381     */
 382    MIPTREE_CREATE_NO_AUX   = 1 << 2,
 383 };
 384
 385 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 386                                                GLenum target,
 387                                                mesa_format format,
 388                                                GLuint first_level,
 389                                                GLuint last_level,
 390                                                GLuint width0,
 391                                                GLuint height0,
 392                                                GLuint depth0,
 393                                                GLuint num_samples,
 394                                                enum intel_miptree_create_flags flags);
 395
 396 struct intel_mipmap_tree *
 397 intel_miptree_create_for_bo(struct brw_context *brw,
 398                             struct brw_bo *bo,
 399                             mesa_format format,
 400                             uint32_t offset,
 401                             uint32_t width,
 402                             uint32_t height,
 403                             uint32_t depth,
 404                             int pitch,
 405                             enum isl_tiling tiling,
 406                             enum intel_miptree_create_flags flags);
 407
 408 struct intel_mipmap_tree *
 409 intel_miptree_create_for_dri_image(struct brw_context *brw,
 410                                    __DRIimage *image,
 411                                    GLenum target,
 412                                    mesa_format format,
 413                                    bool is_winsys_image);
 414
 415 bool
 416 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 417                                          struct intel_renderbuffer *irb,
 418                                          struct intel_mipmap_tree *singlesample_mt,
 419                                          uint32_t width, uint32_t height,
 420                                          uint32_t pitch);
 421
 422 /**
 423  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 424  * The miptree has the following properties:
 425  *     - The target is GL_TEXTURE_2D.
 426  *     - There are no levels other than the base level 0.
 427  *     - Depth is 1.
 428  */
 429 struct intel_mipmap_tree*
 430 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 431                                       mesa_format format,
 432                                       uint32_t width,
 433                                       uint32_t height,
 434                                       uint32_t num_samples);
 435
 436 mesa_format
 437 intel_depth_format_for_depthstencil_format(mesa_format format);
 438
 439 mesa_format
 440 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 441
 442 unsigned
 443 brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
 444
 445 /** \brief Assert that the level and layer are valid for the miptree. */
 446 void
 447 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 448                                 uint32_t level,
 449                                 uint32_t layer);
 450
 451 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 452                              struct intel_mipmap_tree *src);
 453
 454 void intel_miptree_release(struct intel_mipmap_tree **mt);
 455
 456 /* Check if an image fits an existing mipmap tree layout
 457  */
 458 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 459                                     struct gl_texture_image *image);
 460
 461 void
 462 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 463                                GLuint level, GLuint slice,
 464                                GLuint *x, GLuint *y);
 465
 466 enum isl_surf_dim
 467 get_isl_surf_dim(GLenum target);
 468
 469 enum isl_dim_layout
 470 get_isl_dim_layout(const struct gen_device_info *devinfo,
 471                    enum isl_tiling tiling, GLenum target);
 472
 473 void
 474 intel_get_image_dims(struct gl_texture_image *image,
 475                      int *width, int *height, int *depth);
 476
 477 void
 478 intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
 479                      uint32_t *mask_x, uint32_t *mask_y);
 480
 481 void
 482 intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
 483                     uint32_t *tile_w, uint32_t *tile_h);
 484
 485 uint32_t
 486 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 487                                GLuint level, GLuint slice,
 488                                uint32_t *tile_x,
 489                                uint32_t *tile_y);
 490 uint32_t
 491 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 492                                  uint32_t x, uint32_t y);
 493
 494 void
 495 intel_miptree_copy_slice(struct brw_context *brw,
 496                          struct intel_mipmap_tree *src_mt,
 497                          unsigned src_level, unsigned src_layer,
 498                          struct intel_mipmap_tree *dst_mt,
 499                          unsigned dst_level, unsigned dst_layer);
 500
 501 void
 502 intel_miptree_copy_teximage(struct brw_context *brw,
 503                             struct intel_texture_image *intelImage,
 504                             struct intel_mipmap_tree *dst_mt);
 505
 506 /**
 507  * \name Miptree HiZ functions
 508  * \{
 509  *
 510  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 511  * functions on a miptree without HiZ. In that case, each function is a no-op.
 512  */
 513
 514 /**
 515  * \brief Allocate the miptree's embedded HiZ miptree.
 516  * \see intel_mipmap_tree:hiz_mt
 517  * \return false if allocation failed
 518  */
 519 bool
 520 intel_miptree_alloc_hiz(struct brw_context *brw,
 521                         struct intel_mipmap_tree *mt);
 522
 523 bool
 524 intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
 525
 526 /**\}*/
 527
 528 bool
 529 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 530                                    unsigned start_level, unsigned num_levels,
 531                                    unsigned start_layer, unsigned num_layers);
 532
 533
 534 #define INTEL_REMAINING_LAYERS UINT32_MAX
 535 #define INTEL_REMAINING_LEVELS UINT32_MAX
 536
 537 /** Prepare a miptree for access
 538  *
 539  * This function should be called prior to any access to miptree in order to
 540  * perform any needed resolves.
 541  *
 542  * \param[in]  start_level    The first mip level to be accessed
 543  *
 544  * \param[in]  num_levels     The number of miplevels to be accessed or
 545  *                            INTEL_REMAINING_LEVELS to indicate every level
 546  *                            above start_level will be accessed
 547  *
 548  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 549  *
 550  * \param[in]  num_layers     The number of array slices or 3D layers be
 551  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 552  *                            every layer above start_layer will be accessed
 553  *
 554  * \param[in]  aux_supported  Whether or not the access will support the
 555  *                            miptree's auxiliary compression format;  this
 556  *                            must be false for uncompressed miptrees
 557  *
 558  * \param[in]  fast_clear_supported Whether or not the access will support
 559  *                                  fast clears in the miptree's auxiliary
 560  *                                  compression format
 561  */
 562 void
 563 intel_miptree_prepare_access(struct brw_context *brw,
 564                              struct intel_mipmap_tree *mt,
 565                              uint32_t start_level, uint32_t num_levels,
 566                              uint32_t start_layer, uint32_t num_layers,
 567                              enum isl_aux_usage aux_usage,
 568                              bool fast_clear_supported);
 569
 570 /** Complete a write operation
 571  *
 572  * This function should be called after any operation writes to a miptree.
 573  * This will update the miptree's compression state so that future resolves
 574  * happen correctly.  Technically, this function can be called before the
 575  * write occurs but the caller must ensure that they don't interlace
 576  * intel_miptree_prepare_access and intel_miptree_finish_write calls to
 577  * overlapping layer/level ranges.
 578  *
 579  * \param[in]  level             The mip level that was written
 580  *
 581  * \param[in]  start_layer       The first array slice or 3D layer written
 582  *
 583  * \param[in]  num_layers        The number of array slices or 3D layers
 584  *                               written or INTEL_REMAINING_LAYERS to indicate
 585  *                               every layer above start_layer was written
 586  *
 587  * \param[in]  written_with_aux  Whether or not the write was done with
 588  *                               auxiliary compression enabled
 589  */
 590 void
 591 intel_miptree_finish_write(struct brw_context *brw,
 592                            struct intel_mipmap_tree *mt, uint32_t level,
 593                            uint32_t start_layer, uint32_t num_layers,
 594                            enum isl_aux_usage aux_usage);
 595
 596 /** Get the auxiliary compression state of a miptree slice */
 597 enum isl_aux_state
 598 intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
 599                             uint32_t level, uint32_t layer);
 600
 601 /** Set the auxiliary compression state of a miptree slice range
 602  *
 603  * This function directly sets the auxiliary compression state of a slice
 604  * range of a miptree.  It only modifies data structures and does not do any
 605  * resolves.  This should only be called by code which directly performs
 606  * compression operations such as fast clears and resolves.  Most code should
 607  * use intel_miptree_prepare_access or intel_miptree_finish_write.
 608  */
 609 void
 610 intel_miptree_set_aux_state(struct brw_context *brw,
 611                             struct intel_mipmap_tree *mt, uint32_t level,
 612                             uint32_t start_layer, uint32_t num_layers,
 613                             enum isl_aux_state aux_state);
 614
 615 /**
 616  * Prepare a miptree for raw access
 617  *
 618  * This helper prepares the miptree for access that knows nothing about any
 619  * sort of compression whatsoever.  This is useful when mapping the surface or
 620  * using it with the blitter.
 621  */
 622 static inline void
 623 intel_miptree_access_raw(struct brw_context *brw,
 624                          struct intel_mipmap_tree *mt,
 625                          uint32_t level, uint32_t layer,
 626                          bool write)
 627 {
 628    intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
 629    if (write)
 630       intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 631 }
 632
 633 enum isl_aux_usage
 634 intel_miptree_texture_aux_usage(struct brw_context *brw,
 635                                 struct intel_mipmap_tree *mt,
 636                                 enum isl_format view_format);
 637 void
 638 intel_miptree_prepare_texture(struct brw_context *brw,
 639                               struct intel_mipmap_tree *mt,
 640                               enum isl_format view_format,
 641                               uint32_t start_level, uint32_t num_levels,
 642                               uint32_t start_layer, uint32_t num_layers);
 643 void
 644 intel_miptree_prepare_image(struct brw_context *brw,
 645                             struct intel_mipmap_tree *mt);
 646
 647 enum isl_aux_usage
 648 intel_miptree_render_aux_usage(struct brw_context *brw,
 649                                struct intel_mipmap_tree *mt,
 650                                enum isl_format render_format,
 651                                bool blend_enabled,
 652                                bool draw_aux_disabled);
 653 void
 654 intel_miptree_prepare_render(struct brw_context *brw,
 655                              struct intel_mipmap_tree *mt, uint32_t level,
 656                              uint32_t start_layer, uint32_t layer_count,
 657                              enum isl_aux_usage aux_usage);
 658 void
 659 intel_miptree_finish_render(struct brw_context *brw,
 660                             struct intel_mipmap_tree *mt, uint32_t level,
 661                             uint32_t start_layer, uint32_t layer_count,
 662                             enum isl_aux_usage aux_usage);
 663 void
 664 intel_miptree_prepare_depth(struct brw_context *brw,
 665                             struct intel_mipmap_tree *mt, uint32_t level,
 666                             uint32_t start_layer, uint32_t layer_count);
 667 void
 668 intel_miptree_finish_depth(struct brw_context *brw,
 669                            struct intel_mipmap_tree *mt, uint32_t level,
 670                            uint32_t start_layer, uint32_t layer_count,
 671                            bool depth_written);
 672 void
 673 intel_miptree_prepare_external(struct brw_context *brw,
 674                                struct intel_mipmap_tree *mt);
 675 void
 676 intel_miptree_finish_external(struct brw_context *brw,
 677                               struct intel_mipmap_tree *mt);
 678
 679 void
 680 intel_miptree_make_shareable(struct brw_context *brw,
 681                              struct intel_mipmap_tree *mt);
 682
 683 void
 684 intel_miptree_updownsample(struct brw_context *brw,
 685                            struct intel_mipmap_tree *src,
 686                            struct intel_mipmap_tree *dst);
 687
 688 void
 689 intel_update_r8stencil(struct brw_context *brw,
 690                        struct intel_mipmap_tree *mt);
 691
 692 void
 693 intel_miptree_map(struct brw_context *brw,
 694                   struct intel_mipmap_tree *mt,
 695                   unsigned int level,
 696                   unsigned int slice,
 697                   unsigned int x,
 698                   unsigned int y,
 699                   unsigned int w,
 700                   unsigned int h,
 701                   GLbitfield mode,
 702                   void **out_ptr,
 703                   ptrdiff_t *out_stride);
 704
 705 void
 706 intel_miptree_unmap(struct brw_context *brw,
 707                     struct intel_mipmap_tree *mt,
 708                     unsigned int level,
 709                     unsigned int slice);
 710
 711 bool
 712 intel_miptree_sample_with_hiz(struct brw_context *brw,
 713                               struct intel_mipmap_tree *mt);
 714
 715 bool
 716 intel_miptree_set_clear_color(struct brw_context *brw,
 717                               struct intel_mipmap_tree *mt,
 718                               const union gl_color_union *color);
 719
 720 /* Get a clear color suitable for filling out an ISL surface state. */
 721 union isl_color_value
 722 intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
 723                               const struct intel_mipmap_tree *mt,
 724                               enum isl_format view_format, bool sampling,
 725                               struct brw_bo **clear_color_bo,
 726                               uint32_t *clear_color_offset);
 727
 728 bool
 729 intel_miptree_set_depth_clear_value(struct brw_context *brw,
 730                                     struct intel_mipmap_tree *mt,
 731                                     float clear_value);
 732
 733 #ifdef __cplusplus
 734 }
 735 #endif
 736
 737 #endif