1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
31 #include "main/glheader.h"
32 #include "main/context.h"
33 #include "main/framebuffer.h"
34 #include "main/renderbuffer.h"
35 #include "main/texobj.h"
36 #include "main/hash.h"
37 #include "main/fbobject.h"
38 #include "main/version.h"
39 #include "swrast/s_renderbuffer.h"
40 #include "util/ralloc.h"
45 static const __DRIconfigOptionsExtension brw_config_options
= {
46 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
49 DRI_CONF_SECTION_PERFORMANCE
50 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
61 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
62 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
66 DRI_CONF_SECTION_QUALITY
67 DRI_CONF_FORCE_S3TC_ENABLE("false")
69 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
70 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
71 "given integer. If negative, then do not clamp.")
75 DRI_CONF_SECTION_DEBUG
76 DRI_CONF_NO_RAST("false")
77 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
78 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
79 DRI_CONF_DISABLE_THROTTLING("false")
80 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
81 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
82 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
83 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
85 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
86 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 #include "intel_batchbuffer.h"
93 #include "intel_buffers.h"
94 #include "intel_bufmgr.h"
95 #include "intel_fbo.h"
96 #include "intel_mipmap_tree.h"
97 #include "intel_screen.h"
98 #include "intel_tex.h"
99 #include "intel_image.h"
101 #include "brw_context.h"
103 #include "i915_drm.h"
106 * For debugging purposes, this returns a time in seconds.
113 clock_gettime(CLOCK_MONOTONIC
, &tp
);
115 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
119 aub_dump_bmp(struct gl_context
*ctx
)
121 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
123 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
124 struct intel_renderbuffer
*irb
=
125 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
127 if (irb
&& irb
->mt
) {
128 enum aub_dump_bmp_format format
;
130 switch (irb
->Base
.Base
.Format
) {
131 case MESA_FORMAT_B8G8R8A8_UNORM
:
132 case MESA_FORMAT_B8G8R8X8_UNORM
:
133 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
139 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
142 irb
->Base
.Base
.Width
,
143 irb
->Base
.Base
.Height
,
151 static const __DRItexBufferExtension intelTexBufferExtension
= {
152 .base
= { __DRI_TEX_BUFFER
, 3 },
154 .setTexBuffer
= intelSetTexBuffer
,
155 .setTexBuffer2
= intelSetTexBuffer2
,
156 .releaseTexBuffer
= NULL
,
160 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
161 __DRIdrawable
*dPriv
,
163 enum __DRI2throttleReason reason
)
165 struct brw_context
*brw
= cPriv
->driverPrivate
;
170 struct gl_context
*ctx
= &brw
->ctx
;
172 FLUSH_VERTICES(ctx
, 0);
174 if (flags
& __DRI2_FLUSH_DRAWABLE
)
175 intel_resolve_for_dri2_flush(brw
, dPriv
);
177 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
178 brw
->need_swap_throttle
= true;
179 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
180 brw
->need_flush_throttle
= true;
182 intel_batchbuffer_flush(brw
);
184 if (INTEL_DEBUG
& DEBUG_AUB
) {
190 * Provides compatibility with loaders that only support the older (version
191 * 1-3) flush interface.
193 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
196 intel_dri2_flush(__DRIdrawable
*drawable
)
198 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
199 __DRI2_FLUSH_DRAWABLE
,
200 __DRI2_THROTTLE_SWAPBUFFER
);
203 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
204 .base
= { __DRI2_FLUSH
, 4 },
206 .flush
= intel_dri2_flush
,
207 .invalidate
= dri2InvalidateDrawable
,
208 .flush_with_flags
= intel_dri2_flush_with_flags
,
211 static struct intel_image_format intel_image_formats
[] = {
212 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
215 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
218 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
221 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
224 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
227 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
230 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
235 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
236 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
240 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
245 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
250 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
255 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
259 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
263 /* For YUYV buffers, we set up two overlapping DRI images and treat
264 * them as planar buffers in the compositors. Plane 0 is GR88 and
265 * samples YU or YV pairs and places Y into the R component, while
266 * plane 1 is ARGB and samples YUYV clusters and places pairs and
267 * places U into the G component and V into A. This lets the
268 * texture sampler interpolate the Y components correctly when
269 * sampling from plane 0, and interpolate U and V correctly when
270 * sampling from plane 1. */
271 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
273 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
277 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
279 uint32_t tiling
, swizzle
;
280 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
282 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
283 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
284 func
, image
->offset
);
288 static struct intel_image_format
*
289 intel_image_format_lookup(int fourcc
)
291 struct intel_image_format
*f
= NULL
;
293 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
294 if (intel_image_formats
[i
].fourcc
== fourcc
) {
295 f
= &intel_image_formats
[i
];
303 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
305 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
306 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
307 *fourcc
= intel_image_formats
[i
].fourcc
;
315 intel_allocate_image(int dri_format
, void *loaderPrivate
)
319 image
= calloc(1, sizeof *image
);
323 image
->dri_format
= dri_format
;
326 image
->format
= driImageFormatToGLFormat(dri_format
);
327 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
328 image
->format
== MESA_FORMAT_NONE
) {
333 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
334 image
->data
= loaderPrivate
;
340 * Sets up a DRIImage structure to point to a slice out of a miptree.
343 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
344 struct intel_mipmap_tree
*mt
, GLuint level
,
347 intel_miptree_make_shareable(brw
, mt
);
349 intel_miptree_check_level_layer(mt
, level
, zoffset
);
351 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
352 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
353 image
->pitch
= mt
->pitch
;
355 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
359 drm_intel_bo_unreference(image
->bo
);
361 drm_intel_bo_reference(mt
->bo
);
365 intel_create_image_from_name(__DRIscreen
*screen
,
366 int width
, int height
, int format
,
367 int name
, int pitch
, void *loaderPrivate
)
369 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
373 image
= intel_allocate_image(format
, loaderPrivate
);
377 if (image
->format
== MESA_FORMAT_NONE
)
380 cpp
= _mesa_get_format_bytes(image
->format
);
382 image
->width
= width
;
383 image
->height
= height
;
384 image
->pitch
= pitch
* cpp
;
385 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
396 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
397 int renderbuffer
, void *loaderPrivate
)
400 struct brw_context
*brw
= context
->driverPrivate
;
401 struct gl_context
*ctx
= &brw
->ctx
;
402 struct gl_renderbuffer
*rb
;
403 struct intel_renderbuffer
*irb
;
405 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
407 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
411 irb
= intel_renderbuffer(rb
);
412 intel_miptree_make_shareable(brw
, irb
->mt
);
413 image
= calloc(1, sizeof *image
);
417 image
->internal_format
= rb
->InternalFormat
;
418 image
->format
= rb
->Format
;
420 image
->data
= loaderPrivate
;
421 drm_intel_bo_unreference(image
->bo
);
422 image
->bo
= irb
->mt
->bo
;
423 drm_intel_bo_reference(irb
->mt
->bo
);
424 image
->width
= rb
->Width
;
425 image
->height
= rb
->Height
;
426 image
->pitch
= irb
->mt
->pitch
;
427 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
428 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
430 rb
->NeedsFinishRenderTexture
= true;
435 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
436 unsigned texture
, int zoffset
,
442 struct brw_context
*brw
= context
->driverPrivate
;
443 struct gl_texture_object
*obj
;
444 struct intel_texture_object
*iobj
;
447 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
448 if (!obj
|| obj
->Target
!= target
) {
449 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
453 if (target
== GL_TEXTURE_CUBE_MAP
)
456 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
457 iobj
= intel_texture_object(obj
);
458 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
459 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
463 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
464 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
468 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
469 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
472 image
= calloc(1, sizeof *image
);
474 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
478 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
479 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
480 image
->data
= loaderPrivate
;
481 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
482 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
483 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
484 if (image
->dri_format
== MESA_FORMAT_NONE
) {
485 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
490 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
495 intel_destroy_image(__DRIimage
*image
)
497 drm_intel_bo_unreference(image
->bo
);
502 intel_create_image(__DRIscreen
*screen
,
503 int width
, int height
, int format
,
508 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
513 tiling
= I915_TILING_X
;
514 if (use
& __DRI_IMAGE_USE_CURSOR
) {
515 if (width
!= 64 || height
!= 64)
517 tiling
= I915_TILING_NONE
;
520 if (use
& __DRI_IMAGE_USE_LINEAR
)
521 tiling
= I915_TILING_NONE
;
523 image
= intel_allocate_image(format
, loaderPrivate
);
528 cpp
= _mesa_get_format_bytes(image
->format
);
529 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
530 width
, height
, cpp
, &tiling
,
532 if (image
->bo
== NULL
) {
536 image
->width
= width
;
537 image
->height
= height
;
538 image
->pitch
= pitch
;
544 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
547 case __DRI_IMAGE_ATTRIB_STRIDE
:
548 *value
= image
->pitch
;
550 case __DRI_IMAGE_ATTRIB_HANDLE
:
551 *value
= image
->bo
->handle
;
553 case __DRI_IMAGE_ATTRIB_NAME
:
554 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
555 case __DRI_IMAGE_ATTRIB_FORMAT
:
556 *value
= image
->dri_format
;
558 case __DRI_IMAGE_ATTRIB_WIDTH
:
559 *value
= image
->width
;
561 case __DRI_IMAGE_ATTRIB_HEIGHT
:
562 *value
= image
->height
;
564 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
565 if (image
->planar_format
== NULL
)
567 *value
= image
->planar_format
->components
;
569 case __DRI_IMAGE_ATTRIB_FD
:
570 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
573 case __DRI_IMAGE_ATTRIB_FOURCC
:
574 if (intel_lookup_fourcc(image
->dri_format
, value
))
577 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
587 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
591 image
= calloc(1, sizeof *image
);
595 drm_intel_bo_reference(orig_image
->bo
);
596 image
->bo
= orig_image
->bo
;
597 image
->internal_format
= orig_image
->internal_format
;
598 image
->planar_format
= orig_image
->planar_format
;
599 image
->dri_format
= orig_image
->dri_format
;
600 image
->format
= orig_image
->format
;
601 image
->offset
= orig_image
->offset
;
602 image
->width
= orig_image
->width
;
603 image
->height
= orig_image
->height
;
604 image
->pitch
= orig_image
->pitch
;
605 image
->tile_x
= orig_image
->tile_x
;
606 image
->tile_y
= orig_image
->tile_y
;
607 image
->has_depthstencil
= orig_image
->has_depthstencil
;
608 image
->data
= loaderPrivate
;
610 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
611 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
617 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
619 if (use
& __DRI_IMAGE_USE_CURSOR
) {
620 if (image
->width
!= 64 || image
->height
!= 64)
628 intel_create_image_from_names(__DRIscreen
*screen
,
629 int width
, int height
, int fourcc
,
630 int *names
, int num_names
,
631 int *strides
, int *offsets
,
634 struct intel_image_format
*f
= NULL
;
638 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
641 f
= intel_image_format_lookup(fourcc
);
645 image
= intel_create_image_from_name(screen
, width
, height
,
646 __DRI_IMAGE_FORMAT_NONE
,
647 names
[0], strides
[0],
653 image
->planar_format
= f
;
654 for (i
= 0; i
< f
->nplanes
; i
++) {
655 index
= f
->planes
[i
].buffer_index
;
656 image
->offsets
[index
] = offsets
[index
];
657 image
->strides
[index
] = strides
[index
];
664 intel_create_image_from_fds(__DRIscreen
*screen
,
665 int width
, int height
, int fourcc
,
666 int *fds
, int num_fds
, int *strides
, int *offsets
,
669 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
670 struct intel_image_format
*f
;
674 if (fds
== NULL
|| num_fds
!= 1)
677 f
= intel_image_format_lookup(fourcc
);
682 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
684 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
689 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
691 height
* strides
[0]);
692 if (image
->bo
== NULL
) {
696 image
->width
= width
;
697 image
->height
= height
;
698 image
->pitch
= strides
[0];
700 image
->planar_format
= f
;
701 for (i
= 0; i
< f
->nplanes
; i
++) {
702 index
= f
->planes
[i
].buffer_index
;
703 image
->offsets
[index
] = offsets
[index
];
704 image
->strides
[index
] = strides
[index
];
707 if (f
->nplanes
== 1) {
708 image
->offset
= image
->offsets
[0];
709 intel_image_warn_if_unaligned(image
, __FUNCTION__
);
716 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
717 int width
, int height
, int fourcc
,
718 int *fds
, int num_fds
,
719 int *strides
, int *offsets
,
720 enum __DRIYUVColorSpace yuv_color_space
,
721 enum __DRISampleRange sample_range
,
722 enum __DRIChromaSiting horizontal_siting
,
723 enum __DRIChromaSiting vertical_siting
,
728 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
730 /* For now only packed formats that have native sampling are supported. */
731 if (!f
|| f
->nplanes
!= 1) {
732 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
736 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
737 num_fds
, strides
, offsets
,
741 * Invalid parameters and any inconsistencies between are assumed to be
742 * checked by the caller. Therefore besides unsupported formats one can fail
743 * only in allocation.
746 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
750 image
->dma_buf_imported
= true;
751 image
->yuv_color_space
= yuv_color_space
;
752 image
->sample_range
= sample_range
;
753 image
->horizontal_siting
= horizontal_siting
;
754 image
->vertical_siting
= vertical_siting
;
756 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
761 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
763 int width
, height
, offset
, stride
, dri_format
, index
;
764 struct intel_image_format
*f
;
767 if (parent
== NULL
|| parent
->planar_format
== NULL
)
770 f
= parent
->planar_format
;
772 if (plane
>= f
->nplanes
)
775 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
776 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
777 dri_format
= f
->planes
[plane
].dri_format
;
778 index
= f
->planes
[plane
].buffer_index
;
779 offset
= parent
->offsets
[index
];
780 stride
= parent
->strides
[index
];
782 image
= intel_allocate_image(dri_format
, loaderPrivate
);
786 if (offset
+ height
* stride
> parent
->bo
->size
) {
787 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
792 image
->bo
= parent
->bo
;
793 drm_intel_bo_reference(parent
->bo
);
795 image
->width
= width
;
796 image
->height
= height
;
797 image
->pitch
= stride
;
798 image
->offset
= offset
;
800 intel_image_warn_if_unaligned(image
, __FUNCTION__
);
805 static const __DRIimageExtension intelImageExtension
= {
806 .base
= { __DRI_IMAGE
, 11 },
808 .createImageFromName
= intel_create_image_from_name
,
809 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
810 .destroyImage
= intel_destroy_image
,
811 .createImage
= intel_create_image
,
812 .queryImage
= intel_query_image
,
813 .dupImage
= intel_dup_image
,
814 .validateUsage
= intel_validate_usage
,
815 .createImageFromNames
= intel_create_image_from_names
,
816 .fromPlanar
= intel_from_planar
,
817 .createImageFromTexture
= intel_create_image_from_texture
,
818 .createImageFromFds
= intel_create_image_from_fds
,
819 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
821 .getCapabilities
= NULL
825 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
827 const struct intel_screen
*const intelScreen
=
828 (struct intel_screen
*) psp
->driverPrivate
;
831 case __DRI2_RENDERER_VENDOR_ID
:
834 case __DRI2_RENDERER_DEVICE_ID
:
835 value
[0] = intelScreen
->deviceID
;
837 case __DRI2_RENDERER_ACCELERATED
:
840 case __DRI2_RENDERER_VIDEO_MEMORY
: {
841 /* Once a batch uses more than 75% of the maximum mappable size, we
842 * assume that there's some fragmentation, and we start doing extra
843 * flushing, etc. That's the big cliff apps will care about.
846 size_t mappable_size
;
848 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
850 const unsigned gpu_mappable_megabytes
=
851 (aper_size
/ (1024 * 1024)) * 3 / 4;
853 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
854 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
856 if (system_memory_pages
<= 0 || system_page_size
<= 0)
859 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
860 * (uint64_t) system_page_size
;
862 const unsigned system_memory_megabytes
=
863 (unsigned) (system_memory_bytes
/ (1024 * 1024));
865 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
868 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
872 return driQueryRendererIntegerCommon(psp
, param
, value
);
879 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
881 const struct intel_screen
*intelScreen
=
882 (struct intel_screen
*) psp
->driverPrivate
;
885 case __DRI2_RENDERER_VENDOR_ID
:
886 value
[0] = brw_vendor_string
;
888 case __DRI2_RENDERER_DEVICE_ID
:
889 value
[0] = brw_get_renderer_string(intelScreen
->deviceID
);
898 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
899 .base
= { __DRI2_RENDERER_QUERY
, 1 },
901 .queryInteger
= brw_query_renderer_integer
,
902 .queryString
= brw_query_renderer_string
905 static const __DRIrobustnessExtension dri2Robustness
= {
906 .base
= { __DRI2_ROBUSTNESS
, 1 }
909 static const __DRIextension
*intelScreenExtensions
[] = {
910 &intelTexBufferExtension
.base
,
911 &intelFlushExtension
.base
,
912 &intelImageExtension
.base
,
913 &intelRendererQueryExtension
.base
,
914 &dri2ConfigQueryExtension
.base
,
918 static const __DRIextension
*intelRobustScreenExtensions
[] = {
919 &intelTexBufferExtension
.base
,
920 &intelFlushExtension
.base
,
921 &intelImageExtension
.base
,
922 &intelRendererQueryExtension
.base
,
923 &dri2ConfigQueryExtension
.base
,
924 &dri2Robustness
.base
,
929 intel_get_param(__DRIscreen
*psp
, int param
, int *value
)
932 struct drm_i915_getparam gp
;
934 memset(&gp
, 0, sizeof(gp
));
938 ret
= drmCommandWriteRead(psp
->fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
941 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
949 intel_get_boolean(__DRIscreen
*psp
, int param
)
952 return intel_get_param(psp
, param
, &value
) && value
;
956 intelDestroyScreen(__DRIscreen
* sPriv
)
958 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
960 dri_bufmgr_destroy(intelScreen
->bufmgr
);
961 driDestroyOptionInfo(&intelScreen
->optionCache
);
963 ralloc_free(intelScreen
);
964 sPriv
->driverPrivate
= NULL
;
969 * This is called when we need to set up GL rendering to a new X window.
972 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
973 __DRIdrawable
* driDrawPriv
,
974 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
976 struct intel_renderbuffer
*rb
;
977 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
978 mesa_format rgbFormat
;
979 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
980 struct gl_framebuffer
*fb
;
985 fb
= CALLOC_STRUCT(gl_framebuffer
);
989 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
991 if (screen
->winsys_msaa_samples_override
!= -1) {
992 num_samples
= screen
->winsys_msaa_samples_override
;
993 fb
->Visual
.samples
= num_samples
;
996 if (mesaVis
->redBits
== 5)
997 rgbFormat
= MESA_FORMAT_B5G6R5_UNORM
;
998 else if (mesaVis
->sRGBCapable
)
999 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
1000 else if (mesaVis
->alphaBits
== 0)
1001 rgbFormat
= MESA_FORMAT_B8G8R8X8_UNORM
;
1003 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
1004 fb
->Visual
.sRGBCapable
= true;
1007 /* setup the hardware-based renderbuffers */
1008 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1009 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1011 if (mesaVis
->doubleBufferMode
) {
1012 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1013 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1017 * Assert here that the gl_config has an expected depth/stencil bit
1018 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1019 * which constructs the advertised configs.)
1021 if (mesaVis
->depthBits
== 24) {
1022 assert(mesaVis
->stencilBits
== 8);
1024 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1025 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1027 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1028 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1030 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1033 * Use combined depth/stencil. Note that the renderbuffer is
1034 * attached to two attachment points.
1036 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1038 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1039 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1042 else if (mesaVis
->depthBits
== 16) {
1043 assert(mesaVis
->stencilBits
== 0);
1044 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1046 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1049 assert(mesaVis
->depthBits
== 0);
1050 assert(mesaVis
->stencilBits
== 0);
1053 /* now add any/all software-based renderbuffers we may need */
1054 _swrast_add_soft_renderbuffers(fb
,
1055 false, /* never sw color */
1056 false, /* never sw depth */
1057 false, /* never sw stencil */
1058 mesaVis
->accumRedBits
> 0,
1059 false, /* never sw alpha */
1060 false /* never sw aux */ );
1061 driDrawPriv
->driverPrivate
= fb
;
1067 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1069 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1071 _mesa_reference_framebuffer(&fb
, NULL
);
1075 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1077 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1079 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1081 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1082 if (intelScreen
->bufmgr
== NULL
) {
1083 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1084 __func__
, __LINE__
);
1088 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1090 if (!intel_get_boolean(spriv
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1091 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1099 intel_detect_swizzling(struct intel_screen
*screen
)
1101 drm_intel_bo
*buffer
;
1102 unsigned long flags
= 0;
1103 unsigned long aligned_pitch
;
1104 uint32_t tiling
= I915_TILING_X
;
1105 uint32_t swizzle_mode
= 0;
1107 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1109 &tiling
, &aligned_pitch
, flags
);
1113 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1114 drm_intel_bo_unreference(buffer
);
1116 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1123 * Return array of MSAA modes supported by the hardware. The array is
1124 * zero-terminated and sorted in decreasing order.
1127 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1129 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1130 static const int gen7_modes
[] = {8, 4, 0, -1};
1131 static const int gen6_modes
[] = {4, 0, -1};
1132 static const int gen4_modes
[] = {0, -1};
1134 if (screen
->devinfo
->gen
>= 8) {
1136 } else if (screen
->devinfo
->gen
>= 7) {
1138 } else if (screen
->devinfo
->gen
== 6) {
1145 static __DRIconfig
**
1146 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1148 static const mesa_format formats
[] = {
1149 MESA_FORMAT_B5G6R5_UNORM
,
1150 MESA_FORMAT_B8G8R8A8_UNORM
1153 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1154 static const GLenum back_buffer_modes
[] = {
1155 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1158 static const uint8_t singlesample_samples
[1] = {0};
1159 static const uint8_t multisample_samples
[2] = {4, 8};
1161 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1162 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1163 uint8_t depth_bits
[4], stencil_bits
[4];
1164 __DRIconfig
**configs
= NULL
;
1166 /* Generate singlesample configs without accumulation buffer. */
1167 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1168 __DRIconfig
**new_configs
;
1169 int num_depth_stencil_bits
= 2;
1171 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1172 * buffer that has a different number of bits per pixel than the color
1173 * buffer, gen >= 6 supports this.
1176 stencil_bits
[0] = 0;
1178 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1180 stencil_bits
[1] = 0;
1181 if (devinfo
->gen
>= 6) {
1183 stencil_bits
[2] = 8;
1184 num_depth_stencil_bits
= 3;
1188 stencil_bits
[1] = 8;
1191 new_configs
= driCreateConfigs(formats
[i
],
1194 num_depth_stencil_bits
,
1195 back_buffer_modes
, 2,
1196 singlesample_samples
, 1,
1198 configs
= driConcatConfigs(configs
, new_configs
);
1201 /* Generate the minimum possible set of configs that include an
1202 * accumulation buffer.
1204 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1205 __DRIconfig
**new_configs
;
1207 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1209 stencil_bits
[0] = 0;
1212 stencil_bits
[0] = 8;
1215 new_configs
= driCreateConfigs(formats
[i
],
1216 depth_bits
, stencil_bits
, 1,
1217 back_buffer_modes
, 1,
1218 singlesample_samples
, 1,
1220 configs
= driConcatConfigs(configs
, new_configs
);
1223 /* Generate multisample configs.
1225 * This loop breaks early, and hence is a no-op, on gen < 6.
1227 * Multisample configs must follow the singlesample configs in order to
1228 * work around an X server bug present in 1.12. The X server chooses to
1229 * associate the first listed RGBA888-Z24S8 config, regardless of its
1230 * sample count, with the 32-bit depth visual used for compositing.
1232 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1233 * supported. Singlebuffer configs are not supported because no one wants
1236 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1237 if (devinfo
->gen
< 6)
1240 __DRIconfig
**new_configs
;
1241 const int num_depth_stencil_bits
= 2;
1242 int num_msaa_modes
= 0;
1245 stencil_bits
[0] = 0;
1247 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1249 stencil_bits
[1] = 0;
1252 stencil_bits
[1] = 8;
1255 if (devinfo
->gen
>= 7)
1257 else if (devinfo
->gen
== 6)
1260 new_configs
= driCreateConfigs(formats
[i
],
1263 num_depth_stencil_bits
,
1264 back_buffer_modes
, 1,
1265 multisample_samples
,
1268 configs
= driConcatConfigs(configs
, new_configs
);
1271 if (configs
== NULL
) {
1272 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1281 set_max_gl_versions(struct intel_screen
*screen
)
1283 __DRIscreen
*psp
= screen
->driScrnPriv
;
1285 switch (screen
->devinfo
->gen
) {
1290 psp
->max_gl_core_version
= 33;
1291 psp
->max_gl_compat_version
= 30;
1292 psp
->max_gl_es1_version
= 11;
1293 psp
->max_gl_es2_version
= 30;
1297 psp
->max_gl_core_version
= 0;
1298 psp
->max_gl_compat_version
= 21;
1299 psp
->max_gl_es1_version
= 11;
1300 psp
->max_gl_es2_version
= 20;
1303 unreachable("unrecognized intel_screen::gen");
1308 * This is the driver specific part of the createNewScreen entry point.
1309 * Called when using DRI2.
1311 * \return the struct gl_config supported by this driver
1314 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1316 struct intel_screen
*intelScreen
;
1318 if (psp
->image
.loader
) {
1319 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1320 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1322 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1323 "support required\n");
1327 /* Allocate the private area */
1328 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1330 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1333 /* parse information in __driConfigOptions */
1334 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1336 intelScreen
->driScrnPriv
= psp
;
1337 psp
->driverPrivate
= (void *) intelScreen
;
1339 if (!intel_init_bufmgr(intelScreen
))
1342 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1343 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
);
1344 if (!intelScreen
->devinfo
)
1347 intelScreen
->hw_must_use_separate_stencil
= intelScreen
->devinfo
->gen
>= 7;
1349 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1351 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1353 intelScreen
->winsys_msaa_samples_override
=
1354 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1355 printf("Forcing winsys sample count to %d\n",
1356 intelScreen
->winsys_msaa_samples_override
);
1358 intelScreen
->winsys_msaa_samples_override
= -1;
1361 set_max_gl_versions(intelScreen
);
1363 /* Notification of GPU resets requires hardware contexts and a kernel new
1364 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1365 * supported, calling it with a context of 0 will either generate EPERM or
1366 * no error. If the ioctl is not supported, it always generate EINVAL.
1367 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1368 * extension to the loader.
1370 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1372 if (intelScreen
->devinfo
->gen
>= 6) {
1373 struct drm_i915_reset_stats stats
;
1374 memset(&stats
, 0, sizeof(stats
));
1376 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1378 intelScreen
->has_context_reset_notification
=
1379 (ret
!= -1 || errno
!= EINVAL
);
1382 psp
->extensions
= !intelScreen
->has_context_reset_notification
1383 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1385 brw_fs_alloc_reg_sets(intelScreen
);
1386 brw_vec4_alloc_reg_set(intelScreen
);
1388 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1391 struct intel_buffer
{
1396 static __DRIbuffer
*
1397 intelAllocateBuffer(__DRIscreen
*screen
,
1398 unsigned attachment
, unsigned format
,
1399 int width
, int height
)
1401 struct intel_buffer
*intelBuffer
;
1402 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1404 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1405 attachment
== __DRI_BUFFER_BACK_LEFT
);
1407 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1408 if (intelBuffer
== NULL
)
1411 /* The front and back buffers are color buffers, which are X tiled. */
1412 uint32_t tiling
= I915_TILING_X
;
1413 unsigned long pitch
;
1414 int cpp
= format
/ 8;
1415 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1416 "intelAllocateBuffer",
1421 BO_ALLOC_FOR_RENDER
);
1423 if (intelBuffer
->bo
== NULL
) {
1428 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1430 intelBuffer
->base
.attachment
= attachment
;
1431 intelBuffer
->base
.cpp
= cpp
;
1432 intelBuffer
->base
.pitch
= pitch
;
1434 return &intelBuffer
->base
;
1438 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1440 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1442 drm_intel_bo_unreference(intelBuffer
->bo
);
1446 static const struct __DriverAPIRec brw_driver_api
= {
1447 .InitScreen
= intelInitScreen2
,
1448 .DestroyScreen
= intelDestroyScreen
,
1449 .CreateContext
= brwCreateContext
,
1450 .DestroyContext
= intelDestroyContext
,
1451 .CreateBuffer
= intelCreateBuffer
,
1452 .DestroyBuffer
= intelDestroyBuffer
,
1453 .MakeCurrent
= intelMakeCurrent
,
1454 .UnbindContext
= intelUnbindContext
,
1455 .AllocateBuffer
= intelAllocateBuffer
,
1456 .ReleaseBuffer
= intelReleaseBuffer
1459 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1460 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1461 .vtable
= &brw_driver_api
,
1464 static const __DRIextension
*brw_driver_extensions
[] = {
1465 &driCoreExtension
.base
,
1466 &driImageDriverExtension
.base
,
1467 &driDRI2Extension
.base
,
1469 &brw_config_options
.base
,
1473 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1475 globalDriverAPI
= &brw_driver_api
;
1477 return brw_driver_extensions
;