intel: Start adding defines and some bits for sandybridge bringup.
[mesa.git] / src / mesa / drivers / dri / intel / intel_blit.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
33
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41
42 #define FILE_DEBUG_FLAG DEBUG_BLIT
43
44 static GLuint translate_raster_op(GLenum logicop)
45 {
46 switch(logicop) {
47 case GL_CLEAR: return 0x00;
48 case GL_AND: return 0x88;
49 case GL_AND_REVERSE: return 0x44;
50 case GL_COPY: return 0xCC;
51 case GL_AND_INVERTED: return 0x22;
52 case GL_NOOP: return 0xAA;
53 case GL_XOR: return 0x66;
54 case GL_OR: return 0xEE;
55 case GL_NOR: return 0x11;
56 case GL_EQUIV: return 0x99;
57 case GL_INVERT: return 0x55;
58 case GL_OR_REVERSE: return 0xDD;
59 case GL_COPY_INVERTED: return 0x33;
60 case GL_OR_INVERTED: return 0xBB;
61 case GL_NAND: return 0x77;
62 case GL_SET: return 0xFF;
63 default: return 0;
64 }
65 }
66
67
68 /* Copy BitBlt
69 */
70 GLboolean
71 intelEmitCopyBlit(struct intel_context *intel,
72 GLuint cpp,
73 GLshort src_pitch,
74 dri_bo *src_buffer,
75 GLuint src_offset,
76 uint32_t src_tiling,
77 GLshort dst_pitch,
78 dri_bo *dst_buffer,
79 GLuint dst_offset,
80 uint32_t dst_tiling,
81 GLshort src_x, GLshort src_y,
82 GLshort dst_x, GLshort dst_y,
83 GLshort w, GLshort h,
84 GLenum logic_op)
85 {
86 GLuint CMD, BR13, pass = 0;
87 int dst_y2 = dst_y + h;
88 int dst_x2 = dst_x + w;
89 dri_bo *aper_array[3];
90 BATCH_LOCALS;
91
92 /* Blits are in a different ringbuffer so we don't use them. */
93 if (intel->gen >= 6)
94 return GL_FALSE;
95
96 if (dst_tiling != I915_TILING_NONE) {
97 if (dst_offset & 4095)
98 return GL_FALSE;
99 if (dst_tiling == I915_TILING_Y)
100 return GL_FALSE;
101 }
102 if (src_tiling != I915_TILING_NONE) {
103 if (src_offset & 4095)
104 return GL_FALSE;
105 if (src_tiling == I915_TILING_Y)
106 return GL_FALSE;
107 }
108
109 /* do space check before going any further */
110 do {
111 aper_array[0] = intel->batch->buf;
112 aper_array[1] = dst_buffer;
113 aper_array[2] = src_buffer;
114
115 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
116 intel_batchbuffer_flush(intel->batch);
117 pass++;
118 } else
119 break;
120 } while (pass < 2);
121
122 intel_prepare_render(intel);
123
124 if (pass >= 2) {
125 dri_bo_map(dst_buffer, GL_TRUE);
126 dri_bo_map(src_buffer, GL_FALSE);
127 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
128 cpp,
129 dst_pitch,
130 dst_x, dst_y,
131 w, h,
132 (GLubyte *)src_buffer->virtual + src_offset,
133 src_pitch,
134 src_x, src_y);
135
136 dri_bo_unmap(src_buffer);
137 dri_bo_unmap(dst_buffer);
138
139 return GL_TRUE;
140 }
141
142 intel_batchbuffer_require_space(intel->batch, 8 * 4);
143 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
144 __FUNCTION__,
145 src_buffer, src_pitch, src_offset, src_x, src_y,
146 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
147
148 src_pitch *= cpp;
149 dst_pitch *= cpp;
150
151 BR13 = translate_raster_op(logic_op) << 16;
152
153 switch (cpp) {
154 case 1:
155 CMD = XY_SRC_COPY_BLT_CMD;
156 break;
157 case 2:
158 BR13 |= BR13_565;
159 CMD = XY_SRC_COPY_BLT_CMD;
160 break;
161 case 4:
162 BR13 |= BR13_8888;
163 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
164 break;
165 default:
166 return GL_FALSE;
167 }
168
169 #ifndef I915
170 if (dst_tiling != I915_TILING_NONE) {
171 CMD |= XY_DST_TILED;
172 dst_pitch /= 4;
173 }
174 if (src_tiling != I915_TILING_NONE) {
175 CMD |= XY_SRC_TILED;
176 src_pitch /= 4;
177 }
178 #endif
179
180 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
181 return GL_TRUE;
182 }
183
184 assert(dst_x < dst_x2);
185 assert(dst_y < dst_y2);
186
187 BEGIN_BATCH(8);
188 OUT_BATCH(CMD);
189 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
190 OUT_BATCH((dst_y << 16) | dst_x);
191 OUT_BATCH((dst_y2 << 16) | dst_x2);
192 OUT_RELOC(dst_buffer,
193 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
194 dst_offset);
195 OUT_BATCH((src_y << 16) | src_x);
196 OUT_BATCH((uint16_t)src_pitch);
197 OUT_RELOC(src_buffer,
198 I915_GEM_DOMAIN_RENDER, 0,
199 src_offset);
200 ADVANCE_BATCH();
201
202 intel_batchbuffer_emit_mi_flush(intel->batch);
203
204 return GL_TRUE;
205 }
206
207
208 /**
209 * Use blitting to clear the renderbuffers named by 'flags'.
210 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
211 * since that might include software renderbuffers or renderbuffers
212 * which we're clearing with triangles.
213 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
214 */
215 void
216 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
217 {
218 struct intel_context *intel = intel_context(ctx);
219 struct gl_framebuffer *fb = ctx->DrawBuffer;
220 GLuint clear_depth;
221 GLboolean all;
222 GLint cx, cy, cw, ch;
223 BATCH_LOCALS;
224
225 /* Blits are in a different ringbuffer so we don't use them. */
226 assert(intel->gen < 6);
227
228 /*
229 * Compute values for clearing the buffers.
230 */
231 clear_depth = 0;
232 if (mask & BUFFER_BIT_DEPTH) {
233 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
234 }
235 if (mask & BUFFER_BIT_STENCIL) {
236 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
237 }
238
239 cx = fb->_Xmin;
240 if (fb->Name == 0)
241 cy = ctx->DrawBuffer->Height - fb->_Ymax;
242 else
243 cy = fb->_Ymin;
244 cw = fb->_Xmax - fb->_Xmin;
245 ch = fb->_Ymax - fb->_Ymin;
246
247 if (cw == 0 || ch == 0)
248 return;
249
250 GLuint buf;
251 all = (cw == fb->Width && ch == fb->Height);
252
253 intel_prepare_render(intel);
254
255 /* Loop over all renderbuffers */
256 for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
257 const GLbitfield bufBit = 1 << buf;
258 struct intel_renderbuffer *irb;
259 drm_intel_bo *write_buffer;
260 int x1, y1, x2, y2;
261 uint32_t clear_val;
262 uint32_t BR13, CMD;
263 int pitch, cpp;
264 drm_intel_bo *aper_array[2];
265
266 if (!(mask & bufBit))
267 continue;
268
269 /* OK, clear this renderbuffer */
270 irb = intel_get_renderbuffer(fb, buf);
271 write_buffer = intel_region_buffer(intel, irb->region,
272 all ? INTEL_WRITE_FULL :
273 INTEL_WRITE_PART);
274 x1 = cx + irb->region->draw_x;
275 y1 = cy + irb->region->draw_y;
276 x2 = cx + cw + irb->region->draw_x;
277 y2 = cy + ch + irb->region->draw_y;
278
279 pitch = irb->region->pitch;
280 cpp = irb->region->cpp;
281
282 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
283 __FUNCTION__,
284 irb->region->buffer, (pitch * cpp),
285 x1, y1, x2 - x1, y2 - y1);
286
287 BR13 = 0xf0 << 16;
288 CMD = XY_COLOR_BLT_CMD;
289
290 /* Setup the blit command */
291 if (cpp == 4) {
292 BR13 |= BR13_8888;
293 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
294 if (mask & BUFFER_BIT_DEPTH)
295 CMD |= XY_BLT_WRITE_RGB;
296 if (mask & BUFFER_BIT_STENCIL)
297 CMD |= XY_BLT_WRITE_ALPHA;
298 } else {
299 /* clearing RGBA */
300 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
301 }
302 } else {
303 ASSERT(cpp == 2);
304 BR13 |= BR13_565;
305 }
306
307 assert(irb->region->tiling != I915_TILING_Y);
308
309 #ifndef I915
310 if (irb->region->tiling != I915_TILING_NONE) {
311 CMD |= XY_DST_TILED;
312 pitch /= 4;
313 }
314 #endif
315 BR13 |= (pitch * cpp);
316
317 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
318 clear_val = clear_depth;
319 } else {
320 uint8_t clear[4];
321 GLclampf *color = ctx->Color.ClearColor;
322
323 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
324 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
325 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
326 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
327
328 switch (irb->Base.Format) {
329 case MESA_FORMAT_ARGB8888:
330 case MESA_FORMAT_XRGB8888:
331 clear_val = PACK_COLOR_8888(clear[3], clear[0],
332 clear[1], clear[2]);
333 break;
334 case MESA_FORMAT_RGB565:
335 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
336 break;
337 case MESA_FORMAT_ARGB4444:
338 clear_val = PACK_COLOR_4444(clear[3], clear[0],
339 clear[1], clear[2]);
340 break;
341 case MESA_FORMAT_ARGB1555:
342 clear_val = PACK_COLOR_1555(clear[3], clear[0],
343 clear[1], clear[2]);
344 break;
345 default:
346 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
347 irb->Base.Format);
348 clear_val = 0;
349 }
350 }
351
352 assert(x1 < x2);
353 assert(y1 < y2);
354
355 /* do space check before going any further */
356 aper_array[0] = intel->batch->buf;
357 aper_array[1] = write_buffer;
358
359 if (drm_intel_bufmgr_check_aperture_space(aper_array,
360 ARRAY_SIZE(aper_array)) != 0) {
361 intel_batchbuffer_flush(intel->batch);
362 }
363
364 BEGIN_BATCH(6);
365 OUT_BATCH(CMD);
366 OUT_BATCH(BR13);
367 OUT_BATCH((y1 << 16) | x1);
368 OUT_BATCH((y2 << 16) | x2);
369 OUT_RELOC(write_buffer,
370 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
371 0);
372 OUT_BATCH(clear_val);
373 ADVANCE_BATCH();
374
375 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
376 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
377 else
378 mask &= ~bufBit; /* turn off bit, for faster loop exit */
379 }
380 }
381
382 GLboolean
383 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
384 GLuint cpp,
385 GLubyte *src_bits, GLuint src_size,
386 GLuint fg_color,
387 GLshort dst_pitch,
388 dri_bo *dst_buffer,
389 GLuint dst_offset,
390 uint32_t dst_tiling,
391 GLshort x, GLshort y,
392 GLshort w, GLshort h,
393 GLenum logic_op)
394 {
395 int dwords = ALIGN(src_size, 8) / 4;
396 uint32_t opcode, br13, blit_cmd;
397
398 /* Blits are in a different ringbuffer so we don't use them. */
399 if (intel->gen >= 6)
400 return GL_FALSE;
401
402 if (dst_tiling != I915_TILING_NONE) {
403 if (dst_offset & 4095)
404 return GL_FALSE;
405 if (dst_tiling == I915_TILING_Y)
406 return GL_FALSE;
407 }
408
409 assert( logic_op - GL_CLEAR >= 0 );
410 assert( logic_op - GL_CLEAR < 0x10 );
411 assert(dst_pitch > 0);
412
413 if (w < 0 || h < 0)
414 return GL_TRUE;
415
416 dst_pitch *= cpp;
417
418 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
419 __FUNCTION__,
420 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
421
422 intel_batchbuffer_require_space( intel->batch,
423 (8 * 4) +
424 (3 * 4) +
425 dwords * 4 );
426
427 opcode = XY_SETUP_BLT_CMD;
428 if (cpp == 4)
429 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
430 #ifndef I915
431 if (dst_tiling != I915_TILING_NONE) {
432 opcode |= XY_DST_TILED;
433 dst_pitch /= 4;
434 }
435 #endif
436
437 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
438 if (cpp == 2)
439 br13 |= BR13_565;
440 else
441 br13 |= BR13_8888;
442
443 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
444 if (dst_tiling != I915_TILING_NONE)
445 blit_cmd |= XY_DST_TILED;
446
447 BEGIN_BATCH(8 + 3);
448 OUT_BATCH(opcode);
449 OUT_BATCH(br13);
450 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
451 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
452 OUT_RELOC(dst_buffer,
453 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
454 dst_offset);
455 OUT_BATCH(0); /* bg */
456 OUT_BATCH(fg_color); /* fg */
457 OUT_BATCH(0); /* pattern base addr */
458
459 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
460 OUT_BATCH((y << 16) | x);
461 OUT_BATCH(((y + h) << 16) | (x + w));
462 ADVANCE_BATCH();
463
464 intel_batchbuffer_data( intel->batch,
465 src_bits,
466 dwords * 4 );
467
468 intel_batchbuffer_emit_mi_flush(intel->batch);
469
470 return GL_TRUE;
471 }
472
473 /* We don't have a memmove-type blit like some other hardware, so we'll do a
474 * rectangular blit covering a large space, then emit 1-scanline blit at the
475 * end to cover the last if we need.
476 */
477 void
478 intel_emit_linear_blit(struct intel_context *intel,
479 drm_intel_bo *dst_bo,
480 unsigned int dst_offset,
481 drm_intel_bo *src_bo,
482 unsigned int src_offset,
483 unsigned int size)
484 {
485 GLuint pitch, height;
486
487 /* Blits are in a different ringbuffer so we don't use them. */
488 assert(intel->gen < 6);
489
490 /* The pitch is a signed value. */
491 pitch = MIN2(size, (1 << 15) - 1);
492 height = size / pitch;
493 intelEmitCopyBlit(intel, 1,
494 pitch, src_bo, src_offset, I915_TILING_NONE,
495 pitch, dst_bo, dst_offset, I915_TILING_NONE,
496 0, 0, /* src x/y */
497 0, 0, /* dst x/y */
498 pitch, height, /* w, h */
499 GL_COPY);
500
501 src_offset += pitch * height;
502 dst_offset += pitch * height;
503 size -= pitch * height;
504 assert (size < (1 << 15));
505 if (size != 0) {
506 intelEmitCopyBlit(intel, 1,
507 size, src_bo, src_offset, I915_TILING_NONE,
508 size, dst_bo, dst_offset, I915_TILING_NONE,
509 0, 0, /* src x/y */
510 0, 0, /* dst x/y */
511 size, 1, /* w, h */
512 GL_COPY);
513 }
514 }