f4f93b5a13489af6e9399be36d565f9698a7e601
[mesa.git] / src / mesa / drivers / dri / intel / intel_blit.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
33
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41
42 #define FILE_DEBUG_FLAG DEBUG_BLIT
43
44 static GLuint translate_raster_op(GLenum logicop)
45 {
46 switch(logicop) {
47 case GL_CLEAR: return 0x00;
48 case GL_AND: return 0x88;
49 case GL_AND_REVERSE: return 0x44;
50 case GL_COPY: return 0xCC;
51 case GL_AND_INVERTED: return 0x22;
52 case GL_NOOP: return 0xAA;
53 case GL_XOR: return 0x66;
54 case GL_OR: return 0xEE;
55 case GL_NOR: return 0x11;
56 case GL_EQUIV: return 0x99;
57 case GL_INVERT: return 0x55;
58 case GL_OR_REVERSE: return 0xDD;
59 case GL_COPY_INVERTED: return 0x33;
60 case GL_OR_INVERTED: return 0xBB;
61 case GL_NAND: return 0x77;
62 case GL_SET: return 0xFF;
63 default: return 0;
64 }
65 }
66
67
68 /* Copy BitBlt
69 */
70 GLboolean
71 intelEmitCopyBlit(struct intel_context *intel,
72 GLuint cpp,
73 GLshort src_pitch,
74 dri_bo *src_buffer,
75 GLuint src_offset,
76 uint32_t src_tiling,
77 GLshort dst_pitch,
78 dri_bo *dst_buffer,
79 GLuint dst_offset,
80 uint32_t dst_tiling,
81 GLshort src_x, GLshort src_y,
82 GLshort dst_x, GLshort dst_y,
83 GLshort w, GLshort h,
84 GLenum logic_op)
85 {
86 GLuint CMD, BR13, pass = 0;
87 int dst_y2 = dst_y + h;
88 int dst_x2 = dst_x + w;
89 dri_bo *aper_array[3];
90 BATCH_LOCALS;
91
92 /* Blits are in a different ringbuffer so we don't use them. */
93 if (intel->gen >= 6)
94 return GL_FALSE;
95
96 if (dst_tiling != I915_TILING_NONE) {
97 if (dst_offset & 4095)
98 return GL_FALSE;
99 if (dst_tiling == I915_TILING_Y)
100 return GL_FALSE;
101 }
102 if (src_tiling != I915_TILING_NONE) {
103 if (src_offset & 4095)
104 return GL_FALSE;
105 if (src_tiling == I915_TILING_Y)
106 return GL_FALSE;
107 }
108
109 /* do space check before going any further */
110 do {
111 aper_array[0] = intel->batch->buf;
112 aper_array[1] = dst_buffer;
113 aper_array[2] = src_buffer;
114
115 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
116 intel_batchbuffer_flush(intel->batch);
117 pass++;
118 } else
119 break;
120 } while (pass < 2);
121
122 intel_prepare_render(intel);
123
124 if (pass >= 2) {
125 drm_intel_gem_bo_map_gtt(dst_buffer);
126 drm_intel_gem_bo_map_gtt(src_buffer);
127 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
128 cpp,
129 dst_pitch,
130 dst_x, dst_y,
131 w, h,
132 (GLubyte *)src_buffer->virtual + src_offset,
133 src_pitch,
134 src_x, src_y);
135 drm_intel_gem_bo_unmap_gtt(src_buffer);
136 drm_intel_gem_bo_unmap_gtt(dst_buffer);
137
138 return GL_TRUE;
139 }
140
141 intel_batchbuffer_require_space(intel->batch, 8 * 4);
142 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
143 __FUNCTION__,
144 src_buffer, src_pitch, src_offset, src_x, src_y,
145 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
146
147 src_pitch *= cpp;
148 dst_pitch *= cpp;
149
150 BR13 = translate_raster_op(logic_op) << 16;
151
152 switch (cpp) {
153 case 1:
154 CMD = XY_SRC_COPY_BLT_CMD;
155 break;
156 case 2:
157 BR13 |= BR13_565;
158 CMD = XY_SRC_COPY_BLT_CMD;
159 break;
160 case 4:
161 BR13 |= BR13_8888;
162 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
163 break;
164 default:
165 return GL_FALSE;
166 }
167
168 #ifndef I915
169 if (dst_tiling != I915_TILING_NONE) {
170 CMD |= XY_DST_TILED;
171 dst_pitch /= 4;
172 }
173 if (src_tiling != I915_TILING_NONE) {
174 CMD |= XY_SRC_TILED;
175 src_pitch /= 4;
176 }
177 #endif
178
179 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
180 return GL_TRUE;
181 }
182
183 assert(dst_x < dst_x2);
184 assert(dst_y < dst_y2);
185
186 BEGIN_BATCH(8);
187 OUT_BATCH(CMD);
188 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
189 OUT_BATCH((dst_y << 16) | dst_x);
190 OUT_BATCH((dst_y2 << 16) | dst_x2);
191 OUT_RELOC_FENCED(dst_buffer,
192 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
193 dst_offset);
194 OUT_BATCH((src_y << 16) | src_x);
195 OUT_BATCH((uint16_t)src_pitch);
196 OUT_RELOC_FENCED(src_buffer,
197 I915_GEM_DOMAIN_RENDER, 0,
198 src_offset);
199 ADVANCE_BATCH();
200
201 intel_batchbuffer_emit_mi_flush(intel->batch);
202
203 return GL_TRUE;
204 }
205
206
207 /**
208 * Use blitting to clear the renderbuffers named by 'flags'.
209 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
210 * since that might include software renderbuffers or renderbuffers
211 * which we're clearing with triangles.
212 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
213 */
214 void
215 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
216 {
217 struct intel_context *intel = intel_context(ctx);
218 struct gl_framebuffer *fb = ctx->DrawBuffer;
219 GLuint clear_depth;
220 GLboolean all;
221 GLint cx, cy, cw, ch;
222 BATCH_LOCALS;
223
224 /* Blits are in a different ringbuffer so we don't use them. */
225 assert(intel->gen < 6);
226
227 /*
228 * Compute values for clearing the buffers.
229 */
230 clear_depth = 0;
231 if (mask & BUFFER_BIT_DEPTH) {
232 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
233 }
234 if (mask & BUFFER_BIT_STENCIL) {
235 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
236 }
237
238 cx = fb->_Xmin;
239 if (fb->Name == 0)
240 cy = ctx->DrawBuffer->Height - fb->_Ymax;
241 else
242 cy = fb->_Ymin;
243 cw = fb->_Xmax - fb->_Xmin;
244 ch = fb->_Ymax - fb->_Ymin;
245
246 if (cw == 0 || ch == 0)
247 return;
248
249 GLuint buf;
250 all = (cw == fb->Width && ch == fb->Height);
251
252 intel_prepare_render(intel);
253
254 /* Loop over all renderbuffers */
255 for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
256 const GLbitfield bufBit = 1 << buf;
257 struct intel_renderbuffer *irb;
258 drm_intel_bo *write_buffer;
259 int x1, y1, x2, y2;
260 uint32_t clear_val;
261 uint32_t BR13, CMD;
262 int pitch, cpp;
263 drm_intel_bo *aper_array[2];
264
265 if (!(mask & bufBit))
266 continue;
267
268 /* OK, clear this renderbuffer */
269 irb = intel_get_renderbuffer(fb, buf);
270 write_buffer = intel_region_buffer(intel, irb->region,
271 all ? INTEL_WRITE_FULL :
272 INTEL_WRITE_PART);
273 x1 = cx + irb->region->draw_x;
274 y1 = cy + irb->region->draw_y;
275 x2 = cx + cw + irb->region->draw_x;
276 y2 = cy + ch + irb->region->draw_y;
277
278 pitch = irb->region->pitch;
279 cpp = irb->region->cpp;
280
281 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
282 __FUNCTION__,
283 irb->region->buffer, (pitch * cpp),
284 x1, y1, x2 - x1, y2 - y1);
285
286 BR13 = 0xf0 << 16;
287 CMD = XY_COLOR_BLT_CMD;
288
289 /* Setup the blit command */
290 if (cpp == 4) {
291 BR13 |= BR13_8888;
292 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
293 if (mask & BUFFER_BIT_DEPTH)
294 CMD |= XY_BLT_WRITE_RGB;
295 if (mask & BUFFER_BIT_STENCIL)
296 CMD |= XY_BLT_WRITE_ALPHA;
297 } else {
298 /* clearing RGBA */
299 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
300 }
301 } else {
302 ASSERT(cpp == 2);
303 BR13 |= BR13_565;
304 }
305
306 assert(irb->region->tiling != I915_TILING_Y);
307
308 #ifndef I915
309 if (irb->region->tiling != I915_TILING_NONE) {
310 CMD |= XY_DST_TILED;
311 pitch /= 4;
312 }
313 #endif
314 BR13 |= (pitch * cpp);
315
316 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
317 clear_val = clear_depth;
318 } else {
319 uint8_t clear[4];
320 GLclampf *color = ctx->Color.ClearColor;
321
322 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
323 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
324 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
325 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
326
327 switch (irb->Base.Format) {
328 case MESA_FORMAT_ARGB8888:
329 case MESA_FORMAT_XRGB8888:
330 clear_val = PACK_COLOR_8888(clear[3], clear[0],
331 clear[1], clear[2]);
332 break;
333 case MESA_FORMAT_RGB565:
334 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
335 break;
336 case MESA_FORMAT_ARGB4444:
337 clear_val = PACK_COLOR_4444(clear[3], clear[0],
338 clear[1], clear[2]);
339 break;
340 case MESA_FORMAT_ARGB1555:
341 clear_val = PACK_COLOR_1555(clear[3], clear[0],
342 clear[1], clear[2]);
343 break;
344 default:
345 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
346 irb->Base.Format);
347 clear_val = 0;
348 }
349 }
350
351 assert(x1 < x2);
352 assert(y1 < y2);
353
354 /* do space check before going any further */
355 aper_array[0] = intel->batch->buf;
356 aper_array[1] = write_buffer;
357
358 if (drm_intel_bufmgr_check_aperture_space(aper_array,
359 ARRAY_SIZE(aper_array)) != 0) {
360 intel_batchbuffer_flush(intel->batch);
361 }
362
363 BEGIN_BATCH(6);
364 OUT_BATCH(CMD);
365 OUT_BATCH(BR13);
366 OUT_BATCH((y1 << 16) | x1);
367 OUT_BATCH((y2 << 16) | x2);
368 OUT_RELOC_FENCED(write_buffer,
369 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
370 0);
371 OUT_BATCH(clear_val);
372 ADVANCE_BATCH();
373
374 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
375 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
376 else
377 mask &= ~bufBit; /* turn off bit, for faster loop exit */
378 }
379 }
380
381 GLboolean
382 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
383 GLuint cpp,
384 GLubyte *src_bits, GLuint src_size,
385 GLuint fg_color,
386 GLshort dst_pitch,
387 dri_bo *dst_buffer,
388 GLuint dst_offset,
389 uint32_t dst_tiling,
390 GLshort x, GLshort y,
391 GLshort w, GLshort h,
392 GLenum logic_op)
393 {
394 int dwords = ALIGN(src_size, 8) / 4;
395 uint32_t opcode, br13, blit_cmd;
396
397 /* Blits are in a different ringbuffer so we don't use them. */
398 if (intel->gen >= 6)
399 return GL_FALSE;
400
401 if (dst_tiling != I915_TILING_NONE) {
402 if (dst_offset & 4095)
403 return GL_FALSE;
404 if (dst_tiling == I915_TILING_Y)
405 return GL_FALSE;
406 }
407
408 assert( logic_op - GL_CLEAR >= 0 );
409 assert( logic_op - GL_CLEAR < 0x10 );
410 assert(dst_pitch > 0);
411
412 if (w < 0 || h < 0)
413 return GL_TRUE;
414
415 dst_pitch *= cpp;
416
417 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
418 __FUNCTION__,
419 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
420
421 intel_batchbuffer_require_space( intel->batch,
422 (8 * 4) +
423 (3 * 4) +
424 dwords * 4 );
425
426 opcode = XY_SETUP_BLT_CMD;
427 if (cpp == 4)
428 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
429 #ifndef I915
430 if (dst_tiling != I915_TILING_NONE) {
431 opcode |= XY_DST_TILED;
432 dst_pitch /= 4;
433 }
434 #endif
435
436 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
437 if (cpp == 2)
438 br13 |= BR13_565;
439 else
440 br13 |= BR13_8888;
441
442 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
443 if (dst_tiling != I915_TILING_NONE)
444 blit_cmd |= XY_DST_TILED;
445
446 BEGIN_BATCH(8 + 3);
447 OUT_BATCH(opcode);
448 OUT_BATCH(br13);
449 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
450 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
451 OUT_RELOC_FENCED(dst_buffer,
452 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
453 dst_offset);
454 OUT_BATCH(0); /* bg */
455 OUT_BATCH(fg_color); /* fg */
456 OUT_BATCH(0); /* pattern base addr */
457
458 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
459 OUT_BATCH((y << 16) | x);
460 OUT_BATCH(((y + h) << 16) | (x + w));
461 ADVANCE_BATCH();
462
463 intel_batchbuffer_data( intel->batch,
464 src_bits,
465 dwords * 4 );
466
467 intel_batchbuffer_emit_mi_flush(intel->batch);
468
469 return GL_TRUE;
470 }
471
472 /* We don't have a memmove-type blit like some other hardware, so we'll do a
473 * rectangular blit covering a large space, then emit 1-scanline blit at the
474 * end to cover the last if we need.
475 */
476 void
477 intel_emit_linear_blit(struct intel_context *intel,
478 drm_intel_bo *dst_bo,
479 unsigned int dst_offset,
480 drm_intel_bo *src_bo,
481 unsigned int src_offset,
482 unsigned int size)
483 {
484 GLuint pitch, height;
485 GLboolean ok;
486
487 /* Blits are in a different ringbuffer so we don't use them. */
488 assert(intel->gen < 6);
489
490 /* The pitch is a signed value. */
491 pitch = MIN2(size, (1 << 15) - 1);
492 height = size / pitch;
493 ok = intelEmitCopyBlit(intel, 1,
494 pitch, src_bo, src_offset, I915_TILING_NONE,
495 pitch, dst_bo, dst_offset, I915_TILING_NONE,
496 0, 0, /* src x/y */
497 0, 0, /* dst x/y */
498 pitch, height, /* w, h */
499 GL_COPY);
500 assert(ok);
501
502 src_offset += pitch * height;
503 dst_offset += pitch * height;
504 size -= pitch * height;
505 assert (size < (1 << 15));
506 if (size != 0) {
507 ok = intelEmitCopyBlit(intel, 1,
508 size, src_bo, src_offset, I915_TILING_NONE,
509 size, dst_bo, dst_offset, I915_TILING_NONE,
510 0, 0, /* src x/y */
511 0, 0, /* dst x/y */
512 size, 1, /* w, h */
513 GL_COPY);
514 assert(ok);
515 }
516 }