src/mesa/drivers/dri/intel/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/texformat.h"
  33 #include "main/colormac.h"
  34
  35 #include "intel_blit.h"
  36 #include "intel_buffers.h"
  37 #include "intel_context.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_chipset.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 /**
  47  * Copy the back color buffer to the front color buffer.
  48  * Used for SwapBuffers().
  49  */
  50 void
  51 intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
  52                 const drm_clip_rect_t * rect)
  53 {
  54
  55    struct intel_context *intel;
  56    const intelScreenPrivate *intelScreen;
  57
  58    DBG("%s\n", __FUNCTION__);
  59
  60    assert(dPriv);
  61
  62    intel = intelScreenContext(dPriv->driScreenPriv->private);
  63    if (!intel)
  64       return;
  65
  66    intelScreen = intel->intelScreen;
  67
  68    /* The LOCK_HARDWARE is required for the cliprects.  Buffer offsets
  69     * should work regardless.
  70     */
  71    LOCK_HARDWARE(intel);
  72
  73    if (dPriv && dPriv->numClipRects) {
  74       struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
  75       struct intel_region *src, *dst;
  76       int nbox = dPriv->numClipRects;
  77       drm_clip_rect_t *pbox = dPriv->pClipRects;
  78       int cpp;
  79       int src_pitch, dst_pitch;
  80       unsigned short src_x, src_y;
  81       int BR13, CMD;
  82       int i;
  83       dri_bo *aper_array[3];
  84
  85       src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT);
  86       dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT);
  87
  88       src_pitch = src->pitch * src->cpp;
  89       dst_pitch = dst->pitch * dst->cpp;
  90
  91       cpp = src->cpp;
  92
  93       ASSERT(intel_fb);
  94       ASSERT(intel_fb->Base.Name == 0);    /* Not a user-created FBO */
  95       ASSERT(src);
  96       ASSERT(dst);
  97       ASSERT(src->cpp == dst->cpp);
  98
  99       if (cpp == 2) {
 100          BR13 = (0xCC << 16) | BR13_565;
 101          CMD = XY_SRC_COPY_BLT_CMD;
 102       }
 103       else {
 104          BR13 = (0xCC << 16) | BR13_8888;
 105          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 106       }
 107
 108       assert(src->tiling != I915_TILING_Y);
 109       assert(dst->tiling != I915_TILING_Y);
 110 #ifndef I915
 111       if (src->tiling != I915_TILING_NONE) {
 112          CMD |= XY_SRC_TILED;
 113          src_pitch /= 4;
 114       }
 115       if (dst->tiling != I915_TILING_NONE) {
 116          CMD |= XY_DST_TILED;
 117          dst_pitch /= 4;
 118       }
 119 #endif
 120       /* do space/cliprects check before going any further */
 121       intel_batchbuffer_require_space(intel->batch, 8 * 4,
 122                                       REFERENCES_CLIPRECTS);
 123    again:
 124       aper_array[0] = intel->batch->buf;
 125       aper_array[1] = dst->buffer;
 126       aper_array[2] = src->buffer;
 127
 128       if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 129         intel_batchbuffer_flush(intel->batch);
 130         goto again;
 131       }
 132
 133       for (i = 0; i < nbox; i++, pbox++) {
 134          drm_clip_rect_t box = *pbox;
 135
 136          if (rect) {
 137             if (!intel_intersect_cliprects(&box, &box, rect))
 138                continue;
 139          }
 140
 141          if (box.x1 >= box.x2 ||
 142              box.y1 >= box.y2)
 143             continue;
 144
 145          assert(box.x1 < box.x2);
 146          assert(box.y1 < box.y2);
 147          src_x = box.x1 - dPriv->x + dPriv->backX;
 148          src_y = box.y1 - dPriv->y + dPriv->backY;
 149
 150          BEGIN_BATCH(8, REFERENCES_CLIPRECTS);
 151          OUT_BATCH(CMD);
 152          OUT_BATCH(BR13 | dst_pitch);
 153          OUT_BATCH((box.y1 << 16) | box.x1);
 154          OUT_BATCH((box.y2 << 16) | box.x2);
 155
 156          OUT_RELOC(dst->buffer,
 157                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 158                    0);
 159          OUT_BATCH((src_y << 16) | src_x);
 160          OUT_BATCH(src_pitch);
 161          OUT_RELOC(src->buffer,
 162                    I915_GEM_DOMAIN_RENDER, 0,
 163                    0);
 164          ADVANCE_BATCH();
 165       }
 166
 167       /* Flush the rendering and the batch so that the results all land on the
 168        * screen in a timely fashion.
 169        */
 170       intel_batchbuffer_emit_mi_flush(intel->batch);
 171       intel_batchbuffer_flush(intel->batch);
 172    }
 173
 174    UNLOCK_HARDWARE(intel);
 175 }
 176
 177 static GLuint translate_raster_op(GLenum logicop)
 178 {
 179    switch(logicop) {
 180    case GL_CLEAR: return 0x00;
 181    case GL_AND: return 0x88;
 182    case GL_AND_REVERSE: return 0x44;
 183    case GL_COPY: return 0xCC;
 184    case GL_AND_INVERTED: return 0x22;
 185    case GL_NOOP: return 0xAA;
 186    case GL_XOR: return 0x66;
 187    case GL_OR: return 0xEE;
 188    case GL_NOR: return 0x11;
 189    case GL_EQUIV: return 0x99;
 190    case GL_INVERT: return 0x55;
 191    case GL_OR_REVERSE: return 0xDD;
 192    case GL_COPY_INVERTED: return 0x33;
 193    case GL_OR_INVERTED: return 0xBB;
 194    case GL_NAND: return 0x77;
 195    case GL_SET: return 0xFF;
 196    default: return 0;
 197    }
 198 }
 199
 200
 201 /* Copy BitBlt
 202  */
 203 GLboolean
 204 intelEmitCopyBlit(struct intel_context *intel,
 205                   GLuint cpp,
 206                   GLshort src_pitch,
 207                   dri_bo *src_buffer,
 208                   GLuint src_offset,
 209                   uint32_t src_tiling,
 210                   GLshort dst_pitch,
 211                   dri_bo *dst_buffer,
 212                   GLuint dst_offset,
 213                   uint32_t dst_tiling,
 214                   GLshort src_x, GLshort src_y,
 215                   GLshort dst_x, GLshort dst_y,
 216                   GLshort w, GLshort h,
 217                   GLenum logic_op)
 218 {
 219    GLuint CMD, BR13, pass = 0;
 220    int dst_y2 = dst_y + h;
 221    int dst_x2 = dst_x + w;
 222    dri_bo *aper_array[3];
 223    BATCH_LOCALS;
 224
 225    if (dst_tiling != I915_TILING_NONE) {
 226       if (dst_offset & 4095)
 227          return GL_FALSE;
 228       if (dst_tiling == I915_TILING_Y)
 229          return GL_FALSE;
 230    }
 231    if (src_tiling != I915_TILING_NONE) {
 232       if (src_offset & 4095)
 233          return GL_FALSE;
 234       if (src_tiling == I915_TILING_Y)
 235          return GL_FALSE;
 236    }
 237
 238    /* do space/cliprects check before going any further */
 239    do {
 240        aper_array[0] = intel->batch->buf;
 241        aper_array[1] = dst_buffer;
 242        aper_array[2] = src_buffer;
 243
 244        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 245            intel_batchbuffer_flush(intel->batch);
 246            pass++;
 247        } else
 248            break;
 249    } while (pass < 2);
 250
 251    if (pass >= 2) {
 252        LOCK_HARDWARE(intel);
 253        dri_bo_map(dst_buffer, GL_TRUE);
 254        dri_bo_map(src_buffer, GL_FALSE);
 255        _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
 256                        cpp,
 257                        dst_pitch,
 258                        dst_x, dst_y,
 259                        w, h,
 260                        (GLubyte *)src_buffer->virtual + src_offset,
 261                        src_pitch,
 262                        src_x, src_y);
 263
 264        dri_bo_unmap(src_buffer);
 265        dri_bo_unmap(dst_buffer);
 266        UNLOCK_HARDWARE(intel);
 267
 268        return GL_TRUE;
 269    }
 270
 271    intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS);
 272    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 273        __FUNCTION__,
 274        src_buffer, src_pitch, src_offset, src_x, src_y,
 275        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 276
 277    src_pitch *= cpp;
 278    dst_pitch *= cpp;
 279
 280    BR13 = translate_raster_op(logic_op) << 16;
 281
 282    switch (cpp) {
 283    case 1:
 284       CMD = XY_SRC_COPY_BLT_CMD;
 285       break;
 286    case 2:
 287       BR13 |= BR13_565;
 288       CMD = XY_SRC_COPY_BLT_CMD;
 289       break;
 290    case 4:
 291       BR13 |= BR13_8888;
 292       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 293       break;
 294    default:
 295       return GL_FALSE;
 296    }
 297
 298 #ifndef I915
 299    if (dst_tiling != I915_TILING_NONE) {
 300       CMD |= XY_DST_TILED;
 301       dst_pitch /= 4;
 302    }
 303    if (src_tiling != I915_TILING_NONE) {
 304       CMD |= XY_SRC_TILED;
 305       src_pitch /= 4;
 306    }
 307 #endif
 308
 309    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 310       return GL_TRUE;
 311    }
 312
 313    assert(dst_x < dst_x2);
 314    assert(dst_y < dst_y2);
 315
 316    BEGIN_BATCH(8, NO_LOOP_CLIPRECTS);
 317    OUT_BATCH(CMD);
 318    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 319    OUT_BATCH((dst_y << 16) | dst_x);
 320    OUT_BATCH((dst_y2 << 16) | dst_x2);
 321    OUT_RELOC(dst_buffer,
 322              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 323              dst_offset);
 324    OUT_BATCH((src_y << 16) | src_x);
 325    OUT_BATCH((uint16_t)src_pitch);
 326    OUT_RELOC(src_buffer,
 327              I915_GEM_DOMAIN_RENDER, 0,
 328              src_offset);
 329    ADVANCE_BATCH();
 330
 331    intel_batchbuffer_emit_mi_flush(intel->batch);
 332
 333    return GL_TRUE;
 334 }
 335
 336
 337 /**
 338  * Use blitting to clear the renderbuffers named by 'flags'.
 339  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 340  * since that might include software renderbuffers or renderbuffers
 341  * which we're clearing with triangles.
 342  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 343  */
 344 void
 345 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
 346 {
 347    struct intel_context *intel = intel_context(ctx);
 348    struct gl_framebuffer *fb = ctx->DrawBuffer;
 349    GLuint clear_depth;
 350    GLbitfield skipBuffers = 0;
 351    unsigned int num_cliprects;
 352    struct drm_clip_rect *cliprects;
 353    int x_off, y_off;
 354    BATCH_LOCALS;
 355
 356    /*
 357     * Compute values for clearing the buffers.
 358     */
 359    clear_depth = 0;
 360    if (mask & BUFFER_BIT_DEPTH) {
 361       clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 362    }
 363    if (mask & BUFFER_BIT_STENCIL) {
 364       clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
 365    }
 366
 367    /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in
 368     * the loop below.
 369     */
 370    if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) {
 371       skipBuffers = BUFFER_BIT_STENCIL;
 372    }
 373
 374    LOCK_HARDWARE(intel);
 375
 376    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 377    if (num_cliprects) {
 378       GLint cx, cy, cw, ch;
 379       drm_clip_rect_t clear;
 380       int i;
 381
 382       /* Get clear bounds after locking */
 383       cx = fb->_Xmin;
 384       cy = fb->_Ymin;
 385       cw = fb->_Xmax - cx;
 386       ch = fb->_Ymax - cy;
 387
 388       if (fb->Name == 0) {
 389          /* clearing a window */
 390
 391          /* flip top to bottom */
 392          clear.x1 = cx + x_off;
 393          clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch;
 394          clear.x2 = clear.x1 + cw;
 395          clear.y2 = clear.y1 + ch;
 396       }
 397       else {
 398          /* clearing FBO */
 399          assert(num_cliprects == 1);
 400          assert(cliprects == &intel->fboRect);
 401          clear.x1 = cx;
 402          clear.y1 = cy;
 403          clear.x2 = clear.x1 + cw;
 404          clear.y2 = clear.y1 + ch;
 405          /* no change to mask */
 406       }
 407
 408       for (i = 0; i < num_cliprects; i++) {
 409          const drm_clip_rect_t *box = &cliprects[i];
 410          drm_clip_rect_t b;
 411          GLuint buf;
 412          GLuint clearMask = mask;      /* use copy, since we modify it below */
 413          GLboolean all = (cw == fb->Width && ch == fb->Height);
 414
 415          if (!all) {
 416             intel_intersect_cliprects(&b, &clear, box);
 417          }
 418          else {
 419             b = *box;
 420          }
 421
 422          if (b.x1 >= b.x2 || b.y1 >= b.y2)
 423             continue;
 424
 425          if (0)
 426             _mesa_printf("clear %d,%d..%d,%d, mask %x\n",
 427                          b.x1, b.y1, b.x2, b.y2, mask);
 428
 429          /* Loop over all renderbuffers */
 430          for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) {
 431             const GLbitfield bufBit = 1 << buf;
 432             if ((clearMask & bufBit) && !(bufBit & skipBuffers)) {
 433                /* OK, clear this renderbuffer */
 434                struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, buf);
 435                dri_bo *write_buffer =
 436                   intel_region_buffer(intel, irb->region,
 437                                       all ? INTEL_WRITE_FULL :
 438                                       INTEL_WRITE_PART);
 439
 440                GLuint clearVal;
 441                GLint pitch, cpp;
 442                GLuint BR13, CMD;
 443
 444                pitch = irb->region->pitch;
 445                cpp = irb->region->cpp;
 446
 447                DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 448                    __FUNCTION__,
 449                    irb->region->buffer, (pitch * cpp),
 450                    irb->region->draw_offset,
 451                    b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1);
 452
 453                BR13 = 0xf0 << 16;
 454                CMD = XY_COLOR_BLT_CMD;
 455
 456                /* Setup the blit command */
 457                if (cpp == 4) {
 458                   BR13 |= BR13_8888;
 459                   if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 460                      if (clearMask & BUFFER_BIT_DEPTH)
 461                         CMD |= XY_BLT_WRITE_RGB;
 462                      if (clearMask & BUFFER_BIT_STENCIL)
 463                         CMD |= XY_BLT_WRITE_ALPHA;
 464                   }
 465                   else {
 466                      /* clearing RGBA */
 467                      CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 468                   }
 469                }
 470                else {
 471                   ASSERT(cpp == 2);
 472                   BR13 |= BR13_565;
 473                }
 474
 475                assert(irb->region->tiling != I915_TILING_Y);
 476
 477 #ifndef I915
 478                if (irb->region->tiling != I915_TILING_NONE) {
 479                   CMD |= XY_DST_TILED;
 480                   pitch /= 4;
 481                }
 482 #endif
 483                BR13 |= (pitch * cpp);
 484
 485                if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
 486                   clearVal = clear_depth;
 487                }
 488                else {
 489                   uint8_t clear[4];
 490                   GLclampf *color = ctx->Color.ClearColor;
 491
 492                   CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
 493                   CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
 494                   CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
 495                   CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
 496
 497                   switch (irb->texformat->MesaFormat) {
 498                   case MESA_FORMAT_ARGB8888:
 499                      clearVal = intel->ClearColor8888;
 500                      break;
 501                   case MESA_FORMAT_RGB565:
 502                      clearVal = intel->ClearColor565;
 503                      break;
 504                   case MESA_FORMAT_ARGB4444:
 505                      clearVal = PACK_COLOR_4444(clear[3], clear[0],
 506                                                 clear[1], clear[2]);
 507                      break;
 508                   case MESA_FORMAT_ARGB1555:
 509                      clearVal = PACK_COLOR_1555(clear[3], clear[0],
 510                                                 clear[1], clear[2]);
 511                      break;
 512                   default:
 513                      _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
 514                                    irb->texformat->MesaFormat);
 515                      clearVal = 0;
 516                   }
 517                }
 518
 519                /*
 520                   _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
 521                   buf, irb->Base.Name);
 522                 */
 523
 524                assert(b.x1 < b.x2);
 525                assert(b.y1 < b.y2);
 526
 527                BEGIN_BATCH(6, REFERENCES_CLIPRECTS);
 528                OUT_BATCH(CMD);
 529                OUT_BATCH(BR13);
 530                OUT_BATCH((b.y1 << 16) | b.x1);
 531                OUT_BATCH((b.y2 << 16) | b.x2);
 532                OUT_RELOC(write_buffer,
 533                          I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 534                          irb->region->draw_offset);
 535                OUT_BATCH(clearVal);
 536                ADVANCE_BATCH();
 537                clearMask &= ~bufBit;    /* turn off bit, for faster loop exit */
 538             }
 539          }
 540       }
 541    }
 542
 543    UNLOCK_HARDWARE(intel);
 544 }
 545
 546 GLboolean
 547 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 548                                   GLuint cpp,
 549                                   GLubyte *src_bits, GLuint src_size,
 550                                   GLuint fg_color,
 551                                   GLshort dst_pitch,
 552                                   dri_bo *dst_buffer,
 553                                   GLuint dst_offset,
 554                                   uint32_t dst_tiling,
 555                                   GLshort x, GLshort y,
 556                                   GLshort w, GLshort h,
 557                                   GLenum logic_op)
 558 {
 559    int dwords = ALIGN(src_size, 8) / 4;
 560    uint32_t opcode, br13, blit_cmd;
 561
 562    if (dst_tiling != I915_TILING_NONE) {
 563       if (dst_offset & 4095)
 564          return GL_FALSE;
 565       if (dst_tiling == I915_TILING_Y)
 566          return GL_FALSE;
 567    }
 568
 569    assert( logic_op - GL_CLEAR >= 0 );
 570    assert( logic_op - GL_CLEAR < 0x10 );
 571    assert(dst_pitch > 0);
 572
 573    if (w < 0 || h < 0)
 574       return GL_TRUE;
 575
 576    dst_pitch *= cpp;
 577
 578    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 579        __FUNCTION__,
 580        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 581
 582    intel_batchbuffer_require_space( intel->batch,
 583                                     (8 * 4) +
 584                                     (3 * 4) +
 585                                     dwords * 4,
 586                                     REFERENCES_CLIPRECTS );
 587
 588    opcode = XY_SETUP_BLT_CMD;
 589    if (cpp == 4)
 590       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 591 #ifndef I915
 592    if (dst_tiling != I915_TILING_NONE) {
 593       opcode |= XY_DST_TILED;
 594       dst_pitch /= 4;
 595    }
 596 #endif
 597
 598    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 599    if (cpp == 2)
 600       br13 |= BR13_565;
 601    else
 602       br13 |= BR13_8888;
 603
 604    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 605    if (dst_tiling != I915_TILING_NONE)
 606       blit_cmd |= XY_DST_TILED;
 607
 608    BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
 609    OUT_BATCH(opcode);
 610    OUT_BATCH(br13);
 611    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 612    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 613    OUT_RELOC(dst_buffer,
 614              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 615              dst_offset);
 616    OUT_BATCH(0); /* bg */
 617    OUT_BATCH(fg_color); /* fg */
 618    OUT_BATCH(0); /* pattern base addr */
 619
 620    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 621    OUT_BATCH((y << 16) | x);
 622    OUT_BATCH(((y + h) << 16) | (x + w));
 623    ADVANCE_BATCH();
 624
 625    intel_batchbuffer_data( intel->batch,
 626                            src_bits,
 627                            dwords * 4,
 628                            REFERENCES_CLIPRECTS );
 629
 630    intel_batchbuffer_emit_mi_flush(intel->batch);
 631
 632    return GL_TRUE;
 633 }
 634
 635 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 636  * rectangular blit covering a large space, then emit 1-scanline blit at the
 637  * end to cover the last if we need.
 638  */
 639 void
 640 intel_emit_linear_blit(struct intel_context *intel,
 641                        drm_intel_bo *dst_bo,
 642                        unsigned int dst_offset,
 643                        drm_intel_bo *src_bo,
 644                        unsigned int src_offset,
 645                        unsigned int size)
 646 {
 647    GLuint pitch, height;
 648
 649    /* The pitch is a signed value. */
 650    pitch = MIN2(size, (1 << 15) - 1);
 651    height = size / pitch;
 652    intelEmitCopyBlit(intel, 1,
 653                      pitch, src_bo, src_offset, I915_TILING_NONE,
 654                      pitch, dst_bo, dst_offset, I915_TILING_NONE,
 655                      0, 0, /* src x/y */
 656                      0, 0, /* dst x/y */
 657                      pitch, height, /* w, h */
 658                      GL_COPY);
 659
 660    src_offset += pitch * height;
 661    dst_offset += pitch * height;
 662    size -= pitch * height;
 663    assert (size < (1 << 15));
 664    if (size != 0) {
 665       intelEmitCopyBlit(intel, 1,
 666                         size, src_bo, src_offset, I915_TILING_NONE,
 667                         size, dst_bo, dst_offset, I915_TILING_NONE,
 668                         0, 0, /* src x/y */
 669                         0, 0, /* dst x/y */
 670                         size, 1, /* w, h */
 671                         GL_COPY);
 672    }
 673 }