src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32
  33 #include "intel_buffers.h"
  34 #include "intel_fbo.h"
  35 #include "intel_screen.h"
  36 #include "intel_span.h"
  37 #include "intel_regions.h"
  38 #include "intel_tex.h"
  39
  40 #include "swrast/swrast.h"
  41
  42 static void
  43 intel_set_span_functions(struct intel_context *intel,
  44                          struct gl_renderbuffer *rb);
  45
  46 #define SPAN_CACHE_SIZE         4096
  47
  48 static void
  49 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  50 {
  51    if (irb->span_cache == NULL) {
  52       irb->span_cache = malloc(SPAN_CACHE_SIZE);
  53       irb->span_cache_offset = -1;
  54    }
  55
  56    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  57       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  58       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  59                          SPAN_CACHE_SIZE, irb->span_cache);
  60    }
  61 }
  62
  63 static void
  64 clear_span_cache(struct intel_renderbuffer *irb)
  65 {
  66    irb->span_cache_offset = -1;
  67 }
  68
  69 static uint32_t
  70 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  71 {
  72    get_span_cache(irb, offset);
  73
  74    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  75 }
  76
  77 static uint32_t
  78 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  79 {
  80    get_span_cache(irb, offset);
  81
  82    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  83       0xff000000;
  84 }
  85
  86 static uint16_t
  87 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  88 {
  89    get_span_cache(irb, offset);
  90
  91    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  92 }
  93
  94 static uint8_t
  95 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  96 {
  97    get_span_cache(irb, offset);
  98
  99    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 100 }
 101
 102 static void
 103 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 104 {
 105    clear_span_cache(irb);
 106
 107    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 108 }
 109
 110 static void
 111 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 112 {
 113    clear_span_cache(irb);
 114
 115    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 116 }
 117
 118 static void
 119 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 120 {
 121    clear_span_cache(irb);
 122
 123    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 124 }
 125
 126 static void
 127 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 128 {
 129    clear_span_cache(irb);
 130
 131    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 132 }
 133
 134 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 135                                 int x, int y)
 136 {
 137         return (y * irb->region->pitch + x) * irb->region->cpp;
 138 }
 139
 140 /*
 141  * Deal with tiled surfaces
 142  */
 143
 144 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 145                                int x, int y)
 146 {
 147         int     tile_stride;
 148         int     xbyte;
 149         int     x_tile_off, y_tile_off;
 150         int     x_tile_number, y_tile_number;
 151         int     tile_off, tile_base;
 152
 153         x += irb->region->draw_x;
 154         y += irb->region->draw_y;
 155
 156         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 157
 158         xbyte = x * irb->region->cpp;
 159
 160         x_tile_off = xbyte & 0x1ff;
 161         y_tile_off = y & 7;
 162
 163         x_tile_number = xbyte >> 9;
 164         y_tile_number = y >> 3;
 165
 166         tile_off = (y_tile_off << 9) + x_tile_off;
 167
 168         switch (irb->region->bit_6_swizzle) {
 169         case I915_BIT_6_SWIZZLE_NONE:
 170            break;
 171         case I915_BIT_6_SWIZZLE_9:
 172            tile_off ^= ((tile_off >> 3) & 64);
 173            break;
 174         case I915_BIT_6_SWIZZLE_9_10:
 175            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 176            break;
 177         case I915_BIT_6_SWIZZLE_9_11:
 178            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 179            break;
 180         case I915_BIT_6_SWIZZLE_9_10_11:
 181            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 182               ((tile_off >> 5) & 64);
 183            break;
 184         default:
 185            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 186                    irb->region->bit_6_swizzle);
 187            exit(1);
 188         }
 189
 190         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 191
 192 #if 0
 193         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 194                x, y, tile_off, tile_base,
 195                tile_off + tile_base,
 196                irb->region->pitch, tile_stride);
 197 #endif
 198
 199         return tile_base + tile_off;
 200 }
 201
 202 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 203                                int x, int y)
 204 {
 205         int     tile_stride;
 206         int     xbyte;
 207         int     x_tile_off, y_tile_off;
 208         int     x_tile_number, y_tile_number;
 209         int     tile_off, tile_base;
 210
 211         x += irb->region->draw_x;
 212         y += irb->region->draw_y;
 213
 214         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 215
 216         xbyte = x * irb->region->cpp;
 217
 218         x_tile_off = xbyte & 0x7f;
 219         y_tile_off = y & 0x1f;
 220
 221         x_tile_number = xbyte >> 7;
 222         y_tile_number = y >> 5;
 223
 224         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 225            (x_tile_off & 0xf);
 226
 227         switch (irb->region->bit_6_swizzle) {
 228         case I915_BIT_6_SWIZZLE_NONE:
 229            break;
 230         case I915_BIT_6_SWIZZLE_9:
 231            tile_off ^= ((tile_off >> 3) & 64);
 232            break;
 233         case I915_BIT_6_SWIZZLE_9_10:
 234            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 235            break;
 236         case I915_BIT_6_SWIZZLE_9_11:
 237            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 238            break;
 239         case I915_BIT_6_SWIZZLE_9_10_11:
 240            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 241               ((tile_off >> 5) & 64);
 242            break;
 243         default:
 244            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 245                    irb->region->bit_6_swizzle);
 246            exit(1);
 247         }
 248
 249         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 250
 251         return tile_base + tile_off;
 252 }
 253
 254 /*
 255   break intelWriteRGBASpan_ARGB8888
 256 */
 257
 258 #undef DBG
 259 #define DBG 0
 260
 261 #define LOCAL_VARS                                                      \
 262    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 263    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 264    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 265    int minx = 0, miny = 0;                                              \
 266    int maxx = ctx->DrawBuffer->Width;                                   \
 267    int maxy = ctx->DrawBuffer->Height;                                  \
 268    int pitch = irb->region->pitch * irb->region->cpp;                   \
 269    void *buf = irb->region->buffer->virtual;                            \
 270    GLuint p;                                                            \
 271    (void) p;                                                            \
 272    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 273
 274 #define HW_CLIPLOOP()
 275 #define HW_ENDCLIPLOOP()
 276
 277 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 278
 279 #define HW_LOCK()
 280
 281 #define HW_UNLOCK()
 282
 283 /* Convenience macros to avoid typing the swizzle argument over and over */
 284 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X), (_Y))
 285 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X), (_Y))
 286 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X), (_Y))
 287
 288 /* r5g6b5 color span and pixel functions */
 289 #define INTEL_PIXEL_FMT GL_RGB
 290 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 291 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 292 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 293 #define INTEL_TAG(x) x##_RGB565
 294 #include "intel_spantmp.h"
 295
 296 /* a4r4g4b4 color span and pixel functions */
 297 #define INTEL_PIXEL_FMT GL_BGRA
 298 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 299 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 300 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 301 #define INTEL_TAG(x) x##_ARGB4444
 302 #include "intel_spantmp.h"
 303
 304 /* a1r5g5b5 color span and pixel functions */
 305 #define INTEL_PIXEL_FMT GL_BGRA
 306 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 307 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 308 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 309 #define INTEL_TAG(x) x##_ARGB1555
 310 #include "intel_spantmp.h"
 311
 312 /* a8r8g8b8 color span and pixel functions */
 313 #define INTEL_PIXEL_FMT GL_BGRA
 314 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 315 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 316 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 317 #define INTEL_TAG(x) x##_ARGB8888
 318 #include "intel_spantmp.h"
 319
 320 /* x8r8g8b8 color span and pixel functions */
 321 #define INTEL_PIXEL_FMT GL_BGR
 322 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 323 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 324 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 325 #define INTEL_TAG(x) x##_xRGB8888
 326 #include "intel_spantmp.h"
 327
 328 #define LOCAL_DEPTH_VARS                                                \
 329    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 330    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 331    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 332    int minx = 0, miny = 0;                                              \
 333    int maxx = ctx->DrawBuffer->Width;                                   \
 334    int maxy = ctx->DrawBuffer->Height;                                  \
 335    int pitch = irb->region->pitch * irb->region->cpp;                   \
 336    void *buf = irb->region->buffer->virtual;                            \
 337    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 338
 339 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 340
 341 /* z16 depthbuffer functions. */
 342 #define INTEL_VALUE_TYPE GLushort
 343 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 344 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 345 #define INTEL_TAG(name) name##_z16
 346 #include "intel_depthtmp.h"
 347
 348 /* z24x8 depthbuffer functions. */
 349 #define INTEL_VALUE_TYPE GLuint
 350 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 351 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 352 #define INTEL_TAG(name) name##_z24_x8
 353 #include "intel_depthtmp.h"
 354
 355 void
 356 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 357 {
 358    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 359
 360    if (irb == NULL || irb->region == NULL)
 361       return;
 362
 363    if (intel->intelScreen->kernel_exec_fencing)
 364       drm_intel_gem_bo_map_gtt(irb->region->buffer);
 365
 366    intel_set_span_functions(intel, rb);
 367 }
 368
 369 void
 370 intel_renderbuffer_unmap(struct intel_context *intel,
 371                          struct gl_renderbuffer *rb)
 372 {
 373    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 374
 375    if (irb == NULL || irb->region == NULL)
 376       return;
 377
 378    if (intel->intelScreen->kernel_exec_fencing)
 379       drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
 380    else
 381       clear_span_cache(irb);
 382
 383    rb->GetRow = NULL;
 384    rb->PutRow = NULL;
 385 }
 386
 387 /**
 388  * Map or unmap all the renderbuffers which we may need during
 389  * software rendering.
 390  * XXX in the future, we could probably convey extra information to
 391  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 392  * from the depth buffer, we really only need one mapping.
 393  *
 394  * XXX Rewrite this function someday.
 395  * We can probably just loop over all the renderbuffer attachments,
 396  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 397  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 398  */
 399 static void
 400 intel_map_unmap_framebuffer(struct intel_context *intel,
 401                             struct gl_framebuffer *fb,
 402                             GLboolean map)
 403 {
 404    GLuint i;
 405
 406    /* color draw buffers */
 407    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 408       if (map)
 409          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 410       else
 411          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 412    }
 413
 414    /* color read buffer */
 415    if (map)
 416       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 417    else
 418       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 419
 420    /* check for render to textures */
 421    for (i = 0; i < BUFFER_COUNT; i++) {
 422       struct gl_renderbuffer_attachment *att =
 423          fb->Attachment + i;
 424       struct gl_texture_object *tex = att->Texture;
 425       if (tex) {
 426          /* render to texture */
 427          ASSERT(att->Renderbuffer);
 428          if (map)
 429             intel_tex_map_images(intel, intel_texture_object(tex));
 430          else
 431             intel_tex_unmap_images(intel, intel_texture_object(tex));
 432       }
 433    }
 434
 435    /* depth buffer (Note wrapper!) */
 436    if (fb->_DepthBuffer) {
 437       if (map)
 438          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 439       else
 440          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 441    }
 442
 443    /* stencil buffer (Note wrapper!) */
 444    if (fb->_StencilBuffer) {
 445       if (map)
 446          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 447       else
 448          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 449    }
 450
 451    intel_check_front_buffer_rendering(intel);
 452 }
 453
 454 /**
 455  * Prepare for software rendering.  Map current read/draw framebuffers'
 456  * renderbuffes and all currently bound texture objects.
 457  *
 458  * Old note: Moved locking out to get reasonable span performance.
 459  */
 460 void
 461 intelSpanRenderStart(GLcontext * ctx)
 462 {
 463    struct intel_context *intel = intel_context(ctx);
 464    GLuint i;
 465
 466    intelFlush(&intel->ctx);
 467    intel_prepare_render(intel);
 468
 469    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 470       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 471          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 472          intel_tex_map_images(intel, intel_texture_object(texObj));
 473       }
 474    }
 475
 476    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 477    if (ctx->ReadBuffer != ctx->DrawBuffer)
 478       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 479 }
 480
 481 /**
 482  * Called when done software rendering.  Unmap the buffers we mapped in
 483  * the above function.
 484  */
 485 void
 486 intelSpanRenderFinish(GLcontext * ctx)
 487 {
 488    struct intel_context *intel = intel_context(ctx);
 489    GLuint i;
 490
 491    _swrast_flush(ctx);
 492
 493    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 494       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 495          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 496          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 497       }
 498    }
 499
 500    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 501    if (ctx->ReadBuffer != ctx->DrawBuffer)
 502       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 503 }
 504
 505
 506 void
 507 intelInitSpanFuncs(GLcontext * ctx)
 508 {
 509    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 510    swdd->SpanRenderStart = intelSpanRenderStart;
 511    swdd->SpanRenderFinish = intelSpanRenderFinish;
 512 }
 513
 514 void
 515 intel_map_vertex_shader_textures(GLcontext *ctx)
 516 {
 517    struct intel_context *intel = intel_context(ctx);
 518    int i;
 519
 520    if (ctx->VertexProgram._Current == NULL)
 521       return;
 522
 523    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 524       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 525           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 526          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 527
 528          intel_tex_map_images(intel, intel_texture_object(texObj));
 529       }
 530    }
 531 }
 532
 533 void
 534 intel_unmap_vertex_shader_textures(GLcontext *ctx)
 535 {
 536    struct intel_context *intel = intel_context(ctx);
 537    int i;
 538
 539    if (ctx->VertexProgram._Current == NULL)
 540       return;
 541
 542    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 543       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 544           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 545          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 546
 547          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 548       }
 549    }
 550 }
 551
 552 /**
 553  * Plug in appropriate span read/write functions for the given renderbuffer.
 554  * These are used for the software fallbacks.
 555  */
 556 static void
 557 intel_set_span_functions(struct intel_context *intel,
 558                          struct gl_renderbuffer *rb)
 559 {
 560    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 561    uint32_t tiling = irb->region->tiling;
 562
 563    if (intel->intelScreen->kernel_exec_fencing) {
 564       switch (irb->Base.Format) {
 565       case MESA_FORMAT_RGB565:
 566          intel_gttmap_InitPointers_RGB565(rb);
 567          break;
 568       case MESA_FORMAT_ARGB4444:
 569          intel_gttmap_InitPointers_ARGB4444(rb);
 570          break;
 571       case MESA_FORMAT_ARGB1555:
 572          intel_gttmap_InitPointers_ARGB1555(rb);
 573          break;
 574       case MESA_FORMAT_XRGB8888:
 575          intel_gttmap_InitPointers_xRGB8888(rb);
 576          break;
 577       case MESA_FORMAT_ARGB8888:
 578          intel_gttmap_InitPointers_ARGB8888(rb);
 579          break;
 580       case MESA_FORMAT_Z16:
 581          intel_gttmap_InitDepthPointers_z16(rb);
 582          break;
 583       case MESA_FORMAT_X8_Z24:
 584       case MESA_FORMAT_S8_Z24:
 585          intel_gttmap_InitDepthPointers_z24_x8(rb);
 586          break;
 587       default:
 588          _mesa_problem(NULL,
 589                        "Unexpected MesaFormat %d in intelSetSpanFunctions",
 590                        irb->Base.Format);
 591          break;
 592       }
 593       return;
 594    }
 595
 596    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 597     * instead of the fence registers handling it.
 598     */
 599    switch (irb->Base.Format) {
 600    case MESA_FORMAT_RGB565:
 601       switch (tiling) {
 602       case I915_TILING_NONE:
 603       default:
 604          intelInitPointers_RGB565(rb);
 605          break;
 606       case I915_TILING_X:
 607          intel_XTile_InitPointers_RGB565(rb);
 608          break;
 609       case I915_TILING_Y:
 610          intel_YTile_InitPointers_RGB565(rb);
 611          break;
 612       }
 613       break;
 614    case MESA_FORMAT_ARGB4444:
 615       switch (tiling) {
 616       case I915_TILING_NONE:
 617       default:
 618          intelInitPointers_ARGB4444(rb);
 619          break;
 620       case I915_TILING_X:
 621          intel_XTile_InitPointers_ARGB4444(rb);
 622          break;
 623       case I915_TILING_Y:
 624          intel_YTile_InitPointers_ARGB4444(rb);
 625          break;
 626       }
 627       break;
 628    case MESA_FORMAT_ARGB1555:
 629       switch (tiling) {
 630       case I915_TILING_NONE:
 631       default:
 632          intelInitPointers_ARGB1555(rb);
 633          break;
 634       case I915_TILING_X:
 635          intel_XTile_InitPointers_ARGB1555(rb);
 636          break;
 637       case I915_TILING_Y:
 638          intel_YTile_InitPointers_ARGB1555(rb);
 639          break;
 640       }
 641       break;
 642    case MESA_FORMAT_XRGB8888:
 643       switch (tiling) {
 644       case I915_TILING_NONE:
 645       default:
 646          intelInitPointers_xRGB8888(rb);
 647          break;
 648       case I915_TILING_X:
 649          intel_XTile_InitPointers_xRGB8888(rb);
 650          break;
 651       case I915_TILING_Y:
 652          intel_YTile_InitPointers_xRGB8888(rb);
 653          break;
 654       }
 655       break;
 656    case MESA_FORMAT_ARGB8888:
 657       /* 8888 RGBA */
 658       switch (tiling) {
 659       case I915_TILING_NONE:
 660       default:
 661          intelInitPointers_ARGB8888(rb);
 662          break;
 663       case I915_TILING_X:
 664          intel_XTile_InitPointers_ARGB8888(rb);
 665          break;
 666       case I915_TILING_Y:
 667          intel_YTile_InitPointers_ARGB8888(rb);
 668          break;
 669       }
 670       break;
 671    case MESA_FORMAT_Z16:
 672       switch (tiling) {
 673       case I915_TILING_NONE:
 674       default:
 675          intelInitDepthPointers_z16(rb);
 676          break;
 677       case I915_TILING_X:
 678          intel_XTile_InitDepthPointers_z16(rb);
 679          break;
 680       case I915_TILING_Y:
 681          intel_YTile_InitDepthPointers_z16(rb);
 682          break;
 683       }
 684       break;
 685    case MESA_FORMAT_X8_Z24:
 686    case MESA_FORMAT_S8_Z24:
 687       /* There are a few different ways SW asks us to access the S8Z24 data:
 688        * Z24 depth-only depth reads
 689        * S8Z24 depth reads
 690        * S8Z24 stencil reads.
 691        */
 692       if (rb->Format == MESA_FORMAT_S8_Z24) {
 693          switch (tiling) {
 694          case I915_TILING_NONE:
 695          default:
 696             intelInitDepthPointers_z24_x8(rb);
 697             break;
 698          case I915_TILING_X:
 699             intel_XTile_InitDepthPointers_z24_x8(rb);
 700             break;
 701          case I915_TILING_Y:
 702             intel_YTile_InitDepthPointers_z24_x8(rb);
 703             break;
 704          }
 705       } else {
 706          _mesa_problem(NULL,
 707                        "Unexpected ActualFormat in intelSetSpanFunctions");
 708       }
 709       break;
 710    default:
 711       _mesa_problem(NULL,
 712                     "Unexpected MesaFormat in intelSetSpanFunctions");
 713       break;
 714    }
 715 }