src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32
  33 #include "intel_buffers.h"
  34 #include "intel_fbo.h"
  35 #include "intel_screen.h"
  36 #include "intel_span.h"
  37 #include "intel_regions.h"
  38 #include "intel_tex.h"
  39
  40 #include "swrast/swrast.h"
  41
  42 static void
  43 intel_set_span_functions(struct intel_context *intel,
  44                          struct gl_renderbuffer *rb);
  45
  46 #define SPAN_CACHE_SIZE         4096
  47
  48 static void
  49 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  50 {
  51    if (irb->span_cache == NULL) {
  52       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  53       irb->span_cache_offset = -1;
  54    }
  55
  56    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  57       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  58       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  59                          SPAN_CACHE_SIZE, irb->span_cache);
  60    }
  61 }
  62
  63 static void
  64 clear_span_cache(struct intel_renderbuffer *irb)
  65 {
  66    irb->span_cache_offset = -1;
  67 }
  68
  69 static uint32_t
  70 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  71 {
  72    get_span_cache(irb, offset);
  73
  74    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  75 }
  76
  77 static uint32_t
  78 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  79 {
  80    get_span_cache(irb, offset);
  81
  82    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  83       0xff000000;
  84 }
  85
  86 static uint16_t
  87 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  88 {
  89    get_span_cache(irb, offset);
  90
  91    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  92 }
  93
  94 static uint8_t
  95 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  96 {
  97    get_span_cache(irb, offset);
  98
  99    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 100 }
 101
 102 static void
 103 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 104 {
 105    clear_span_cache(irb);
 106
 107    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 108 }
 109
 110 static void
 111 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 112 {
 113    clear_span_cache(irb);
 114
 115    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 116 }
 117
 118 static void
 119 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 120 {
 121    clear_span_cache(irb);
 122
 123    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 124 }
 125
 126 static void
 127 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 128 {
 129    clear_span_cache(irb);
 130
 131    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 132 }
 133
 134 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 135                                 int x, int y)
 136 {
 137         return (y * irb->region->pitch + x) * irb->region->cpp;
 138 }
 139
 140 /*
 141  * Deal with tiled surfaces
 142  */
 143
 144 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 145                                int x, int y)
 146 {
 147         int     tile_stride;
 148         int     xbyte;
 149         int     x_tile_off, y_tile_off;
 150         int     x_tile_number, y_tile_number;
 151         int     tile_off, tile_base;
 152
 153         x += irb->region->draw_x;
 154         y += irb->region->draw_y;
 155
 156         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 157
 158         xbyte = x * irb->region->cpp;
 159
 160         x_tile_off = xbyte & 0x1ff;
 161         y_tile_off = y & 7;
 162
 163         x_tile_number = xbyte >> 9;
 164         y_tile_number = y >> 3;
 165
 166         tile_off = (y_tile_off << 9) + x_tile_off;
 167
 168         switch (irb->region->bit_6_swizzle) {
 169         case I915_BIT_6_SWIZZLE_NONE:
 170            break;
 171         case I915_BIT_6_SWIZZLE_9:
 172            tile_off ^= ((tile_off >> 3) & 64);
 173            break;
 174         case I915_BIT_6_SWIZZLE_9_10:
 175            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 176            break;
 177         case I915_BIT_6_SWIZZLE_9_11:
 178            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 179            break;
 180         case I915_BIT_6_SWIZZLE_9_10_11:
 181            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 182               ((tile_off >> 5) & 64);
 183            break;
 184         default:
 185            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 186                    irb->region->bit_6_swizzle);
 187            exit(1);
 188         }
 189
 190         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 191
 192 #if 0
 193         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 194                x, y, tile_off, tile_base,
 195                tile_off + tile_base,
 196                irb->region->pitch, tile_stride);
 197 #endif
 198
 199         return tile_base + tile_off;
 200 }
 201
 202 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 203                                int x, int y)
 204 {
 205         int     tile_stride;
 206         int     xbyte;
 207         int     x_tile_off, y_tile_off;
 208         int     x_tile_number, y_tile_number;
 209         int     tile_off, tile_base;
 210
 211         x += irb->region->draw_x;
 212         y += irb->region->draw_y;
 213
 214         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 215
 216         xbyte = x * irb->region->cpp;
 217
 218         x_tile_off = xbyte & 0x7f;
 219         y_tile_off = y & 0x1f;
 220
 221         x_tile_number = xbyte >> 7;
 222         y_tile_number = y >> 5;
 223
 224         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 225            (x_tile_off & 0xf);
 226
 227         switch (irb->region->bit_6_swizzle) {
 228         case I915_BIT_6_SWIZZLE_NONE:
 229            break;
 230         case I915_BIT_6_SWIZZLE_9:
 231            tile_off ^= ((tile_off >> 3) & 64);
 232            break;
 233         case I915_BIT_6_SWIZZLE_9_10:
 234            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 235            break;
 236         case I915_BIT_6_SWIZZLE_9_11:
 237            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 238            break;
 239         case I915_BIT_6_SWIZZLE_9_10_11:
 240            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 241               ((tile_off >> 5) & 64);
 242            break;
 243         default:
 244            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 245                    irb->region->bit_6_swizzle);
 246            exit(1);
 247         }
 248
 249         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 250
 251         return tile_base + tile_off;
 252 }
 253
 254 /*
 255   break intelWriteRGBASpan_ARGB8888
 256 */
 257
 258 #undef DBG
 259 #define DBG 0
 260
 261 #define LOCAL_VARS                                                      \
 262    struct intel_context *intel = intel_context(ctx);                    \
 263    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 264    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 265    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 266    unsigned int num_cliprects;                                          \
 267    struct drm_clip_rect *cliprects;                                     \
 268    int x_off, y_off;                                                    \
 269    int pitch = irb->region->pitch * irb->region->cpp;                   \
 270    void *buf = irb->region->buffer->virtual;                            \
 271    GLuint p;                                                            \
 272    (void) p;                                                            \
 273    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 274    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 275
 276 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 277  * the cliprect info from the context, not the driDrawable.
 278  * Move this into spantmp2.h someday.
 279  */
 280 #define HW_CLIPLOOP()                                                   \
 281    do {                                                                 \
 282       int _nc = num_cliprects;                                          \
 283       while ( _nc-- ) {                                                 \
 284          int minx = cliprects[_nc].x1 - x_off;                          \
 285          int miny = cliprects[_nc].y1 - y_off;                          \
 286          int maxx = cliprects[_nc].x2 - x_off;                          \
 287          int maxy = cliprects[_nc].y2 - y_off;
 288
 289 #if 0
 290       }}
 291 #endif
 292
 293 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 294
 295 #define HW_LOCK()
 296
 297 #define HW_UNLOCK()
 298
 299 /* Convenience macros to avoid typing the swizzle argument over and over */
 300 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 301 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 302 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 303
 304 /* r5g6b5 color span and pixel functions */
 305 #define INTEL_PIXEL_FMT GL_RGB
 306 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 307 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 308 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 309 #define INTEL_TAG(x) x##_RGB565
 310 #include "intel_spantmp.h"
 311
 312 /* a4r4g4b4 color span and pixel functions */
 313 #define INTEL_PIXEL_FMT GL_BGRA
 314 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 315 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 316 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 317 #define INTEL_TAG(x) x##_ARGB4444
 318 #include "intel_spantmp.h"
 319
 320 /* a1r5g5b5 color span and pixel functions */
 321 #define INTEL_PIXEL_FMT GL_BGRA
 322 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 323 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 324 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 325 #define INTEL_TAG(x) x##_ARGB1555
 326 #include "intel_spantmp.h"
 327
 328 /* a8r8g8b8 color span and pixel functions */
 329 #define INTEL_PIXEL_FMT GL_BGRA
 330 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 331 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 332 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 333 #define INTEL_TAG(x) x##_ARGB8888
 334 #include "intel_spantmp.h"
 335
 336 /* x8r8g8b8 color span and pixel functions */
 337 #define INTEL_PIXEL_FMT GL_BGR
 338 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 339 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 340 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 341 #define INTEL_TAG(x) x##_xRGB8888
 342 #include "intel_spantmp.h"
 343
 344 #define LOCAL_DEPTH_VARS                                                \
 345    struct intel_context *intel = intel_context(ctx);                    \
 346    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 347    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 348    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 349    unsigned int num_cliprects;                                          \
 350    struct drm_clip_rect *cliprects;                                     \
 351    int x_off, y_off;                                                    \
 352    int pitch = irb->region->pitch * irb->region->cpp;                   \
 353    void *buf = irb->region->buffer->virtual;                            \
 354    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 355    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 356
 357
 358 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 359
 360 /* z16 depthbuffer functions. */
 361 #define INTEL_VALUE_TYPE GLushort
 362 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 363 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 364 #define INTEL_TAG(name) name##_z16
 365 #include "intel_depthtmp.h"
 366
 367 /* z24x8 depthbuffer functions. */
 368 #define INTEL_VALUE_TYPE GLuint
 369 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 370 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 371 #define INTEL_TAG(name) name##_z24_x8
 372 #include "intel_depthtmp.h"
 373
 374
 375 /**
 376  ** 8-bit stencil function (XXX FBO: This is obsolete)
 377  **/
 378 /* XXX */
 379 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 380 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 381 #define TAG(x) intel_gttmap_##x##_z24_s8
 382 #include "stenciltmp.h"
 383
 384 /**
 385  ** 8-bit stencil function (XXX FBO: This is obsolete)
 386  **/
 387 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 388 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 389 #define TAG(x) intel##x##_z24_s8
 390 #include "stenciltmp.h"
 391
 392 /**
 393  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 394  **/
 395 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
 396 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
 397 #define TAG(x) intel_XTile_##x##_z24_s8
 398 #include "stenciltmp.h"
 399
 400 /**
 401  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 402  **/
 403 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
 404 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
 405 #define TAG(x) intel_YTile_##x##_z24_s8
 406 #include "stenciltmp.h"
 407
 408 void
 409 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 410 {
 411    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 412
 413    if (irb == NULL || irb->region == NULL)
 414       return;
 415
 416    if (intel->intelScreen->kernel_exec_fencing)
 417       drm_intel_gem_bo_map_gtt(irb->region->buffer);
 418
 419    intel_set_span_functions(intel, rb);
 420 }
 421
 422 void
 423 intel_renderbuffer_unmap(struct intel_context *intel,
 424                          struct gl_renderbuffer *rb)
 425 {
 426    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 427
 428    if (irb == NULL || irb->region == NULL)
 429       return;
 430
 431    if (intel->intelScreen->kernel_exec_fencing)
 432       drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
 433    else
 434       clear_span_cache(irb);
 435
 436    rb->GetRow = NULL;
 437    rb->PutRow = NULL;
 438 }
 439
 440 /**
 441  * Map or unmap all the renderbuffers which we may need during
 442  * software rendering.
 443  * XXX in the future, we could probably convey extra information to
 444  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 445  * from the depth buffer, we really only need one mapping.
 446  *
 447  * XXX Rewrite this function someday.
 448  * We can probably just loop over all the renderbuffer attachments,
 449  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 450  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 451  */
 452 static void
 453 intel_map_unmap_framebuffer(struct intel_context *intel,
 454                             struct gl_framebuffer *fb,
 455                             GLboolean map)
 456 {
 457    GLuint i;
 458
 459    /* color draw buffers */
 460    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 461       if (map)
 462          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 463       else
 464          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 465    }
 466
 467    /* color read buffer */
 468    if (map)
 469       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 470    else
 471       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 472
 473    /* check for render to textures */
 474    for (i = 0; i < BUFFER_COUNT; i++) {
 475       struct gl_renderbuffer_attachment *att =
 476          fb->Attachment + i;
 477       struct gl_texture_object *tex = att->Texture;
 478       if (tex) {
 479          /* render to texture */
 480          ASSERT(att->Renderbuffer);
 481          if (map)
 482             intel_tex_map_images(intel, intel_texture_object(tex));
 483          else
 484             intel_tex_unmap_images(intel, intel_texture_object(tex));
 485       }
 486    }
 487
 488    /* depth buffer (Note wrapper!) */
 489    if (fb->_DepthBuffer) {
 490       if (map)
 491          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 492       else
 493          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 494    }
 495
 496    /* stencil buffer (Note wrapper!) */
 497    if (fb->_StencilBuffer) {
 498       if (map)
 499          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 500       else
 501          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 502    }
 503
 504    intel_check_front_buffer_rendering(intel);
 505 }
 506
 507 /**
 508  * Prepare for software rendering.  Map current read/draw framebuffers'
 509  * renderbuffes and all currently bound texture objects.
 510  *
 511  * Old note: Moved locking out to get reasonable span performance.
 512  */
 513 void
 514 intelSpanRenderStart(GLcontext * ctx)
 515 {
 516    struct intel_context *intel = intel_context(ctx);
 517    GLuint i;
 518
 519    intelFlush(&intel->ctx);
 520
 521    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 522       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 523          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 524          intel_tex_map_images(intel, intel_texture_object(texObj));
 525       }
 526    }
 527
 528    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 529    if (ctx->ReadBuffer != ctx->DrawBuffer)
 530       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 531 }
 532
 533 /**
 534  * Called when done software rendering.  Unmap the buffers we mapped in
 535  * the above function.
 536  */
 537 void
 538 intelSpanRenderFinish(GLcontext * ctx)
 539 {
 540    struct intel_context *intel = intel_context(ctx);
 541    GLuint i;
 542
 543    _swrast_flush(ctx);
 544
 545    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 546       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 547          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 548          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 549       }
 550    }
 551
 552    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 553    if (ctx->ReadBuffer != ctx->DrawBuffer)
 554       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 555 }
 556
 557
 558 void
 559 intelInitSpanFuncs(GLcontext * ctx)
 560 {
 561    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 562    swdd->SpanRenderStart = intelSpanRenderStart;
 563    swdd->SpanRenderFinish = intelSpanRenderFinish;
 564 }
 565
 566 void
 567 intel_map_vertex_shader_textures(GLcontext *ctx)
 568 {
 569    struct intel_context *intel = intel_context(ctx);
 570    int i;
 571
 572    if (ctx->VertexProgram._Current == NULL)
 573       return;
 574
 575    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 576       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 577           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 578          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 579
 580          intel_tex_map_images(intel, intel_texture_object(texObj));
 581       }
 582    }
 583 }
 584
 585 void
 586 intel_unmap_vertex_shader_textures(GLcontext *ctx)
 587 {
 588    struct intel_context *intel = intel_context(ctx);
 589    int i;
 590
 591    if (ctx->VertexProgram._Current == NULL)
 592       return;
 593
 594    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 595       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 596           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 597          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 598
 599          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 600       }
 601    }
 602 }
 603
 604 /**
 605  * Plug in appropriate span read/write functions for the given renderbuffer.
 606  * These are used for the software fallbacks.
 607  */
 608 static void
 609 intel_set_span_functions(struct intel_context *intel,
 610                          struct gl_renderbuffer *rb)
 611 {
 612    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 613    uint32_t tiling = irb->region->tiling;
 614
 615    if (intel->intelScreen->kernel_exec_fencing) {
 616       switch (irb->Base.Format) {
 617       case MESA_FORMAT_RGB565:
 618          intel_gttmap_InitPointers_RGB565(rb);
 619          break;
 620       case MESA_FORMAT_ARGB4444:
 621          intel_gttmap_InitPointers_ARGB4444(rb);
 622          break;
 623       case MESA_FORMAT_ARGB1555:
 624          intel_gttmap_InitPointers_ARGB1555(rb);
 625          break;
 626       case MESA_FORMAT_XRGB8888:
 627          intel_gttmap_InitPointers_xRGB8888(rb);
 628          break;
 629       case MESA_FORMAT_ARGB8888:
 630          intel_gttmap_InitPointers_ARGB8888(rb);
 631          break;
 632       case MESA_FORMAT_Z16:
 633          intel_gttmap_InitDepthPointers_z16(rb);
 634          break;
 635       case MESA_FORMAT_X8_Z24:
 636          intel_gttmap_InitDepthPointers_z24_x8(rb);
 637          break;
 638       case MESA_FORMAT_S8_Z24:
 639          /* There are a few different ways SW asks us to access the S8Z24 data:
 640           * Z24 depth-only depth reads
 641           * S8Z24 depth reads
 642           * S8Z24 stencil reads.
 643           */
 644          if (rb->Format == MESA_FORMAT_S8_Z24) {
 645             intel_gttmap_InitDepthPointers_z24_x8(rb);
 646          } else if (rb->Format == MESA_FORMAT_S8) {
 647             intel_gttmap_InitStencilPointers_z24_s8(rb);
 648          }
 649          break;
 650       default:
 651          _mesa_problem(NULL,
 652                        "Unexpected MesaFormat %d in intelSetSpanFunctions",
 653                        irb->Base.Format);
 654          break;
 655       }
 656       return;
 657    }
 658
 659    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 660     * instead of the fence registers handling it.
 661     */
 662    switch (irb->Base.Format) {
 663    case MESA_FORMAT_RGB565:
 664       switch (tiling) {
 665       case I915_TILING_NONE:
 666       default:
 667          intelInitPointers_RGB565(rb);
 668          break;
 669       case I915_TILING_X:
 670          intel_XTile_InitPointers_RGB565(rb);
 671          break;
 672       case I915_TILING_Y:
 673          intel_YTile_InitPointers_RGB565(rb);
 674          break;
 675       }
 676       break;
 677    case MESA_FORMAT_ARGB4444:
 678       switch (tiling) {
 679       case I915_TILING_NONE:
 680       default:
 681          intelInitPointers_ARGB4444(rb);
 682          break;
 683       case I915_TILING_X:
 684          intel_XTile_InitPointers_ARGB4444(rb);
 685          break;
 686       case I915_TILING_Y:
 687          intel_YTile_InitPointers_ARGB4444(rb);
 688          break;
 689       }
 690       break;
 691    case MESA_FORMAT_ARGB1555:
 692       switch (tiling) {
 693       case I915_TILING_NONE:
 694       default:
 695          intelInitPointers_ARGB1555(rb);
 696          break;
 697       case I915_TILING_X:
 698          intel_XTile_InitPointers_ARGB1555(rb);
 699          break;
 700       case I915_TILING_Y:
 701          intel_YTile_InitPointers_ARGB1555(rb);
 702          break;
 703       }
 704       break;
 705    case MESA_FORMAT_XRGB8888:
 706       switch (tiling) {
 707       case I915_TILING_NONE:
 708       default:
 709          intelInitPointers_xRGB8888(rb);
 710          break;
 711       case I915_TILING_X:
 712          intel_XTile_InitPointers_xRGB8888(rb);
 713          break;
 714       case I915_TILING_Y:
 715          intel_YTile_InitPointers_xRGB8888(rb);
 716          break;
 717       }
 718       break;
 719    case MESA_FORMAT_ARGB8888:
 720       /* 8888 RGBA */
 721       switch (tiling) {
 722       case I915_TILING_NONE:
 723       default:
 724          intelInitPointers_ARGB8888(rb);
 725          break;
 726       case I915_TILING_X:
 727          intel_XTile_InitPointers_ARGB8888(rb);
 728          break;
 729       case I915_TILING_Y:
 730          intel_YTile_InitPointers_ARGB8888(rb);
 731          break;
 732       }
 733       break;
 734    case MESA_FORMAT_Z16:
 735       switch (tiling) {
 736       case I915_TILING_NONE:
 737       default:
 738          intelInitDepthPointers_z16(rb);
 739          break;
 740       case I915_TILING_X:
 741          intel_XTile_InitDepthPointers_z16(rb);
 742          break;
 743       case I915_TILING_Y:
 744          intel_YTile_InitDepthPointers_z16(rb);
 745          break;
 746       }
 747       break;
 748    case MESA_FORMAT_X8_Z24:
 749    case MESA_FORMAT_S8_Z24:
 750       /* There are a few different ways SW asks us to access the S8Z24 data:
 751        * Z24 depth-only depth reads
 752        * S8Z24 depth reads
 753        * S8Z24 stencil reads.
 754        */
 755       if (rb->Format == MESA_FORMAT_S8_Z24) {
 756          switch (tiling) {
 757          case I915_TILING_NONE:
 758          default:
 759             intelInitDepthPointers_z24_x8(rb);
 760             break;
 761          case I915_TILING_X:
 762             intel_XTile_InitDepthPointers_z24_x8(rb);
 763             break;
 764          case I915_TILING_Y:
 765             intel_YTile_InitDepthPointers_z24_x8(rb);
 766             break;
 767          }
 768       } else if (rb->Format == MESA_FORMAT_S8) {
 769          switch (tiling) {
 770          case I915_TILING_NONE:
 771          default:
 772             intelInitStencilPointers_z24_s8(rb);
 773             break;
 774          case I915_TILING_X:
 775             intel_XTile_InitStencilPointers_z24_s8(rb);
 776             break;
 777          case I915_TILING_Y:
 778             intel_YTile_InitStencilPointers_z24_s8(rb);
 779             break;
 780          }
 781       } else {
 782          _mesa_problem(NULL,
 783                        "Unexpected ActualFormat in intelSetSpanFunctions");
 784       }
 785       break;
 786    default:
 787       _mesa_problem(NULL,
 788                     "Unexpected MesaFormat in intelSetSpanFunctions");
 789       break;
 790    }
 791 }