1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "main/glheader.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "main/colormac.h"
32 #include "main/texformat.h"
34 #include "intel_buffers.h"
35 #include "intel_fbo.h"
36 #include "intel_screen.h"
37 #include "intel_span.h"
38 #include "intel_regions.h"
39 #include "intel_tex.h"
41 #include "swrast/swrast.h"
44 intel_set_span_functions(struct intel_context
*intel
,
45 struct gl_renderbuffer
*rb
);
47 #define SPAN_CACHE_SIZE 4096
50 get_span_cache(struct intel_renderbuffer
*irb
, uint32_t offset
)
52 if (irb
->span_cache
== NULL
) {
53 irb
->span_cache
= _mesa_malloc(SPAN_CACHE_SIZE
);
54 irb
->span_cache_offset
= -1;
57 if ((offset
& ~(SPAN_CACHE_SIZE
- 1)) != irb
->span_cache_offset
) {
58 irb
->span_cache_offset
= offset
& ~(SPAN_CACHE_SIZE
- 1);
59 dri_bo_get_subdata(irb
->region
->buffer
, irb
->span_cache_offset
,
60 SPAN_CACHE_SIZE
, irb
->span_cache
);
65 clear_span_cache(struct intel_renderbuffer
*irb
)
67 irb
->span_cache_offset
= -1;
71 pread_32(struct intel_renderbuffer
*irb
, uint32_t offset
)
73 get_span_cache(irb
, offset
);
75 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
79 pread_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
)
81 get_span_cache(irb
, offset
);
83 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1))) |
88 pread_16(struct intel_renderbuffer
*irb
, uint32_t offset
)
90 get_span_cache(irb
, offset
);
92 return *(uint16_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
96 pread_8(struct intel_renderbuffer
*irb
, uint32_t offset
)
98 get_span_cache(irb
, offset
);
100 return *(uint8_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
104 pwrite_32(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
106 clear_span_cache(irb
);
108 dri_bo_subdata(irb
->region
->buffer
, offset
, 4, &val
);
112 pwrite_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
114 clear_span_cache(irb
);
116 dri_bo_subdata(irb
->region
->buffer
, offset
, 3, &val
);
120 pwrite_16(struct intel_renderbuffer
*irb
, uint32_t offset
, uint16_t val
)
122 clear_span_cache(irb
);
124 dri_bo_subdata(irb
->region
->buffer
, offset
, 2, &val
);
128 pwrite_8(struct intel_renderbuffer
*irb
, uint32_t offset
, uint8_t val
)
130 clear_span_cache(irb
);
132 dri_bo_subdata(irb
->region
->buffer
, offset
, 1, &val
);
136 z24s8_to_s8z24(uint32_t val
)
138 return (val
<< 24) | (val
>> 8);
142 s8z24_to_z24s8(uint32_t val
)
144 return (val
>> 24) | (val
<< 8);
147 static uint32_t no_tile_swizzle(struct intel_renderbuffer
*irb
,
150 return (y
* irb
->region
->pitch
+ x
) * irb
->region
->cpp
;
154 * Deal with tiled surfaces
157 static uint32_t x_tile_swizzle(struct intel_renderbuffer
*irb
,
162 int x_tile_off
, y_tile_off
;
163 int x_tile_number
, y_tile_number
;
164 int tile_off
, tile_base
;
166 x
+= irb
->region
->draw_x
;
167 y
+= irb
->region
->draw_y
;
169 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 3;
171 xbyte
= x
* irb
->region
->cpp
;
173 x_tile_off
= xbyte
& 0x1ff;
176 x_tile_number
= xbyte
>> 9;
177 y_tile_number
= y
>> 3;
179 tile_off
= (y_tile_off
<< 9) + x_tile_off
;
181 switch (irb
->region
->bit_6_swizzle
) {
182 case I915_BIT_6_SWIZZLE_NONE
:
184 case I915_BIT_6_SWIZZLE_9
:
185 tile_off
^= ((tile_off
>> 3) & 64);
187 case I915_BIT_6_SWIZZLE_9_10
:
188 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
190 case I915_BIT_6_SWIZZLE_9_11
:
191 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
193 case I915_BIT_6_SWIZZLE_9_10_11
:
194 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
195 ((tile_off
>> 5) & 64);
198 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
199 irb
->region
->bit_6_swizzle
);
203 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
206 printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
207 x
, y
, tile_off
, tile_base
,
208 tile_off
+ tile_base
,
209 irb
->region
->pitch
, tile_stride
);
212 return tile_base
+ tile_off
;
215 static uint32_t y_tile_swizzle(struct intel_renderbuffer
*irb
,
220 int x_tile_off
, y_tile_off
;
221 int x_tile_number
, y_tile_number
;
222 int tile_off
, tile_base
;
224 x
+= irb
->region
->draw_x
;
225 y
+= irb
->region
->draw_y
;
227 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 5;
229 xbyte
= x
* irb
->region
->cpp
;
231 x_tile_off
= xbyte
& 0x7f;
232 y_tile_off
= y
& 0x1f;
234 x_tile_number
= xbyte
>> 7;
235 y_tile_number
= y
>> 5;
237 tile_off
= ((x_tile_off
& ~0xf) << 5) + (y_tile_off
<< 4) +
240 switch (irb
->region
->bit_6_swizzle
) {
241 case I915_BIT_6_SWIZZLE_NONE
:
243 case I915_BIT_6_SWIZZLE_9
:
244 tile_off
^= ((tile_off
>> 3) & 64);
246 case I915_BIT_6_SWIZZLE_9_10
:
247 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
249 case I915_BIT_6_SWIZZLE_9_11
:
250 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
252 case I915_BIT_6_SWIZZLE_9_10_11
:
253 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
254 ((tile_off
>> 5) & 64);
257 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
258 irb
->region
->bit_6_swizzle
);
262 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
264 return tile_base
+ tile_off
;
268 break intelWriteRGBASpan_ARGB8888
275 struct intel_context *intel = intel_context(ctx); \
276 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
277 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
278 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
279 unsigned int num_cliprects; \
280 struct drm_clip_rect *cliprects; \
284 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
286 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
287 * the cliprect info from the context, not the driDrawable.
288 * Move this into spantmp2.h someday.
290 #define HW_CLIPLOOP() \
292 int _nc = num_cliprects; \
294 int minx = cliprects[_nc].x1 - x_off; \
295 int miny = cliprects[_nc].y1 - y_off; \
296 int maxx = cliprects[_nc].x2 - x_off; \
297 int maxy = cliprects[_nc].y2 - y_off;
303 #define Y_FLIP(_y) ((_y) * yScale + yBias)
305 /* XXX with GEM, these need to tell the kernel */
310 /* Convenience macros to avoid typing the swizzle argument over and over */
311 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
312 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
313 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
315 /* r5g6b5 color span and pixel functions */
316 #define INTEL_PIXEL_FMT GL_RGB
317 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
318 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
319 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
320 #define INTEL_TAG(x) x##_RGB565
321 #include "intel_spantmp.h"
323 /* a4r4g4b4 color span and pixel functions */
324 #define INTEL_PIXEL_FMT GL_BGRA
325 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
326 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
327 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
328 #define INTEL_TAG(x) x##_ARGB4444
329 #include "intel_spantmp.h"
331 /* a1r5g5b5 color span and pixel functions */
332 #define INTEL_PIXEL_FMT GL_BGRA
333 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
334 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
335 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
336 #define INTEL_TAG(x) x##_ARGB1555
337 #include "intel_spantmp.h"
339 /* a8r8g8b8 color span and pixel functions */
340 #define INTEL_PIXEL_FMT GL_BGRA
341 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
342 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
343 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
344 #define INTEL_TAG(x) x##_ARGB8888
345 #include "intel_spantmp.h"
347 /* x8r8g8b8 color span and pixel functions */
348 #define INTEL_PIXEL_FMT GL_BGRA
349 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
350 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
351 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
352 #define INTEL_TAG(x) x##_xRGB8888
353 #include "intel_spantmp.h"
355 #define LOCAL_DEPTH_VARS \
356 struct intel_context *intel = intel_context(ctx); \
357 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
358 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
359 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
360 unsigned int num_cliprects; \
361 struct drm_clip_rect *cliprects; \
363 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
366 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
368 /* z16 depthbuffer functions. */
369 #define INTEL_VALUE_TYPE GLushort
370 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
371 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
372 #define INTEL_TAG(name) name##_z16
373 #include "intel_depthtmp.h"
375 /* z24 depthbuffer functions. */
376 #define INTEL_VALUE_TYPE GLuint
377 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
378 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
379 #define INTEL_TAG(name) name##_z24
380 #include "intel_depthtmp.h"
382 /* z24s8 depthbuffer functions. */
383 #define INTEL_VALUE_TYPE GLuint
384 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
385 #define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
386 #define INTEL_TAG(name) name##_z24_s8
387 #include "intel_depthtmp.h"
391 ** 8-bit stencil function (XXX FBO: This is obsolete)
393 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
394 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
395 #define TAG(x) intel##x##_z24_s8
396 #include "stenciltmp.h"
399 ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
401 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
402 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
403 #define TAG(x) intel_XTile_##x##_z24_s8
404 #include "stenciltmp.h"
407 ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
409 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
410 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
411 #define TAG(x) intel_YTile_##x##_z24_s8
412 #include "stenciltmp.h"
415 intel_renderbuffer_map(struct intel_context
*intel
, struct gl_renderbuffer
*rb
)
417 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
419 if (irb
== NULL
|| irb
->region
== NULL
)
422 intel_set_span_functions(intel
, rb
);
426 intel_renderbuffer_unmap(struct intel_context
*intel
,
427 struct gl_renderbuffer
*rb
)
429 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
431 if (irb
== NULL
|| irb
->region
== NULL
)
434 clear_span_cache(irb
);
441 * Map or unmap all the renderbuffers which we may need during
442 * software rendering.
443 * XXX in the future, we could probably convey extra information to
444 * reduce the number of mappings needed. I.e. if doing a glReadPixels
445 * from the depth buffer, we really only need one mapping.
447 * XXX Rewrite this function someday.
448 * We can probably just loop over all the renderbuffer attachments,
449 * map/unmap all of them, and not worry about the _ColorDrawBuffers
450 * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
453 intel_map_unmap_buffers(struct intel_context
*intel
, GLboolean map
)
455 GLcontext
*ctx
= &intel
->ctx
;
458 /* color draw buffers */
459 for (j
= 0; j
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; j
++) {
461 intel_renderbuffer_map(intel
, ctx
->DrawBuffer
->_ColorDrawBuffers
[j
]);
463 intel_renderbuffer_unmap(intel
, ctx
->DrawBuffer
->_ColorDrawBuffers
[j
]);
466 /* check for render to textures */
467 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
468 struct gl_renderbuffer_attachment
*att
=
469 ctx
->DrawBuffer
->Attachment
+ i
;
470 struct gl_texture_object
*tex
= att
->Texture
;
472 /* render to texture */
473 ASSERT(att
->Renderbuffer
);
475 intel_tex_map_images(intel
, intel_texture_object(tex
));
477 intel_tex_unmap_images(intel
, intel_texture_object(tex
));
481 /* color read buffers */
483 intel_renderbuffer_map(intel
, ctx
->ReadBuffer
->_ColorReadBuffer
);
485 intel_renderbuffer_unmap(intel
, ctx
->ReadBuffer
->_ColorReadBuffer
);
487 /* depth buffer (Note wrapper!) */
488 if (ctx
->DrawBuffer
->_DepthBuffer
) {
490 intel_renderbuffer_map(intel
, ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
492 intel_renderbuffer_unmap(intel
,
493 ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
496 /* stencil buffer (Note wrapper!) */
497 if (ctx
->DrawBuffer
->_StencilBuffer
) {
499 intel_renderbuffer_map(intel
,
500 ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
502 intel_renderbuffer_unmap(intel
,
503 ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
510 * Prepare for software rendering. Map current read/draw framebuffers'
511 * renderbuffes and all currently bound texture objects.
513 * Old note: Moved locking out to get reasonable span performance.
516 intelSpanRenderStart(GLcontext
* ctx
)
518 struct intel_context
*intel
= intel_context(ctx
);
521 intelFlush(&intel
->ctx
);
522 LOCK_HARDWARE(intel
);
524 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
525 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
526 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
527 intel_tex_map_images(intel
, intel_texture_object(texObj
));
531 intel_map_unmap_buffers(intel
, GL_TRUE
);
535 * Called when done software rendering. Unmap the buffers we mapped in
536 * the above function.
539 intelSpanRenderFinish(GLcontext
* ctx
)
541 struct intel_context
*intel
= intel_context(ctx
);
546 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
547 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
548 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
549 intel_tex_unmap_images(intel
, intel_texture_object(texObj
));
553 intel_map_unmap_buffers(intel
, GL_FALSE
);
555 UNLOCK_HARDWARE(intel
);
560 intelInitSpanFuncs(GLcontext
* ctx
)
562 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
563 swdd
->SpanRenderStart
= intelSpanRenderStart
;
564 swdd
->SpanRenderFinish
= intelSpanRenderFinish
;
569 * Plug in appropriate span read/write functions for the given renderbuffer.
570 * These are used for the software fallbacks.
573 intel_set_span_functions(struct intel_context
*intel
,
574 struct gl_renderbuffer
*rb
)
576 struct intel_renderbuffer
*irb
= (struct intel_renderbuffer
*) rb
;
579 /* If in GEM mode, we need to do the tile address swizzling ourselves,
580 * instead of the fence registers handling it.
583 tiling
= irb
->region
->tiling
;
585 tiling
= I915_TILING_NONE
;
587 switch (irb
->texformat
->MesaFormat
) {
588 case MESA_FORMAT_RGB565
:
590 case I915_TILING_NONE
:
592 intelInitPointers_RGB565(rb
);
595 intel_XTile_InitPointers_RGB565(rb
);
598 intel_YTile_InitPointers_RGB565(rb
);
602 case MESA_FORMAT_ARGB4444
:
604 case I915_TILING_NONE
:
606 intelInitPointers_ARGB4444(rb
);
609 intel_XTile_InitPointers_ARGB4444(rb
);
612 intel_YTile_InitPointers_ARGB4444(rb
);
616 case MESA_FORMAT_ARGB1555
:
618 case I915_TILING_NONE
:
620 intelInitPointers_ARGB1555(rb
);
623 intel_XTile_InitPointers_ARGB1555(rb
);
626 intel_YTile_InitPointers_ARGB1555(rb
);
630 case MESA_FORMAT_ARGB8888
:
631 if (rb
->AlphaBits
== 0) { /* XXX: Need xRGB8888 Mesa format */
634 case I915_TILING_NONE
:
636 intelInitPointers_xRGB8888(rb
);
639 intel_XTile_InitPointers_xRGB8888(rb
);
642 intel_YTile_InitPointers_xRGB8888(rb
);
648 case I915_TILING_NONE
:
650 intelInitPointers_ARGB8888(rb
);
653 intel_XTile_InitPointers_ARGB8888(rb
);
656 intel_YTile_InitPointers_ARGB8888(rb
);
661 case MESA_FORMAT_Z16
:
663 case I915_TILING_NONE
:
665 intelInitDepthPointers_z16(rb
);
668 intel_XTile_InitDepthPointers_z16(rb
);
671 intel_YTile_InitDepthPointers_z16(rb
);
675 case MESA_FORMAT_S8_Z24
:
676 /* There are a few different ways SW asks us to access the S8Z24 data:
677 * Z24 depth-only depth reads
679 * S8Z24 stencil reads.
681 if (rb
->_ActualFormat
== GL_DEPTH_COMPONENT24
) {
683 case I915_TILING_NONE
:
685 intelInitDepthPointers_z24(rb
);
688 intel_XTile_InitDepthPointers_z24(rb
);
691 intel_YTile_InitDepthPointers_z24(rb
);
694 } else if (rb
->_ActualFormat
== GL_DEPTH24_STENCIL8_EXT
) {
696 case I915_TILING_NONE
:
698 intelInitDepthPointers_z24_s8(rb
);
701 intel_XTile_InitDepthPointers_z24_s8(rb
);
704 intel_YTile_InitDepthPointers_z24_s8(rb
);
707 } else if (rb
->_ActualFormat
== GL_STENCIL_INDEX8_EXT
) {
709 case I915_TILING_NONE
:
711 intelInitStencilPointers_z24_s8(rb
);
714 intel_XTile_InitStencilPointers_z24_s8(rb
);
717 intel_YTile_InitStencilPointers_z24_s8(rb
);
724 "Unexpected MesaFormat in intelSetSpanFunctions");