src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32
  33 #include "intel_fbo.h"
  34 #include "intel_screen.h"
  35 #include "intel_span.h"
  36 #include "intel_regions.h"
  37 #include "intel_tex.h"
  38
  39 #include "swrast/swrast.h"
  40
  41 static void
  42 intel_set_span_functions(struct intel_context *intel,
  43                          struct gl_renderbuffer *rb);
  44
  45 #define SPAN_CACHE_SIZE         4096
  46
  47 static void
  48 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  49 {
  50    if (irb->span_cache == NULL) {
  51       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  52       irb->span_cache_offset = -1;
  53    }
  54
  55    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  56       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  57       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  58                          SPAN_CACHE_SIZE, irb->span_cache);
  59    }
  60 }
  61
  62 static void
  63 clear_span_cache(struct intel_renderbuffer *irb)
  64 {
  65    irb->span_cache_offset = -1;
  66 }
  67
  68 static uint32_t
  69 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  70 {
  71    get_span_cache(irb, offset);
  72
  73    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  74 }
  75
  76 static uint32_t
  77 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  78 {
  79    get_span_cache(irb, offset);
  80
  81    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  82       0xff000000;
  83 }
  84
  85 static uint16_t
  86 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  87 {
  88    get_span_cache(irb, offset);
  89
  90    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  91 }
  92
  93 static uint8_t
  94 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  95 {
  96    get_span_cache(irb, offset);
  97
  98    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  99 }
 100
 101 static void
 102 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 103 {
 104    clear_span_cache(irb);
 105
 106    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 107 }
 108
 109 static void
 110 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 111 {
 112    clear_span_cache(irb);
 113
 114    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 115 }
 116
 117 static void
 118 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 119 {
 120    clear_span_cache(irb);
 121
 122    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 123 }
 124
 125 static void
 126 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 127 {
 128    clear_span_cache(irb);
 129
 130    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 131 }
 132
 133 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 134                                 struct intel_context *intel,
 135                                 int x, int y)
 136 {
 137         x += intel->drawX;
 138         y += intel->drawY;
 139
 140         return (y * irb->region->pitch + x) * irb->region->cpp;
 141 }
 142
 143 /*
 144  * Deal with tiled surfaces
 145  */
 146
 147 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 148                                struct intel_context *intel,
 149                                int x, int y)
 150 {
 151         int     tile_stride;
 152         int     xbyte;
 153         int     x_tile_off, y_tile_off;
 154         int     x_tile_number, y_tile_number;
 155         int     tile_off, tile_base;
 156
 157         tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
 158
 159         x += intel->drawX;
 160         y += intel->drawY;
 161
 162         xbyte = x * irb->region->cpp;
 163
 164         x_tile_off = xbyte & 0x1ff;
 165         y_tile_off = y & 7;
 166
 167         x_tile_number = xbyte >> 9;
 168         y_tile_number = y >> 3;
 169
 170         tile_off = (y_tile_off << 9) + x_tile_off;
 171
 172         switch (irb->region->bit_6_swizzle) {
 173         case I915_BIT_6_SWIZZLE_NONE:
 174            break;
 175         case I915_BIT_6_SWIZZLE_9:
 176            tile_off ^= ((tile_off >> 3) & 64);
 177            break;
 178         case I915_BIT_6_SWIZZLE_9_10:
 179            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 180            break;
 181         case I915_BIT_6_SWIZZLE_9_11:
 182            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 183            break;
 184         case I915_BIT_6_SWIZZLE_9_10_11:
 185            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 186               ((tile_off >> 5) & 64);
 187            break;
 188         default:
 189            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 190                    irb->region->bit_6_swizzle);
 191            exit(1);
 192         }
 193
 194         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 195
 196 #if 0
 197         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 198                x, y, tile_off, tile_base,
 199                tile_off + tile_base,
 200                irb->pfPitch, tile_stride);
 201 #endif
 202
 203         return tile_base + tile_off;
 204 }
 205
 206 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 207                                struct intel_context *intel,
 208                                int x, int y)
 209 {
 210         int     tile_stride;
 211         int     xbyte;
 212         int     x_tile_off, y_tile_off;
 213         int     x_tile_number, y_tile_number;
 214         int     tile_off, tile_base;
 215
 216         tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
 217
 218         x += intel->drawX;
 219         y += intel->drawY;
 220
 221         xbyte = x * irb->region->cpp;
 222
 223         x_tile_off = xbyte & 0x7f;
 224         y_tile_off = y & 0x1f;
 225
 226         x_tile_number = xbyte >> 7;
 227         y_tile_number = y >> 5;
 228
 229         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 230            (x_tile_off & 0xf);
 231
 232         switch (irb->region->bit_6_swizzle) {
 233         case I915_BIT_6_SWIZZLE_NONE:
 234            break;
 235         case I915_BIT_6_SWIZZLE_9:
 236            tile_off ^= ((tile_off >> 3) & 64);
 237            break;
 238         case I915_BIT_6_SWIZZLE_9_10:
 239            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 240            break;
 241         case I915_BIT_6_SWIZZLE_9_11:
 242            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 243            break;
 244         case I915_BIT_6_SWIZZLE_9_10_11:
 245            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 246               ((tile_off >> 5) & 64);
 247            break;
 248         default:
 249            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 250                    irb->region->bit_6_swizzle);
 251            exit(1);
 252         }
 253
 254         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 255
 256         return tile_base + tile_off;
 257 }
 258
 259 /*
 260   break intelWriteRGBASpan_ARGB8888
 261 */
 262
 263 #undef DBG
 264 #define DBG 0
 265
 266 #define LOCAL_VARS                                                      \
 267    struct intel_context *intel = intel_context(ctx);                    \
 268    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 269    const GLint yScale = irb->RenderToTexture ? 1 : -1;                  \
 270    const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
 271    GLuint p;                                                            \
 272    (void) p;
 273
 274 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 275  * the cliprect info from the context, not the driDrawable.
 276  * Move this into spantmp2.h someday.
 277  */
 278 #define HW_CLIPLOOP()                                                   \
 279    do {                                                                 \
 280       int _nc = intel->numClipRects;                                    \
 281       while ( _nc-- ) {                                                 \
 282          int minx = intel->pClipRects[_nc].x1 - intel->drawX;           \
 283          int miny = intel->pClipRects[_nc].y1 - intel->drawY;           \
 284          int maxx = intel->pClipRects[_nc].x2 - intel->drawX;           \
 285          int maxy = intel->pClipRects[_nc].y2 - intel->drawY;
 286
 287 #if 0
 288       }}
 289 #endif
 290
 291 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 292
 293 /* XXX with GEM, these need to tell the kernel */
 294 #define HW_LOCK()
 295
 296 #define HW_UNLOCK()
 297
 298 /* 16 bit, RGB565 color spanline and pixel functions
 299  */
 300 #define SPANTMP_PIXEL_FMT GL_RGB
 301 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 302
 303 #define TAG(x)    intel##x##_RGB565
 304 #define TAG2(x,y) intel##x##_RGB565##y
 305 #define GET_VALUE(X, Y) pread_16(irb, no_tile_swizzle(irb, intel, X, Y))
 306 #define PUT_VALUE(X, Y, V) pwrite_16(irb, no_tile_swizzle(irb, intel, X, Y), V)
 307 #include "spantmp2.h"
 308
 309 /* 32 bit, ARGB8888 color spanline and pixel functions
 310  */
 311 #define SPANTMP_PIXEL_FMT GL_BGRA
 312 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 313
 314 #define TAG(x)    intel##x##_ARGB8888
 315 #define TAG2(x,y) intel##x##_ARGB8888##y
 316 #define GET_VALUE(X, Y) pread_32(irb, no_tile_swizzle(irb, intel, X, Y))
 317 #define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
 318 #include "spantmp2.h"
 319
 320 /* 32 bit, xRGB8888 color spanline and pixel functions
 321  */
 322 #define SPANTMP_PIXEL_FMT GL_BGRA
 323 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 324
 325 #define TAG(x)    intel##x##_xRGB8888
 326 #define TAG2(x,y) intel##x##_xRGB8888##y
 327 #define GET_VALUE(X, Y) pread_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y))
 328 #define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y), V)
 329 #include "spantmp2.h"
 330
 331 /* 16 bit RGB565 color tile spanline and pixel functions
 332  */
 333
 334 #define SPANTMP_PIXEL_FMT GL_RGB
 335 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 336
 337 #define TAG(x)    intel_XTile_##x##_RGB565
 338 #define TAG2(x,y) intel_XTile_##x##_RGB565##y
 339 #define GET_VALUE(X, Y) pread_16(irb, x_tile_swizzle(irb, intel, X, Y))
 340 #define PUT_VALUE(X, Y, V) pwrite_16(irb, x_tile_swizzle(irb, intel, X, Y), V)
 341 #include "spantmp2.h"
 342
 343 #define SPANTMP_PIXEL_FMT GL_RGB
 344 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 345
 346 #define TAG(x)    intel_YTile_##x##_RGB565
 347 #define TAG2(x,y) intel_YTile_##x##_RGB565##y
 348 #define GET_VALUE(X, Y) pread_16(irb, y_tile_swizzle(irb, intel, X, Y))
 349 #define PUT_VALUE(X, Y, V) pwrite_16(irb, y_tile_swizzle(irb, intel, X, Y), V)
 350 #include "spantmp2.h"
 351
 352 /* 32 bit ARGB888 color tile spanline and pixel functions
 353  */
 354
 355 #define SPANTMP_PIXEL_FMT GL_BGRA
 356 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 357
 358 #define TAG(x)    intel_XTile_##x##_ARGB8888
 359 #define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
 360 #define GET_VALUE(X, Y) pread_32(irb, x_tile_swizzle(irb, intel, X, Y))
 361 #define PUT_VALUE(X, Y, V) pwrite_32(irb, x_tile_swizzle(irb, intel, X, Y), V)
 362 #include "spantmp2.h"
 363
 364 #define SPANTMP_PIXEL_FMT GL_BGRA
 365 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 366
 367 #define TAG(x)    intel_YTile_##x##_ARGB8888
 368 #define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
 369 #define GET_VALUE(X, Y) pread_32(irb, y_tile_swizzle(irb, intel, X, Y))
 370 #define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
 371 #include "spantmp2.h"
 372
 373 /* 32 bit xRGB888 color tile spanline and pixel functions
 374  */
 375
 376 #define SPANTMP_PIXEL_FMT GL_BGRA
 377 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 378
 379 #define TAG(x)    intel_XTile_##x##_xRGB8888
 380 #define TAG2(x,y) intel_XTile_##x##_xRGB8888##y
 381 #define GET_VALUE(X, Y) pread_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y))
 382 #define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y), V)
 383 #include "spantmp2.h"
 384
 385 #define SPANTMP_PIXEL_FMT GL_BGRA
 386 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 387
 388 #define TAG(x)    intel_YTile_##x##_xRGB8888
 389 #define TAG2(x,y) intel_YTile_##x##_xRGB8888##y
 390 #define GET_VALUE(X, Y) pread_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y))
 391 #define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y), V)
 392 #include "spantmp2.h"
 393
 394 #define LOCAL_DEPTH_VARS                                                \
 395    struct intel_context *intel = intel_context(ctx);                    \
 396    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 397    const GLint yScale = irb->RenderToTexture ? 1 : -1;                  \
 398    const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;
 399
 400
 401 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 402
 403 /**
 404  ** 16-bit depthbuffer functions.
 405  **/
 406 #define VALUE_TYPE GLushort
 407 #define WRITE_DEPTH(_x, _y, d) \
 408    pwrite_16(irb, no_tile_swizzle(irb, intel, _x, _y), d)
 409 #define READ_DEPTH(d, _x, _y) \
 410    d = pread_16(irb, no_tile_swizzle(irb, intel, _x, _y))
 411 #define TAG(x) intel##x##_z16
 412 #include "depthtmp.h"
 413
 414
 415 /**
 416  ** 16-bit x tile depthbuffer functions.
 417  **/
 418 #define VALUE_TYPE GLushort
 419 #define WRITE_DEPTH(_x, _y, d) \
 420    pwrite_16(irb, x_tile_swizzle(irb, intel, _x, _y), d)
 421 #define READ_DEPTH(d, _x, _y) \
 422    d = pread_16(irb, x_tile_swizzle(irb, intel, _x, _y))
 423 #define TAG(x) intel_XTile_##x##_z16
 424 #include "depthtmp.h"
 425
 426 /**
 427  ** 16-bit y tile depthbuffer functions.
 428  **/
 429 #define VALUE_TYPE GLushort
 430 #define WRITE_DEPTH(_x, _y, d) \
 431    pwrite_16(irb, y_tile_swizzle(irb, intel, _x, _y), d)
 432 #define READ_DEPTH(d, _x, _y) \
 433    d = pread_16(irb, y_tile_swizzle(irb, intel, _x, _y))
 434 #define TAG(x) intel_YTile_##x##_z16
 435 #include "depthtmp.h"
 436
 437
 438 /**
 439  ** 24/8-bit interleaved depth/stencil functions
 440  ** Note: we're actually reading back combined depth+stencil values.
 441  ** The wrappers in main/depthstencil.c are used to extract the depth
 442  ** and stencil values.
 443  **/
 444 #define VALUE_TYPE GLuint
 445
 446 /* Change ZZZS -> SZZZ */
 447 #define WRITE_DEPTH(_x, _y, d)                                  \
 448    pwrite_32(irb, no_tile_swizzle(irb, intel, _x, _y),          \
 449              ((d) >> 8) | ((d) << 24))
 450
 451 /* Change SZZZ -> ZZZS */
 452 #define READ_DEPTH( d, _x, _y ) {                               \
 453    GLuint tmp = pread_32(irb, no_tile_swizzle(irb, intel, _x, _y));     \
 454    d = (tmp << 8) | (tmp >> 24);                                \
 455 }
 456
 457 #define TAG(x) intel##x##_z24_s8
 458 #include "depthtmp.h"
 459
 460
 461 /**
 462  ** 24/8-bit x-tile interleaved depth/stencil functions
 463  ** Note: we're actually reading back combined depth+stencil values.
 464  ** The wrappers in main/depthstencil.c are used to extract the depth
 465  ** and stencil values.
 466  **/
 467 #define VALUE_TYPE GLuint
 468
 469 /* Change ZZZS -> SZZZ */
 470 #define WRITE_DEPTH(_x, _y, d)                                  \
 471    pwrite_32(irb, x_tile_swizzle(irb, intel, _x, _y),           \
 472              ((d) >> 8) | ((d) << 24))                          \
 473
 474 /* Change SZZZ -> ZZZS */
 475 #define READ_DEPTH( d, _x, _y ) {                               \
 476    GLuint tmp = pread_32(irb, x_tile_swizzle(irb, intel, _x, _y));      \
 477    d = (tmp << 8) | (tmp >> 24);                                \
 478 }
 479
 480 #define TAG(x) intel_XTile_##x##_z24_s8
 481 #include "depthtmp.h"
 482
 483 /**
 484  ** 24/8-bit y-tile interleaved depth/stencil functions
 485  ** Note: we're actually reading back combined depth+stencil values.
 486  ** The wrappers in main/depthstencil.c are used to extract the depth
 487  ** and stencil values.
 488  **/
 489 #define VALUE_TYPE GLuint
 490
 491 /* Change ZZZS -> SZZZ */
 492 #define WRITE_DEPTH(_x, _y, d)                                  \
 493    pwrite_32(irb, y_tile_swizzle(irb, intel, _x, _y),           \
 494              ((d) >> 8) | ((d) << 24))
 495
 496 /* Change SZZZ -> ZZZS */
 497 #define READ_DEPTH( d, _x, _y ) {                               \
 498    GLuint tmp = pread_32(irb, y_tile_swizzle(irb, intel, _x, _y));      \
 499    d = (tmp << 8) | (tmp >> 24);                                \
 500 }
 501
 502 #define TAG(x) intel_YTile_##x##_z24_s8
 503 #include "depthtmp.h"
 504
 505
 506 /**
 507  ** 8-bit stencil function (XXX FBO: This is obsolete)
 508  **/
 509 #define WRITE_STENCIL(_x, _y, d)                                \
 510    pwrite_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3, d)
 511
 512 #define READ_STENCIL(d, _x, _y)                                 \
 513    d = pread_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3);
 514
 515 #define TAG(x) intel##x##_z24_s8
 516 #include "stenciltmp.h"
 517
 518 /**
 519  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 520  **/
 521 #define WRITE_STENCIL(_x, _y, d)                                \
 522    pwrite_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3, d)
 523
 524 #define READ_STENCIL(d, _x, _y)                                 \
 525    d = pread_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3);
 526
 527 #define TAG(x) intel_XTile_##x##_z24_s8
 528 #include "stenciltmp.h"
 529
 530 /**
 531  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 532  **/
 533 #define WRITE_STENCIL(_x, _y, d)                                \
 534    pwrite_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3, d)
 535
 536 #define READ_STENCIL(d, _x, _y)                                 \
 537    d = pread_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3)
 538
 539 #define TAG(x) intel_YTile_##x##_z24_s8
 540 #include "stenciltmp.h"
 541
 542 void
 543 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 544 {
 545    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 546
 547    if (irb == NULL || irb->region == NULL)
 548       return;
 549
 550    irb->pfPitch = irb->region->pitch;
 551
 552    intel_set_span_functions(intel, rb);
 553 }
 554
 555 void
 556 intel_renderbuffer_unmap(struct intel_context *intel,
 557                          struct gl_renderbuffer *rb)
 558 {
 559    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 560
 561    if (irb == NULL || irb->region == NULL)
 562       return;
 563
 564    clear_span_cache(irb);
 565    irb->pfPitch = 0;
 566
 567    rb->GetRow = NULL;
 568    rb->PutRow = NULL;
 569 }
 570
 571 /**
 572  * Map or unmap all the renderbuffers which we may need during
 573  * software rendering.
 574  * XXX in the future, we could probably convey extra information to
 575  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 576  * from the depth buffer, we really only need one mapping.
 577  *
 578  * XXX Rewrite this function someday.
 579  * We can probably just loop over all the renderbuffer attachments,
 580  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 581  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 582  */
 583 static void
 584 intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
 585 {
 586    GLcontext *ctx = &intel->ctx;
 587    GLuint i, j;
 588
 589    /* color draw buffers */
 590    for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
 591       if (map)
 592          intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
 593       else
 594          intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
 595    }
 596
 597    /* check for render to textures */
 598    for (i = 0; i < BUFFER_COUNT; i++) {
 599       struct gl_renderbuffer_attachment *att =
 600          ctx->DrawBuffer->Attachment + i;
 601       struct gl_texture_object *tex = att->Texture;
 602       if (tex) {
 603          /* render to texture */
 604          ASSERT(att->Renderbuffer);
 605          if (map) {
 606             struct gl_texture_image *texImg;
 607             texImg = tex->Image[att->CubeMapFace][att->TextureLevel];
 608             intel_tex_map_images(intel, intel_texture_object(tex));
 609          }
 610          else {
 611             intel_tex_unmap_images(intel, intel_texture_object(tex));
 612          }
 613       }
 614    }
 615
 616    /* color read buffers */
 617    if (map)
 618       intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
 619    else
 620       intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
 621
 622    /* depth buffer (Note wrapper!) */
 623    if (ctx->DrawBuffer->_DepthBuffer) {
 624       if (map)
 625          intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
 626       else
 627          intel_renderbuffer_unmap(intel,
 628                                   ctx->DrawBuffer->_DepthBuffer->Wrapped);
 629    }
 630
 631    /* stencil buffer (Note wrapper!) */
 632    if (ctx->DrawBuffer->_StencilBuffer) {
 633       if (map)
 634          intel_renderbuffer_map(intel,
 635                                 ctx->DrawBuffer->_StencilBuffer->Wrapped);
 636       else
 637          intel_renderbuffer_unmap(intel,
 638                                   ctx->DrawBuffer->_StencilBuffer->Wrapped);
 639    }
 640 }
 641
 642
 643
 644 /**
 645  * Prepare for softare rendering.  Map current read/draw framebuffers'
 646  * renderbuffes and all currently bound texture objects.
 647  *
 648  * Old note: Moved locking out to get reasonable span performance.
 649  */
 650 void
 651 intelSpanRenderStart(GLcontext * ctx)
 652 {
 653    struct intel_context *intel = intel_context(ctx);
 654    GLuint i;
 655
 656    intelFlush(&intel->ctx);
 657    LOCK_HARDWARE(intel);
 658
 659    for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
 660       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 661          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 662          intel_tex_map_images(intel, intel_texture_object(texObj));
 663       }
 664    }
 665
 666    intel_map_unmap_buffers(intel, GL_TRUE);
 667 }
 668
 669 /**
 670  * Called when done softare rendering.  Unmap the buffers we mapped in
 671  * the above function.
 672  */
 673 void
 674 intelSpanRenderFinish(GLcontext * ctx)
 675 {
 676    struct intel_context *intel = intel_context(ctx);
 677    GLuint i;
 678
 679    _swrast_flush(ctx);
 680
 681    for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
 682       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 683          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 684          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 685       }
 686    }
 687
 688    intel_map_unmap_buffers(intel, GL_FALSE);
 689
 690    UNLOCK_HARDWARE(intel);
 691 }
 692
 693
 694 void
 695 intelInitSpanFuncs(GLcontext * ctx)
 696 {
 697    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 698    swdd->SpanRenderStart = intelSpanRenderStart;
 699    swdd->SpanRenderFinish = intelSpanRenderFinish;
 700 }
 701
 702
 703 /**
 704  * Plug in appropriate span read/write functions for the given renderbuffer.
 705  * These are used for the software fallbacks.
 706  */
 707 static void
 708 intel_set_span_functions(struct intel_context *intel,
 709                          struct gl_renderbuffer *rb)
 710 {
 711    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 712    uint32_t tiling;
 713
 714    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 715     * instead of the fence registers handling it.
 716     */
 717    if (intel->ttm)
 718       tiling = irb->region->tiling;
 719    else
 720       tiling = I915_TILING_NONE;
 721
 722    if (rb->_ActualFormat == GL_RGB5) {
 723       /* 565 RGB */
 724       switch (tiling) {
 725       case I915_TILING_NONE:
 726       default:
 727          intelInitPointers_RGB565(rb);
 728          break;
 729       case I915_TILING_X:
 730          intel_XTile_InitPointers_RGB565(rb);
 731          break;
 732       case I915_TILING_Y:
 733          intel_YTile_InitPointers_RGB565(rb);
 734          break;
 735       }
 736    }
 737    else if (rb->_ActualFormat == GL_RGB8) {
 738       /* 8888 RGBx */
 739       switch (tiling) {
 740       case I915_TILING_NONE:
 741       default:
 742          intelInitPointers_xRGB8888(rb);
 743          break;
 744       case I915_TILING_X:
 745          intel_XTile_InitPointers_xRGB8888(rb);
 746          break;
 747       case I915_TILING_Y:
 748          intel_YTile_InitPointers_xRGB8888(rb);
 749          break;
 750       }
 751    }
 752    else if (rb->_ActualFormat == GL_RGBA8) {
 753       /* 8888 RGBA */
 754       switch (tiling) {
 755       case I915_TILING_NONE:
 756       default:
 757          intelInitPointers_ARGB8888(rb);
 758          break;
 759       case I915_TILING_X:
 760          intel_XTile_InitPointers_ARGB8888(rb);
 761          break;
 762       case I915_TILING_Y:
 763          intel_YTile_InitPointers_ARGB8888(rb);
 764          break;
 765       }
 766    }
 767    else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
 768       switch (tiling) {
 769       case I915_TILING_NONE:
 770       default:
 771          intelInitDepthPointers_z16(rb);
 772          break;
 773       case I915_TILING_X:
 774          intel_XTile_InitDepthPointers_z16(rb);
 775          break;
 776       case I915_TILING_Y:
 777          intel_YTile_InitDepthPointers_z16(rb);
 778          break;
 779       }
 780    }
 781    else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 ||        /* XXX FBO remove */
 782             rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
 783       switch (tiling) {
 784       case I915_TILING_NONE:
 785       default:
 786          intelInitDepthPointers_z24_s8(rb);
 787          break;
 788       case I915_TILING_X:
 789          intel_XTile_InitDepthPointers_z24_s8(rb);
 790          break;
 791       case I915_TILING_Y:
 792          intel_YTile_InitDepthPointers_z24_s8(rb);
 793          break;
 794       }
 795    }
 796    else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
 797       switch (tiling) {
 798       case I915_TILING_NONE:
 799       default:
 800          intelInitStencilPointers_z24_s8(rb);
 801          break;
 802       case I915_TILING_X:
 803          intel_XTile_InitStencilPointers_z24_s8(rb);
 804          break;
 805       case I915_TILING_Y:
 806          intel_YTile_InitStencilPointers_z24_s8(rb);
 807          break;
 808       }
 809    }
 810    else {
 811       _mesa_problem(NULL,
 812                     "Unexpected _ActualFormat in intelSetSpanFunctions");
 813    }
 814 }