dri/nouveau: Implement texture matrices.
[mesa.git] / src / mesa / drivers / dri / nouveau / nv10_state_tex.c
1 /*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "nouveau_driver.h"
28 #include "nouveau_context.h"
29 #include "nouveau_gldefs.h"
30 #include "nouveau_texture.h"
31 #include "nouveau_class.h"
32 #include "nouveau_util.h"
33 #include "nv10_driver.h"
34
35 #define TX_MATRIX(i) (NV10TCL_TX0_MATRIX(0) + 64 * (i))
36
37 void
38 nv10_emit_tex_gen(GLcontext *ctx, int emit)
39 {
40 }
41
42 void
43 nv10_emit_tex_mat(GLcontext *ctx, int emit)
44 {
45 const int i = emit - NOUVEAU_STATE_TEX_MAT0;
46 struct nouveau_context *nctx = to_nouveau_context(ctx);
47 struct nouveau_channel *chan = context_chan(ctx);
48 struct nouveau_grobj *celsius = context_eng3d(ctx);
49
50 if (nctx->fallback == HWTNL &&
51 ((ctx->Texture._TexMatEnabled & 1 << i) ||
52 ctx->Texture.Unit[i]._GenFlags)) {
53 BEGIN_RING(chan, celsius, NV10TCL_TX_MATRIX_ENABLE(i), 1);
54 OUT_RING(chan, 1);
55
56 BEGIN_RING(chan, celsius, TX_MATRIX(i), 16);
57 OUT_RINGm(chan, ctx->TextureMatrixStack[i].Top->m);
58
59 } else {
60 BEGIN_RING(chan, celsius, NV10TCL_TX_MATRIX_ENABLE(i), 1);
61 OUT_RING(chan, 0);
62 }
63 }
64
65 static uint32_t
66 get_tex_format_pot(struct gl_texture_image *ti)
67 {
68 switch (ti->TexFormat) {
69 case MESA_FORMAT_ARGB8888:
70 return NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8;
71
72 case MESA_FORMAT_XRGB8888:
73 return NV10TCL_TX_FORMAT_FORMAT_X8R8G8B8;
74
75 case MESA_FORMAT_ARGB1555:
76 return NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5;
77
78 case MESA_FORMAT_ARGB4444:
79 return NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4;
80
81 case MESA_FORMAT_RGB565:
82 return NV10TCL_TX_FORMAT_FORMAT_R5G6B5;
83
84 case MESA_FORMAT_A8:
85 case MESA_FORMAT_I8:
86 return NV10TCL_TX_FORMAT_FORMAT_A8;
87
88 case MESA_FORMAT_L8:
89 return NV10TCL_TX_FORMAT_FORMAT_L8;
90
91 case MESA_FORMAT_CI8:
92 return NV10TCL_TX_FORMAT_FORMAT_INDEX8;
93
94 default:
95 assert(0);
96 }
97 }
98
99 static uint32_t
100 get_tex_format_rect(struct gl_texture_image *ti)
101 {
102 switch (ti->TexFormat) {
103 case MESA_FORMAT_ARGB1555:
104 return NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT;
105
106 case MESA_FORMAT_RGB565:
107 return NV10TCL_TX_FORMAT_FORMAT_R5G6B5_RECT;
108
109 case MESA_FORMAT_ARGB8888:
110 case MESA_FORMAT_XRGB8888:
111 return NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT;
112
113 case MESA_FORMAT_A8:
114 case MESA_FORMAT_L8:
115 case MESA_FORMAT_I8:
116 return NV10TCL_TX_FORMAT_FORMAT_A8_RECT;
117
118 default:
119 assert(0);
120 }
121 }
122
123 void
124 nv10_emit_tex_obj(GLcontext *ctx, int emit)
125 {
126 const int i = emit - NOUVEAU_STATE_TEX_OBJ0;
127 struct nouveau_channel *chan = context_chan(ctx);
128 struct nouveau_grobj *celsius = context_eng3d(ctx);
129 struct nouveau_bo_context *bctx = context_bctx_i(ctx, TEXTURE, i);
130 const int bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART | NOUVEAU_BO_VRAM;
131 struct gl_texture_object *t;
132 struct nouveau_surface *s;
133 struct gl_texture_image *ti;
134 uint32_t tx_format, tx_filter, tx_enable;
135
136 if (!ctx->Texture.Unit[i]._ReallyEnabled) {
137 BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(i), 1);
138 OUT_RING(chan, 0);
139 return;
140 }
141
142 t = ctx->Texture.Unit[i]._Current;
143 s = &to_nouveau_texture(t)->surfaces[t->BaseLevel];
144 ti = t->Image[0][t->BaseLevel];
145
146 if (!nouveau_texture_validate(ctx, t))
147 return;
148
149 /* Recompute the texturing registers. */
150 tx_format = nvgl_wrap_mode(t->WrapT) << 28
151 | nvgl_wrap_mode(t->WrapS) << 24
152 | ti->HeightLog2 << 20
153 | ti->WidthLog2 << 16
154 | 5 << 4 | 1 << 12;
155
156 tx_filter = nvgl_filter_mode(t->MagFilter) << 28
157 | nvgl_filter_mode(t->MinFilter) << 24;
158
159 tx_enable = NV10TCL_TX_ENABLE_ENABLE
160 | log2i(t->MaxAnisotropy) << 4;
161
162 if (t->Target == GL_TEXTURE_RECTANGLE) {
163 BEGIN_RING(chan, celsius, NV10TCL_TX_NPOT_PITCH(i), 1);
164 OUT_RING(chan, s->pitch << 16);
165 BEGIN_RING(chan, celsius, NV10TCL_TX_NPOT_SIZE(i), 1);
166 OUT_RING(chan, align(s->width, 2) << 16 | s->height);
167
168 tx_format |= get_tex_format_rect(ti);
169 } else {
170 tx_format |= get_tex_format_pot(ti);
171 }
172
173 if (t->MinFilter != GL_NEAREST &&
174 t->MinFilter != GL_LINEAR) {
175 int lod_min = t->MinLod;
176 int lod_max = MIN2(t->MaxLod, t->_MaxLambda);
177 int lod_bias = t->LodBias
178 + ctx->Texture.Unit[i].LodBias;
179
180 lod_max = CLAMP(lod_max, 0, 15);
181 lod_min = CLAMP(lod_min, 0, 15);
182 lod_bias = CLAMP(lod_bias, 0, 15);
183
184 tx_format |= NV10TCL_TX_FORMAT_MIPMAP;
185 tx_filter |= lod_bias << 8;
186 tx_enable |= lod_min << 26
187 | lod_max << 14;
188 }
189
190 /* Write it to the hardware. */
191 nouveau_bo_mark(bctx, celsius, NV10TCL_TX_FORMAT(i),
192 s->bo, tx_format, 0,
193 NV10TCL_TX_FORMAT_DMA0,
194 NV10TCL_TX_FORMAT_DMA1,
195 bo_flags | NOUVEAU_BO_OR);
196
197 nouveau_bo_markl(bctx, celsius, NV10TCL_TX_OFFSET(i),
198 s->bo, 0, bo_flags);
199
200 BEGIN_RING(chan, celsius, NV10TCL_TX_FILTER(i), 1);
201 OUT_RING(chan, tx_filter);
202
203 BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(i), 1);
204 OUT_RING(chan, tx_enable);
205 }
206