src/mesa/drivers/dri/r200/r200_ioctl.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include <sched.h>
  36 #include <errno.h>
  37
  38 #include "main/glheader.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/context.h"
  42 #include "swrast/swrast.h"
  43
  44
  45
  46 #include "radeon_common.h"
  47 #include "radeon_lock.h"
  48 #include "r200_context.h"
  49 #include "r200_ioctl.h"
  50 #include "radeon_reg.h"
  51
  52 #include "vblank.h"
  53
  54 #define R200_TIMEOUT             512
  55 #define R200_IDLE_RETRY           16
  56
  57 static void r200KernelClear(GLcontext *ctx, GLuint flags)
  58 {
  59    r200ContextPtr rmesa = R200_CONTEXT(ctx);
  60    __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
  61    GLint cx, cy, cw, ch, ret;
  62    GLuint i;
  63
  64    radeonEmitState(&rmesa->radeon);
  65
  66    LOCK_HARDWARE( &rmesa->radeon );
  67
  68    /* Throttle the number of clear ioctls we do.
  69     */
  70    while ( 1 ) {
  71       drm_radeon_getparam_t gp;
  72       int ret;
  73       int clear;
  74
  75       gp.param = RADEON_PARAM_LAST_CLEAR;
  76       gp.value = (int *)&clear;
  77       ret = drmCommandWriteRead( rmesa->radeon.dri.fd,
  78                       DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
  79
  80       if ( ret ) {
  81          fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
  82          exit(1);
  83       }
  84
  85       /* Clear throttling needs more thought.
  86        */
  87       if ( rmesa->radeon.sarea->last_clear - clear <= 25 ) {
  88          break;
  89       }
  90
  91       if (rmesa->radeon.do_usleeps) {
  92          UNLOCK_HARDWARE( &rmesa->radeon );
  93          DO_USLEEP( 1 );
  94          LOCK_HARDWARE( &rmesa->radeon );
  95       }
  96    }
  97
  98    /* Send current state to the hardware */
  99    rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
 100
 101
 102   /* compute region after locking: */
 103    cx = ctx->DrawBuffer->_Xmin;
 104    cy = ctx->DrawBuffer->_Ymin;
 105    cw = ctx->DrawBuffer->_Xmax - cx;
 106    ch = ctx->DrawBuffer->_Ymax - cy;
 107
 108    /* Flip top to bottom */
 109    cx += dPriv->x;
 110    cy  = dPriv->y + dPriv->h - cy - ch;
 111    for ( i = 0 ; i < dPriv->numClipRects ; ) {
 112       GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
 113       drm_clip_rect_t *box = dPriv->pClipRects;
 114       drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
 115       drm_radeon_clear_t clear;
 116       drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
 117       GLint n = 0;
 118
 119       if (cw != dPriv->w || ch != dPriv->h) {
 120          /* clear subregion */
 121          for ( ; i < nr ; i++ ) {
 122             GLint x = box[i].x1;
 123             GLint y = box[i].y1;
 124             GLint w = box[i].x2 - x;
 125             GLint h = box[i].y2 - y;
 126
 127             if ( x < cx ) w -= cx - x, x = cx;
 128             if ( y < cy ) h -= cy - y, y = cy;
 129             if ( x + w > cx + cw ) w = cx + cw - x;
 130             if ( y + h > cy + ch ) h = cy + ch - y;
 131             if ( w <= 0 ) continue;
 132             if ( h <= 0 ) continue;
 133
 134             b->x1 = x;
 135             b->y1 = y;
 136             b->x2 = x + w;
 137             b->y2 = y + h;
 138             b++;
 139             n++;
 140          }
 141       } else {
 142          /* clear whole window */
 143          for ( ; i < nr ; i++ ) {
 144             *b++ = box[i];
 145             n++;
 146          }
 147       }
 148
 149       rmesa->radeon.sarea->nbox = n;
 150
 151       clear.flags       = flags;
 152       clear.clear_color = rmesa->radeon.state.color.clear;
 153       clear.clear_depth = rmesa->radeon.state.depth.clear;      /* needed for hyperz */
 154       clear.color_mask  = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
 155       clear.depth_mask  = rmesa->radeon.state.stencil.clear;
 156       clear.depth_boxes = depth_boxes;
 157
 158       n--;
 159       b = rmesa->radeon.sarea->boxes;
 160       for ( ; n >= 0 ; n-- ) {
 161          depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
 162          depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
 163          depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
 164          depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
 165          depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear;
 166       }
 167
 168       ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR,
 169                              &clear, sizeof(clear));
 170
 171
 172       if ( ret ) {
 173          UNLOCK_HARDWARE( &rmesa->radeon );
 174          fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret );
 175          exit( 1 );
 176       }
 177    }
 178    UNLOCK_HARDWARE( &rmesa->radeon );
 179 }
 180 /* ================================================================
 181  * Buffer clear
 182  */
 183 static void r200Clear( GLcontext *ctx, GLbitfield mask )
 184 {
 185    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 186    __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
 187    GLuint flags = 0;
 188    GLuint color_mask = 0;
 189    GLuint orig_mask = mask;
 190
 191    if ( R200_DEBUG & RADEON_IOCTL ) {
 192            if (rmesa->radeon.sarea)
 193                fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage);
 194            else
 195                fprintf( stderr, "r200Clear %x radeon->sarea is NULL\n", mask);
 196    }
 197
 198    {
 199       LOCK_HARDWARE( &rmesa->radeon );
 200       UNLOCK_HARDWARE( &rmesa->radeon );
 201       if ( dPriv->numClipRects == 0 )
 202          return;
 203    }
 204
 205    radeonFlush( ctx );
 206
 207    if ( mask & BUFFER_BIT_FRONT_LEFT ) {
 208       flags |= RADEON_FRONT;
 209       color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
 210       mask &= ~BUFFER_BIT_FRONT_LEFT;
 211    }
 212
 213    if ( mask & BUFFER_BIT_BACK_LEFT ) {
 214       flags |= RADEON_BACK;
 215       color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
 216       mask &= ~BUFFER_BIT_BACK_LEFT;
 217    }
 218
 219    if ( mask & BUFFER_BIT_DEPTH ) {
 220       flags |= RADEON_DEPTH;
 221       mask &= ~BUFFER_BIT_DEPTH;
 222    }
 223
 224    if ( (mask & BUFFER_BIT_STENCIL) ) {
 225       flags |= RADEON_STENCIL;
 226       mask &= ~BUFFER_BIT_STENCIL;
 227    }
 228
 229    if ( mask ) {
 230       if (R200_DEBUG & RADEON_FALLBACKS)
 231          fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
 232       _swrast_Clear( ctx, mask );
 233    }
 234
 235    if ( !flags )
 236       return;
 237
 238    if (rmesa->using_hyperz) {
 239       flags |= RADEON_USE_COMP_ZBUF;
 240 /*      if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
 241          flags |= RADEON_USE_HIERZ; */
 242       if (!((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
 243             ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) {
 244           flags |= RADEON_CLEAR_FASTZ;
 245       }
 246    }
 247
 248    if (rmesa->radeon.radeonScreen->kernel_mm)
 249       radeonUserClear(ctx, orig_mask);
 250    else {
 251       r200KernelClear(ctx, flags);
 252       rmesa->radeon.hw.all_dirty = GL_TRUE;
 253    }
 254 }
 255
 256 GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
 257                            GLint size )
 258 {
 259    ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map;
 260    int valid = (size >= 0 &&
 261                 offset >= 0 &&
 262                 offset + size < rmesa->radeon.radeonScreen->gartTextures.size);
 263
 264    if (R200_DEBUG & RADEON_IOCTL)
 265       fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid );
 266
 267    return valid;
 268 }
 269
 270
 271 GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer )
 272 {
 273    ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map;
 274
 275    if (offset < 0 || offset > rmesa->radeon.radeonScreen->gartTextures.size)
 276       return ~0;
 277    else
 278       return rmesa->radeon.radeonScreen->gart_texture_offset + offset;
 279 }
 280
 281
 282
 283 void r200InitIoctlFuncs( struct dd_function_table *functions )
 284 {
 285     functions->Clear = r200Clear;
 286     functions->Finish = radeonFinish;
 287     functions->Flush = radeonFlush;
 288 }
 289