src/mesa/drivers/dri/r200/r200_ioctl.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #ifndef __R200_IOCTL_H__
  36 #define __R200_IOCTL_H__
  37
  38 #include "main/simple_list.h"
  39 #include "radeon_dri.h"
  40
  41 #include "radeon_bocs_wrapper.h"
  42
  43 #include "xf86drm.h"
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count);
  48 extern void r200EmitVertexAOS( r200ContextPtr rmesa,
  49                                GLuint vertex_size,
  50                                struct radeon_bo *bo,
  51                                GLuint offset );
  52
  53 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
  54                                 GLuint primitive,
  55                                 GLuint vertex_nr );
  56
  57 extern void r200FlushElts(struct gl_context *ctx);
  58
  59 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  60                                            GLuint primitive,
  61                                            GLuint min_nr );
  62
  63 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
  64
  65 extern void r200InitIoctlFuncs( struct dd_function_table *functions );
  66
  67 extern GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
  68                                    GLint size );
  69
  70 extern GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa,
  71                                          const GLvoid *pointer );
  72
  73 void r200SetUpAtomList( r200ContextPtr rmesa );
  74
  75 /* ================================================================
  76  * Helper macros:
  77  */
  78
  79 /* Close off the last primitive, if it exists.
  80  */
  81 #define R200_NEWPRIM( rmesa )                   \
  82 do {                                            \
  83    if ( rmesa->radeon.dma.flush )                       \
  84       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );   \
  85 } while (0)
  86
  87 /* Can accomodate several state changes and primitive changes without
  88  * actually firing the buffer.
  89  */
  90 #define R200_STATECHANGE( rmesa, ATOM )                 \
  91 do {                                                            \
  92    R200_NEWPRIM( rmesa );                                       \
  93    rmesa->hw.ATOM.dirty = GL_TRUE;                              \
  94    rmesa->radeon.hw.is_dirty = GL_TRUE;                         \
  95 } while (0)
  96
  97 #define R200_SET_STATE( rmesa, ATOM, index, newvalue )  \
  98   do {  \
  99     uint32_t __index = (index); \
 100     uint32_t __dword = (newvalue); \
 101     if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \
 102       R200_STATECHANGE( (rmesa), ATOM ); \
 103       (rmesa)->hw.ATOM.cmd[__index] = __dword; \
 104     } \
 105   } while(0)
 106
 107 #define R200_DB_STATE( ATOM )                           \
 108    memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd,  \
 109            rmesa->hw.ATOM.cmd_size * 4)
 110
 111 static INLINE int R200_DB_STATECHANGE(
 112    r200ContextPtr rmesa,
 113    struct radeon_state_atom *atom )
 114 {
 115    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
 116       GLuint *tmp;
 117       R200_NEWPRIM( rmesa );
 118       atom->dirty = GL_TRUE;
 119       rmesa->radeon.hw.is_dirty = GL_TRUE;
 120       tmp = atom->cmd;
 121       atom->cmd = atom->lastcmd;
 122       atom->lastcmd = tmp;
 123       return 1;
 124    }
 125    else
 126       return 0;
 127 }
 128
 129
 130 /* Command lengths.  Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
 131  * are available, you will also be adding an rmesa->state.max_state_size because
 132  * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
 133  */
 134 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2))
 135 #define VERT_AOS_BUFSZ  (5)
 136 #define ELTS_BUFSZ(nr)  (12 + nr * 2)
 137 #define VBUF_BUFSZ      (3)
 138 #define SCISSOR_BUFSZ   (8)
 139 #define INDEX_BUFSZ     (8+2)
 140
 141 static inline uint32_t cmdpacket3(int cmd_type)
 142 {
 143   drm_radeon_cmd_header_t cmd;
 144
 145   cmd.i = 0;
 146   cmd.header.cmd_type = cmd_type;
 147
 148   return (uint32_t)cmd.i;
 149
 150 }
 151
 152 #define OUT_BATCH_PACKET3(packet, num_extra) do {             \
 153     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 154       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3));                                      \
 155       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 156     } else {                                                  \
 157       OUT_BATCH(CP_PACKET2);                                  \
 158       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 159     }                                                         \
 160   } while(0)
 161
 162 #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do {        \
 163     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 164       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP));         \
 165       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 166     } else {                                                  \
 167       OUT_BATCH(CP_PACKET2);                                  \
 168       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 169     }                                                         \
 170   } while(0)
 171
 172
 173 #endif /* __R200_IOCTL_H__ */