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Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54 #include "radeon_queryobj.h"
55
56 #include "xmlpool.h"
57
58 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
59 * 1.3 cmdbuffers allow all previous state to be updated as well as
60 * the tcl scalar and vector areas.
61 */
62 static struct {
63 int start;
64 int len;
65 const char *name;
66 } packet[RADEON_MAX_STATE_PACKETS] = {
67 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
68 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
69 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
70 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
71 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
72 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
73 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
74 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
75 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
76 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
77 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
78 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
79 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
80 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
81 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
82 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
83 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
84 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
85 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
86 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
87 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
88 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
89 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
90 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
91 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
92 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
93 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
94 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
95 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
96 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
97 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
98 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
99 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
100 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
101 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
102 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
103 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
104 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
105 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
106 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
107 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
108 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
109 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
110 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
111 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
112 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
113 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
114 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
115 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
116 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
117 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
118 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
119 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
120 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
121 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
122 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
123 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
124 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
125 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
126 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
127 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
128 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
129 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
130 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
131 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
132 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
133 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
134 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
135 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
136 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
137 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
138 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
139 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
140 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
141 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
142 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
143 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
144 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
145 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
146 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
147 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
148 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
149 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
150 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
151 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
152 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
153 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
154 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
155 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
156 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
157 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
158 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
159 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
160 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
161 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
162 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
163 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
164 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
165 };
166
167 /* =============================================================
168 * State initialization
169 */
170 static int cmdpkt( r200ContextPtr rmesa, int id )
171 {
172 drm_radeon_cmd_header_t h;
173
174 if (rmesa->radeon.radeonScreen->kernel_mm) {
175 return CP_PACKET0(packet[id].start, packet[id].len - 1);
176 } else {
177 h.i = 0;
178 h.packet.cmd_type = RADEON_CMD_PACKET;
179 h.packet.packet_id = id;
180 }
181 return h.i;
182 }
183
184 static int cmdvec( int offset, int stride, int count )
185 {
186 drm_radeon_cmd_header_t h;
187 h.i = 0;
188 h.vectors.cmd_type = RADEON_CMD_VECTORS;
189 h.vectors.offset = offset;
190 h.vectors.stride = stride;
191 h.vectors.count = count;
192 return h.i;
193 }
194
195 /* warning: the count here is divided by 4 compared to other cmds
196 (so it doesn't exceed the char size)! */
197 static int cmdveclinear( int offset, int count )
198 {
199 drm_radeon_cmd_header_t h;
200 h.i = 0;
201 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
202 h.veclinear.addr_lo = offset & 0xff;
203 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
204 h.veclinear.count = count;
205 return h.i;
206 }
207
208 static int cmdscl( int offset, int stride, int count )
209 {
210 drm_radeon_cmd_header_t h;
211 h.i = 0;
212 h.scalars.cmd_type = RADEON_CMD_SCALARS;
213 h.scalars.offset = offset;
214 h.scalars.stride = stride;
215 h.scalars.count = count;
216 return h.i;
217 }
218
219 static int cmdscl2( int offset, int stride, int count )
220 {
221 drm_radeon_cmd_header_t h;
222 h.i = 0;
223 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
224 h.scalars.offset = offset - 0x100;
225 h.scalars.stride = stride;
226 h.scalars.count = count;
227 return h.i;
228 }
229
230 /**
231 * Check functions are used to check if state is active.
232 * If it is active check function returns maximum emit size.
233 */
234 #define CHECK( NM, FLAG, ADD ) \
235 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
236 { \
237 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
238 (void) rmesa; \
239 return (FLAG) ? atom->cmd_size + (ADD) : 0; \
240 }
241
242 #define TCL_CHECK( NM, FLAG, ADD ) \
243 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
244 { \
245 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
246 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
247 }
248
249 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
250 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
251 { \
252 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
253 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
254 }
255
256 #define VP_CHECK( NM, FLAG, ADD ) \
257 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
258 { \
259 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
260 (void) atom; \
261 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
262 }
263
264 CHECK( always, GL_TRUE, 0 )
265 CHECK( always_add4, GL_TRUE, 4 )
266 CHECK( never, GL_FALSE, 0 )
267 CHECK( tex_any, ctx->Texture._EnabledUnits, 0 )
268 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled), 0 );
269 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
270 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
271 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
272 CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
273 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
274 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE )
275 TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 )
276 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
277 TCL_CHECK( tcl, GL_TRUE, 0 )
278 TCL_CHECK( tcl_add8, GL_TRUE, 8 )
279 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
280 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded, 0 )
281 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
282 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 0 )
283 TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 )
284 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
285 TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 )
286 TCL_CHECK( tcl_light_add8, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 8 )
287 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 0 )
288 TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 )
289 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 )
290 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 )
291 VP_CHECK( tcl_vp, GL_TRUE, 0 )
292 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 )
293 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 0 )
294 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 0 )
295 VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 )
296 VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 )
297
298 #define OUT_VEC(hdr, data) do { \
299 drm_radeon_cmd_header_t h; \
300 h.i = hdr; \
301 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
302 OUT_BATCH(0); \
303 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
304 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
305 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
306 OUT_BATCH_TABLE((data), h.vectors.count); \
307 } while(0)
308
309 #define OUT_VECLINEAR(hdr, data) do { \
310 drm_radeon_cmd_header_t h; \
311 uint32_t _start, _sz; \
312 h.i = hdr; \
313 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
314 _sz = h.veclinear.count * 4; \
315 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
316 BEGIN_BATCH_NO_AUTOSTATE(dwords); \
317 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
318 OUT_BATCH(0); \
319 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
320 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
321 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
322 OUT_BATCH_TABLE((data), _sz); \
323 END_BATCH(); \
324 } \
325 } while(0)
326
327 #define OUT_SCL(hdr, data) do { \
328 drm_radeon_cmd_header_t h; \
329 h.i = hdr; \
330 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
331 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
332 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
333 OUT_BATCH_TABLE((data), h.scalars.count); \
334 } while(0)
335
336 #define OUT_SCL2(hdr, data) do { \
337 drm_radeon_cmd_header_t h; \
338 h.i = hdr; \
339 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
340 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
341 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
342 OUT_BATCH_TABLE((data), h.scalars.count); \
343 } while(0)
344 static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom)
345 {
346 r200ContextPtr r200 = R200_CONTEXT(ctx);
347 struct radeon_renderbuffer *rrb;
348 rrb = radeon_get_colorbuffer(&r200->radeon);
349 if (!rrb || !rrb->bo)
350 return 0;
351 return atom->cmd_size;
352 }
353
354 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
355 {
356 r200ContextPtr r200 = R200_CONTEXT(ctx);
357 BATCH_LOCALS(&r200->radeon);
358 uint32_t dwords = atom->check(ctx, atom);
359
360 BEGIN_BATCH_NO_AUTOSTATE(dwords);
361 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
362 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
363 END_BATCH();
364 }
365
366 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
367 {
368 r200ContextPtr r200 = R200_CONTEXT(ctx);
369 BATCH_LOCALS(&r200->radeon);
370 uint32_t dwords = atom->check(ctx, atom);
371
372 BEGIN_BATCH_NO_AUTOSTATE(dwords);
373 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
374 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
375 END_BATCH();
376 }
377
378 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
379 {
380 r200ContextPtr r200 = R200_CONTEXT(ctx);
381 BATCH_LOCALS(&r200->radeon);
382 uint32_t dwords = atom->check(ctx, atom);
383
384 BEGIN_BATCH_NO_AUTOSTATE(dwords);
385 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
386 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
387 END_BATCH();
388 }
389
390 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r200ContextPtr r200 = R200_CONTEXT(ctx);
393 BATCH_LOCALS(&r200->radeon);
394 uint32_t dwords = atom->check(ctx, atom);
395
396 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
397 }
398
399 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
400 {
401 r200ContextPtr r200 = R200_CONTEXT(ctx);
402 BATCH_LOCALS(&r200->radeon);
403 uint32_t dwords = atom->check(ctx, atom);
404
405 BEGIN_BATCH_NO_AUTOSTATE(dwords);
406 OUT_SCL(atom->cmd[0], atom->cmd+1);
407 END_BATCH();
408 }
409
410
411 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
412 {
413 r200ContextPtr r200 = R200_CONTEXT(ctx);
414 BATCH_LOCALS(&r200->radeon);
415 uint32_t dwords = atom->check(ctx, atom);
416
417 BEGIN_BATCH_NO_AUTOSTATE(dwords);
418 OUT_VEC(atom->cmd[0], atom->cmd+1);
419 END_BATCH();
420 }
421
422 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
423 {
424 r200ContextPtr r200 = R200_CONTEXT(ctx);
425 BATCH_LOCALS(&r200->radeon);
426 struct radeon_renderbuffer *rrb;
427 uint32_t cbpitch;
428 uint32_t zbpitch, depth_fmt;
429 uint32_t dwords = atom->check(ctx, atom);
430
431 /* output the first 7 bytes of context */
432 BEGIN_BATCH_NO_AUTOSTATE(dwords);
433 OUT_BATCH_TABLE(atom->cmd, 5);
434
435 rrb = radeon_get_depthbuffer(&r200->radeon);
436 if (!rrb) {
437 OUT_BATCH(0);
438 OUT_BATCH(0);
439 } else {
440 zbpitch = (rrb->pitch / rrb->cpp);
441 if (r200->using_hyperz)
442 zbpitch |= RADEON_DEPTH_HYPERZ;
443 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
444 OUT_BATCH(zbpitch);
445 if (rrb->cpp == 4)
446 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
447 else
448 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
449 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
450 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
451 }
452
453 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
454 OUT_BATCH(atom->cmd[CTX_CMD_1]);
455 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
456
457 rrb = radeon_get_colorbuffer(&r200->radeon);
458 if (!rrb || !rrb->bo) {
459 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
460 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
461 } else {
462 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
463 if (rrb->cpp == 4)
464 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
465 else
466 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
467
468 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
469 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
470 }
471
472 OUT_BATCH(atom->cmd[CTX_CMD_2]);
473
474 if (!rrb || !rrb->bo) {
475 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
476 } else {
477 cbpitch = (rrb->pitch / rrb->cpp);
478 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
479 cbpitch |= R200_COLOR_TILE_ENABLE;
480 OUT_BATCH(cbpitch);
481 }
482
483 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
484 OUT_BATCH_TABLE((atom->cmd + 14), 4);
485
486 END_BATCH();
487 }
488
489 static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
490 {
491 r200ContextPtr r200 = R200_CONTEXT(ctx);
492 struct radeon_renderbuffer *rrb, *drb;
493 uint32_t dwords;
494
495 rrb = radeon_get_colorbuffer(&r200->radeon);
496 if (!rrb || !rrb->bo) {
497 return 0;
498 }
499
500 drb = radeon_get_depthbuffer(&r200->radeon);
501
502 dwords = 10;
503 if (drb)
504 dwords += 6;
505 if (rrb)
506 dwords += 8;
507 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
508 dwords += 4;
509
510
511 return dwords;
512 }
513
514 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
515 {
516 r200ContextPtr r200 = R200_CONTEXT(ctx);
517 BATCH_LOCALS(&r200->radeon);
518 struct radeon_renderbuffer *rrb, *drb;
519 uint32_t cbpitch = 0;
520 uint32_t zbpitch = 0;
521 uint32_t dwords = atom->check(ctx, atom);
522 uint32_t depth_fmt;
523
524 rrb = radeon_get_colorbuffer(&r200->radeon);
525 if (!rrb || !rrb->bo) {
526 return;
527 }
528
529 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
530 if (rrb->cpp == 4)
531 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
532 else switch (rrb->base._ActualFormat) {
533 case GL_RGB5:
534 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
535 break;
536 case GL_RGBA4:
537 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
538 break;
539 case GL_RGB5_A1:
540 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
541 break;
542 }
543
544 cbpitch = (rrb->pitch / rrb->cpp);
545 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
546 cbpitch |= R200_COLOR_TILE_ENABLE;
547
548 drb = radeon_get_depthbuffer(&r200->radeon);
549 if (drb) {
550 zbpitch = (drb->pitch / drb->cpp);
551 if (drb->cpp == 4)
552 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
553 else
554 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
555 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
556 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
557 }
558
559 /* output the first 7 bytes of context */
560 BEGIN_BATCH_NO_AUTOSTATE(dwords);
561
562 /* In the CS case we need to split this up */
563 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
564 OUT_BATCH_TABLE((atom->cmd + 1), 4);
565
566 if (drb) {
567 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
568 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
569
570 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
571 OUT_BATCH(zbpitch);
572 }
573
574 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
575 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
576 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
577 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
578 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
579
580
581 if (rrb) {
582 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
583 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
584
585 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
586 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
587 }
588
589 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
590 OUT_BATCH_TABLE((atom->cmd + 14), 4);
591 }
592
593 END_BATCH();
594 }
595
596 static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
597 {
598 r200ContextPtr r200 = R200_CONTEXT(ctx);
599 uint32_t dwords = atom->cmd_size + 2;
600 int i = atom->idx;
601 radeonTexObj *t = r200->state.texture.unit[i].texobj;
602 if (!(t && t->mt && !t->image_override))
603 dwords -= 2;
604
605 return dwords;
606 }
607
608 static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
609 {
610 r200ContextPtr r200 = R200_CONTEXT(ctx);
611 /** XOR is bit flip operation so use it for finding pair */
612 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
613 return 0;
614
615 return get_tex_size(ctx, atom);
616 }
617
618 static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
619 {
620 r200ContextPtr r200 = R200_CONTEXT(ctx);
621 if (!(r200->state.texture.unit[atom->idx].unitneeded))
622 return 0;
623
624 return get_tex_size(ctx, atom);
625 }
626
627
628 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
629 {
630 r200ContextPtr r200 = R200_CONTEXT(ctx);
631 BATCH_LOCALS(&r200->radeon);
632 uint32_t dwords = atom->check(ctx, atom);
633 int i = atom->idx;
634 radeonTexObj *t = r200->state.texture.unit[i].texobj;
635
636 BEGIN_BATCH_NO_AUTOSTATE(dwords);
637 /* is this ok even with drm older than 1.18? */
638 OUT_BATCH_TABLE(atom->cmd, 10);
639
640 if (t && t->mt && !t->image_override) {
641 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
642 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
643 } else if (!t) {
644 /* workaround for old CS mechanism */
645 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
646 } else {
647 OUT_BATCH(t->override_offset);
648 }
649
650 END_BATCH();
651 }
652
653 static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
654 {
655 r200ContextPtr r200 = R200_CONTEXT(ctx);
656 uint32_t dwords = atom->cmd_size + 2;
657 int hastexture = 1;
658 int i = atom->idx;
659 radeonTexObj *t = r200->state.texture.unit[i].texobj;
660 if (!t)
661 hastexture = 0;
662 else {
663 if (!t->mt && !t->bo)
664 hastexture = 0;
665 }
666
667 if (!hastexture)
668 dwords -= 4;
669 return dwords;
670 }
671
672 static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
673 {
674 r200ContextPtr r200 = R200_CONTEXT(ctx);
675 /** XOR is bit flip operation so use it for finding pair */
676 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
677 return 0;
678
679 return get_tex_mm_size(ctx, atom);
680 }
681
682 static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
683 {
684 r200ContextPtr r200 = R200_CONTEXT(ctx);
685 if (!(r200->state.texture.unit[atom->idx].unitneeded))
686 return 0;
687
688 return get_tex_mm_size(ctx, atom);
689 }
690
691
692 static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
693 {
694 r200ContextPtr r200 = R200_CONTEXT(ctx);
695 BATCH_LOCALS(&r200->radeon);
696 uint32_t dwords = atom->check(ctx, atom);
697 int i = atom->idx;
698 radeonTexObj *t = r200->state.texture.unit[i].texobj;
699 if (!r200->state.texture.unit[i].unitneeded)
700 dwords -= 4;
701 BEGIN_BATCH_NO_AUTOSTATE(dwords);
702
703 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
704 OUT_BATCH_TABLE((atom->cmd + 1), 8);
705
706 if (dwords > atom->cmd_size) {
707 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
708 if (t->mt && !t->image_override) {
709 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
710 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
711 } else {
712 if (t->bo)
713 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
714 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
715 }
716 }
717 END_BATCH();
718 }
719
720
721 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
722 {
723 r200ContextPtr r200 = R200_CONTEXT(ctx);
724 BATCH_LOCALS(&r200->radeon);
725 uint32_t dwords = atom->check(ctx, atom);
726 int i = atom->idx, j;
727 radeonTexObj *t = r200->state.texture.unit[i].texobj;
728 radeon_mipmap_level *lvl;
729
730 if (!(t && !t->image_override))
731 dwords = 2;
732
733 BEGIN_BATCH_NO_AUTOSTATE(dwords);
734 /* XXX that size won't really match with image_override... */
735 OUT_BATCH_TABLE(atom->cmd, 2);
736
737 if (t && !t->image_override) {
738 lvl = &t->mt->levels[0];
739 OUT_BATCH_TABLE((atom->cmd + 2), 1);
740 for (j = 1; j <= 5; j++) {
741 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
742 RADEON_GEM_DOMAIN_VRAM, 0, 0);
743 }
744 }
745 END_BATCH();
746 }
747
748 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
749 {
750 r200ContextPtr r200 = R200_CONTEXT(ctx);
751 BATCH_LOCALS(&r200->radeon);
752 uint32_t dwords = atom->check(ctx, atom);
753 int i = atom->idx, j;
754 radeonTexObj *t = r200->state.texture.unit[i].texobj;
755 radeon_mipmap_level *lvl;
756 if (!(t && !t->image_override))
757 dwords = 2;
758
759 BEGIN_BATCH_NO_AUTOSTATE(dwords);
760 OUT_BATCH_TABLE(atom->cmd, 2);
761
762 if (t && !t->image_override) {
763 lvl = &t->mt->levels[0];
764 for (j = 1; j <= 5; j++) {
765 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
766 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
767 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
768 }
769 }
770 END_BATCH();
771 }
772
773 /* Initialize the context's hardware state.
774 */
775 void r200InitState( r200ContextPtr rmesa )
776 {
777 GLcontext *ctx = rmesa->radeon.glCtx;
778 GLuint i;
779
780 rmesa->radeon.state.color.clear = 0x00000000;
781
782 switch ( ctx->Visual.depthBits ) {
783 case 16:
784 rmesa->radeon.state.depth.clear = 0x0000ffff;
785 rmesa->radeon.state.stencil.clear = 0x00000000;
786 break;
787 case 24:
788 default:
789 rmesa->radeon.state.depth.clear = 0x00ffffff;
790 rmesa->radeon.state.stencil.clear = 0xffff0000;
791 break;
792 }
793
794 rmesa->radeon.Fallback = 0;
795
796 rmesa->radeon.hw.max_state_size = 0;
797
798 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
799 do { \
800 rmesa->hw.ATOM.cmd_size = SZ; \
801 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
802 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
803 rmesa->hw.ATOM.name = NM; \
804 rmesa->hw.ATOM.idx = IDX; \
805 if (check_##CHK != check_never) { \
806 rmesa->hw.ATOM.check = check_##CHK; \
807 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
808 } else { \
809 rmesa->hw.ATOM.check = NULL; \
810 } \
811 rmesa->hw.ATOM.dirty = GL_FALSE; \
812 } while (0)
813
814
815 /* Allocate state buffers:
816 */
817 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
818 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
819 else
820 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
821
822 if (rmesa->radeon.radeonScreen->kernel_mm)
823 {
824 rmesa->hw.ctx.emit = ctx_emit_cs;
825 rmesa->hw.ctx.check = check_always_ctx;
826 }
827 else
828 {
829 rmesa->hw.ctx.emit = ctx_emit;
830 }
831 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
832 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
833 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
834 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
835 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
836 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
837 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
838 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
839 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
840 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
841 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
842 {
843 int state_size = TEX_STATE_SIZE_NEWDRM;
844 if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) {
845 state_size = TEX_STATE_SIZE_OLDDRM;
846 }
847 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
848 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
849 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
850 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
851 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
852 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
853 }
854 else {
855 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
856 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
857 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
858 }
859 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
860 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
861 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
862 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
863 if (!rmesa->radeon.radeonScreen->kernel_mm)
864 {
865 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
866 rmesa->hw.tex[0].check = check_tex_pair;
867 rmesa->hw.tex[1].check = check_tex_pair;
868 } else {
869 rmesa->hw.tex[0].check = check_tex;
870 rmesa->hw.tex[1].check = check_tex;
871 }
872 rmesa->hw.tex[2].check = check_tex;
873 rmesa->hw.tex[3].check = check_tex;
874 rmesa->hw.tex[4].check = check_tex;
875 rmesa->hw.tex[5].check = check_tex;
876 }
877 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
878 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
879 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
880 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
881 } else {
882 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 );
883 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
884 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
885 }
886 }
887 }
888 /* polygon stipple is done with irq for non-kms */
889 if (rmesa->radeon.radeonScreen->kernel_mm) {
890 ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
891 }
892
893 for (i = 0; i < 6; i++)
894 if (rmesa->radeon.radeonScreen->kernel_mm)
895 rmesa->hw.tex[i].emit = tex_emit_mm;
896 else
897 rmesa->hw.tex[i].emit = tex_emit;
898 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
899 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
900 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
901 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
902 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
903 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
904 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
905 for (i = 0; i < 6; i++)
906 if (rmesa->radeon.radeonScreen->kernel_mm) {
907 rmesa->hw.cube[i].emit = cube_emit_cs;
908 rmesa->hw.cube[i].check = check_tex_cube_cs;
909 } else
910 rmesa->hw.cube[i].emit = cube_emit;
911 }
912 else {
913 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
914 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
915 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
916 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
917 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
918 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
919 }
920
921 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
922 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
923 if (rmesa->radeon.radeonScreen->kernel_mm) {
924 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
925 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
926 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
927 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
928 } else {
929 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
930 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
931 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
932 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
933 }
934 }
935 else {
936 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
937 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
938 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
939 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
940 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
941 }
942 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
943 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
944 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
945 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
946 if (rmesa->radeon.radeonScreen->kernel_mm) {
947 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 );
948 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 );
949 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 );
950 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 );
951 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 );
952 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
953 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 );
954 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
955 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 );
956 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 );
957 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
958 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 );
959 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 );
960 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 );
961 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 );
962 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
963 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
964 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
965 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
966 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
967 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
968 ALLOC_STATE( lit[0], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-0", 0 );
969 ALLOC_STATE( lit[1], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-1", 1 );
970 ALLOC_STATE( lit[2], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-2", 2 );
971 ALLOC_STATE( lit[3], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-3", 3 );
972 ALLOC_STATE( lit[4], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-4", 4 );
973 ALLOC_STATE( lit[5], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-5", 5 );
974 ALLOC_STATE( lit[6], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-6", 6 );
975 ALLOC_STATE( lit[7], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-7", 7 );
976 ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 );
977 } else {
978 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
979 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
980 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
981 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
982 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
983 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
984 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
985 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
986 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
987 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
988 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
989 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
990 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
991 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
992 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
993 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
994 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
995 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
996 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
997 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
998 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
999 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
1000 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
1001 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
1002 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
1003 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
1004 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
1005 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
1006 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
1007 ALLOC_STATE( sci, never, SCI_STATE_SIZE, "SCI/scissor", 0 );
1008 }
1009 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
1010 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
1011 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
1012 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
1013 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
1014 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
1015 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
1016 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1017 }
1018 else {
1019 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1020 }
1021 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
1022 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1023 if (rmesa->radeon.radeonScreen->kernel_mm)
1024 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1025 else
1026 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1027 }
1028 else {
1029 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1030 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1031 }
1032
1033 r200SetUpAtomList( rmesa );
1034
1035 /* Fill in the packet headers:
1036 */
1037 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
1038 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
1039 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
1040 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
1041 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
1042 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
1043 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
1044 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
1045 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
1046 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
1047 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
1048 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
1049 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
1050 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
1051 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
1052 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
1053 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
1054 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
1055 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
1056 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
1057 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1058 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
1059 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
1060 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1061 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
1062 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1063 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
1064 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1065 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
1066 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1067 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
1068 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1069 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
1070 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1071 } else {
1072 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
1073 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1074 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
1075 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1076 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
1077 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1078 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
1079 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1080 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
1081 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1082 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
1083 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1084 }
1085 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
1086 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
1087 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
1088 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
1089 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
1090 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
1091 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
1092 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
1093 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
1094 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
1095 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
1096 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
1097 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
1098 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
1099 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
1100 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
1101 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
1102 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
1103 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
1104 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
1105 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
1106 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
1107 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
1108 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
1109 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
1110 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
1111 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
1112 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
1113 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
1114 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
1115 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
1116 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
1117 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
1118
1119 rmesa->hw.sci.cmd[SCI_CMD_0] = CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0);
1120 rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
1121 rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
1122
1123 if (rmesa->radeon.radeonScreen->kernel_mm) {
1124
1125 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
1126 rmesa->hw.stp.cmd[STP_DATA_0] = 0;
1127 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
1128
1129 rmesa->hw.mtl[0].emit = mtl_emit;
1130 rmesa->hw.mtl[1].emit = mtl_emit;
1131
1132 rmesa->hw.vpi[0].emit = veclinear_emit;
1133 rmesa->hw.vpi[1].emit = veclinear_emit;
1134 rmesa->hw.vpp[0].emit = veclinear_emit;
1135 rmesa->hw.vpp[1].emit = veclinear_emit;
1136
1137 rmesa->hw.grd.emit = scl_emit;
1138 rmesa->hw.fog.emit = vec_emit;
1139 rmesa->hw.glt.emit = vec_emit;
1140 rmesa->hw.eye.emit = vec_emit;
1141
1142 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
1143 rmesa->hw.mat[i].emit = vec_emit;
1144
1145 for (i = 0; i < 8; i++)
1146 rmesa->hw.lit[i].emit = lit_emit;
1147
1148 for (i = 0; i < 6; i++)
1149 rmesa->hw.ucp[i].emit = vec_emit;
1150
1151 rmesa->hw.ptp.emit = ptp_emit;
1152 }
1153
1154
1155
1156 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
1157 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
1158 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
1159 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
1160 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
1161 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
1162 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
1163 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
1164
1165 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
1166 cmdveclinear( R200_PVS_PROG0, 64 );
1167 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
1168 cmdveclinear( R200_PVS_PROG1, 64 );
1169 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
1170 cmdveclinear( R200_PVS_PARAM0, 96 );
1171 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
1172 cmdveclinear( R200_PVS_PARAM1, 96 );
1173
1174 rmesa->hw.grd.cmd[GRD_CMD_0] =
1175 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
1176 rmesa->hw.fog.cmd[FOG_CMD_0] =
1177 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
1178 rmesa->hw.glt.cmd[GLT_CMD_0] =
1179 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
1180 rmesa->hw.eye.cmd[EYE_CMD_0] =
1181 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
1182
1183 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
1184 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
1185 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1186 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1187 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1188 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1189 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1190 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1191 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1192 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1193 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1194 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1195 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1196 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1197 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1198 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1199 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1200 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1201
1202 for (i = 0 ; i < 8; i++) {
1203 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1204 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1205 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1206 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1207 }
1208
1209 for (i = 0 ; i < 6; i++) {
1210 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1211 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1212 }
1213
1214 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1215 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1216 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1217 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1218
1219 /* Initial Harware state:
1220 */
1221 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1222 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1223
1224 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1225 R200_FOG_USE_SPEC_ALPHA);
1226
1227 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1228
1229 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1230 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1231 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1232
1233 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1234 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1235 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1236 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1237 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1238 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1239 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1240 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1241 }
1242
1243 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1244 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1245
1246 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1247 ((rmesa->radeon.radeonScreen->depthPitch &
1248 R200_DEPTHPITCH_MASK) |
1249 R200_DEPTH_ENDIAN_NO_SWAP);
1250
1251 if (rmesa->using_hyperz)
1252 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1253
1254 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1255 R200_STENCIL_TEST_ALWAYS |
1256 R200_STENCIL_FAIL_KEEP |
1257 R200_STENCIL_ZPASS_KEEP |
1258 R200_STENCIL_ZFAIL_KEEP |
1259 R200_Z_WRITE_ENABLE);
1260
1261 if (rmesa->using_hyperz) {
1262 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1263 R200_Z_DECOMPRESSION_ENABLE;
1264 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1265 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1266 }
1267
1268 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1269 | R200_TEX_BLEND_0_ENABLE);
1270
1271 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1272 case DRI_CONF_DITHER_XERRORDIFFRESET:
1273 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1274 break;
1275 case DRI_CONF_DITHER_ORDERED:
1276 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1277 break;
1278 }
1279 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1280 DRI_CONF_ROUND_ROUND )
1281 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1282 else
1283 rmesa->radeon.state.color.roundEnable = 0;
1284 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1285 DRI_CONF_COLOR_REDUCTION_DITHER )
1286 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1287 else
1288 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1289
1290 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1291 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1292 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1293
1294 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1295 R200_BFACE_SOLID |
1296 R200_FFACE_SOLID |
1297 R200_FLAT_SHADE_VTX_LAST |
1298 R200_DIFFUSE_SHADE_GOURAUD |
1299 R200_ALPHA_SHADE_GOURAUD |
1300 R200_SPECULAR_SHADE_GOURAUD |
1301 R200_FOG_SHADE_GOURAUD |
1302 R200_DISC_FOG_SHADE_GOURAUD |
1303 R200_VTX_PIX_CENTER_OGL |
1304 R200_ROUND_MODE_TRUNC |
1305 R200_ROUND_PREC_8TH_PIX);
1306
1307 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1308 R200_SCISSOR_ENABLE);
1309
1310 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1311
1312 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1313 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1314 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1315
1316 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1317
1318 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1319 ((0x00 << R200_STENCIL_REF_SHIFT) |
1320 (0xff << R200_STENCIL_MASK_SHIFT) |
1321 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1322
1323 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1324 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1325
1326 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1327
1328 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1329 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1330 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1331 R200_STIPPLE_BIG_BIT_ORDER);
1332
1333
1334 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1335 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1336 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1337 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1338 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1339 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1340 #ifdef MESA_BIG_ENDIAN
1341 R200_VC_32BIT_SWAP;
1342 #else
1343 R200_VC_NO_SWAP;
1344 #endif
1345
1346 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1347 /* Bypass TCL */
1348 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1349 }
1350
1351 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1352 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1353 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1354 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1355 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1356 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1357 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1358 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1359 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1360 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1361 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1362 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1363 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1364 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1365 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1366
1367
1368 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1369 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1370 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1371 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1372 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1373 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1374
1375 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1376 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1377 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1378 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1379 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1380 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1381 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1382 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1383 (/* R200_TEXCOORD_PROJ | */
1384 0x100000); /* Small default bias */
1385 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1386 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1387 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1388 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1389 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1390 }
1391 else {
1392 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1393 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1394 }
1395
1396 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1397 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1398 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1399 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1400 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1401 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1402 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1403 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1404 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1405 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1406 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1407
1408 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1409 (R200_TXC_ARG_A_ZERO |
1410 R200_TXC_ARG_B_ZERO |
1411 R200_TXC_ARG_C_DIFFUSE_COLOR |
1412 R200_TXC_OP_MADD);
1413
1414 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1415 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1416 R200_TXC_SCALE_1X |
1417 R200_TXC_CLAMP_0_1 |
1418 R200_TXC_OUTPUT_REG_R0);
1419
1420 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1421 (R200_TXA_ARG_A_ZERO |
1422 R200_TXA_ARG_B_ZERO |
1423 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1424 R200_TXA_OP_MADD);
1425
1426 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1427 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1428 R200_TXA_SCALE_1X |
1429 R200_TXA_CLAMP_0_1 |
1430 R200_TXA_OUTPUT_REG_R0);
1431 }
1432
1433 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1434 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1435 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1436 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1437 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1438 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1439
1440 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1441 (R200_VAP_TCL_ENABLE |
1442 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1443
1444 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1445 (R200_VPORT_X_SCALE_ENA |
1446 R200_VPORT_Y_SCALE_ENA |
1447 R200_VPORT_Z_SCALE_ENA |
1448 R200_VPORT_X_OFFSET_ENA |
1449 R200_VPORT_Y_OFFSET_ENA |
1450 R200_VPORT_Z_OFFSET_ENA |
1451 /* FIXME: Turn on for tex rect only */
1452 R200_VTX_ST_DENORMALIZED |
1453 R200_VTX_W0_FMT);
1454
1455
1456 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1457 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1458 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1459 ((R200_VTX_Z0 | R200_VTX_W0 |
1460 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1461 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1462 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1463 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1464
1465
1466 /* Matrix selection */
1467 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1468 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1469
1470 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1471 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1472
1473 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1474 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1475
1476 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1477 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1478 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1479 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1480 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1481
1482 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1483 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1484 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1485
1486
1487 /* General TCL state */
1488 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1489 (R200_SPECULAR_LIGHTS |
1490 R200_DIFFUSE_SPECULAR_COMBINE |
1491 R200_LOCAL_LIGHT_VEC_GL |
1492 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1493 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1494
1495 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1496 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1497 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1498 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1499 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1500 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1501 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1502 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1503 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1504
1505 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1506 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1507 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1508 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1509
1510 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1511 (R200_UCP_IN_CLIP_SPACE |
1512 R200_CULL_FRONT_IS_CCW);
1513
1514 /* Texgen/Texmat state */
1515 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1516 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1517 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1518 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1519 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1520 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1521 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1522 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1523 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1524 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1525 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1526 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1527 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1528 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1529 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1530 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1531 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1532
1533
1534 for (i = 0 ; i < 8; i++) {
1535 struct gl_light *l = &ctx->Light.Light[i];
1536 GLenum p = GL_LIGHT0 + i;
1537 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1538
1539 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1540 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1541 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1542 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1543 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1544 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1545 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1546 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1547 &l->ConstantAttenuation );
1548 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1549 &l->LinearAttenuation );
1550 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1551 &l->QuadraticAttenuation );
1552 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1553 }
1554
1555 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1556 ctx->Light.Model.Ambient );
1557
1558 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1559
1560 for (i = 0 ; i < 6; i++) {
1561 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1562 }
1563
1564 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1565 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1566 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1567 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1568 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1569 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1570
1571 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1572 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1573 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1574 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1575
1576 rmesa->hw.eye.cmd[EYE_X] = 0;
1577 rmesa->hw.eye.cmd[EYE_Y] = 0;
1578 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1579 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1580
1581 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1582 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1583
1584 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1585 location? In any case, since point attenuation triggers _needeyecoords,
1586 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1587 isn't set */
1588 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1589 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1590 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1591 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1592 /* no idea what the ptp_vport_scale values are good for, except the
1593 PTSIZE one - hopefully doesn't matter */
1594 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1595 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1596 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1597 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1598 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1599 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1600 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1601 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1602 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1603 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1604 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1605 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1606
1607 r200LightingSpaceChange( ctx );
1608
1609 if (rmesa->radeon.radeonScreen->kernel_mm) {
1610 radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE);
1611 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
1612 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0;
1613 }
1614
1615 rmesa->radeon.hw.all_dirty = GL_TRUE;
1616
1617 rcommonInitCmdBuf(&rmesa->radeon);
1618 }