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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169 static int cmdpkt( r200ContextPtr rmesa, int id )
170 {
171 drm_radeon_cmd_header_t h;
172
173 if (rmesa->radeon.radeonScreen->kernel_mm) {
174 return CP_PACKET0(packet[id].start, packet[id].len - 1);
175 } else {
176 h.i = 0;
177 h.packet.cmd_type = RADEON_CMD_PACKET;
178 h.packet.packet_id = id;
179 }
180 return h.i;
181 }
182
183 static int cmdvec( int offset, int stride, int count )
184 {
185 drm_radeon_cmd_header_t h;
186 h.i = 0;
187 h.vectors.cmd_type = RADEON_CMD_VECTORS;
188 h.vectors.offset = offset;
189 h.vectors.stride = stride;
190 h.vectors.count = count;
191 return h.i;
192 }
193
194 /* warning: the count here is divided by 4 compared to other cmds
195 (so it doesn't exceed the char size)! */
196 static int cmdveclinear( int offset, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
201 h.veclinear.addr_lo = offset & 0xff;
202 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
203 h.veclinear.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 static int cmdscl2( int offset, int stride, int count )
219 {
220 drm_radeon_cmd_header_t h;
221 h.i = 0;
222 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
223 h.scalars.offset = offset - 0x100;
224 h.scalars.stride = stride;
225 h.scalars.count = count;
226 return h.i;
227 }
228
229 #define CHECK( NM, FLAG ) \
230 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
231 { \
232 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
233 (void) rmesa; \
234 return (FLAG) ? atom->cmd_size : 0; \
235 }
236
237 #define TCL_CHECK( NM, FLAG ) \
238 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
239 { \
240 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
241 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
242 }
243
244 #define TCL_OR_VP_CHECK( NM, FLAG ) \
245 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
246 { \
247 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
248 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
249 }
250
251 #define VP_CHECK( NM, FLAG ) \
252 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
253 { \
254 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
255 (void) atom; \
256 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
257 }
258
259 CHECK( always, GL_TRUE )
260 CHECK( never, GL_FALSE )
261 CHECK( tex_any, ctx->Texture._EnabledUnits )
262 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
263 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
264 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
265 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
266 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
267 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
268 CHECK( afs, ctx->ATIFragmentShader._Enabled )
269 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
270 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
271 TCL_CHECK( tcl, GL_TRUE )
272 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
273 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
274 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
275 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
276 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
277 VP_CHECK( tcl_vp, GL_TRUE )
278 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
279 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
280
281 #define OUT_VEC(hdr, data) do { \
282 drm_radeon_cmd_header_t h; \
283 h.i = hdr; \
284 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
285 OUT_BATCH(0); \
286 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
287 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
288 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
289 OUT_BATCH_TABLE((data), h.vectors.count); \
290 } while(0)
291
292 #define OUT_VECLINEAR(hdr, data) do { \
293 drm_radeon_cmd_header_t h; \
294 uint32_t _start, _sz; \
295 h.i = hdr; \
296 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
297 _sz = h.veclinear.count * 4; \
298 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
299 BEGIN_BATCH_NO_AUTOSTATE(dwords); \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
305 OUT_BATCH_TABLE((data), _sz); \
306 END_BATCH(); \
307 } \
308 } while(0)
309
310 #define OUT_SCL(hdr, data) do { \
311 drm_radeon_cmd_header_t h; \
312 h.i = hdr; \
313 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
314 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
315 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
316 OUT_BATCH_TABLE((data), h.scalars.count); \
317 } while(0)
318
319 #define OUT_SCL2(hdr, data) do { \
320 drm_radeon_cmd_header_t h; \
321 h.i = hdr; \
322 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
323 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
324 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
325 OUT_BATCH_TABLE((data), h.scalars.count); \
326 } while(0)
327
328 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
329 {
330 r200ContextPtr r200 = R200_CONTEXT(ctx);
331 BATCH_LOCALS(&r200->radeon);
332 uint32_t dwords = atom->cmd_size;
333
334 dwords += 6;
335 BEGIN_BATCH_NO_AUTOSTATE(dwords);
336 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
337 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
338 END_BATCH();
339 }
340
341 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
342 {
343 r200ContextPtr r200 = R200_CONTEXT(ctx);
344 BATCH_LOCALS(&r200->radeon);
345 uint32_t dwords = atom->cmd_size;
346
347 dwords += 8;
348 BEGIN_BATCH_NO_AUTOSTATE(dwords);
349 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
350 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
351 END_BATCH();
352 }
353
354 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
355 {
356 r200ContextPtr r200 = R200_CONTEXT(ctx);
357 BATCH_LOCALS(&r200->radeon);
358 uint32_t dwords = atom->cmd_size;
359
360 dwords += 8;
361 BEGIN_BATCH_NO_AUTOSTATE(dwords);
362 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
363 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
364 END_BATCH();
365 }
366
367 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
368 {
369 r200ContextPtr r200 = R200_CONTEXT(ctx);
370 BATCH_LOCALS(&r200->radeon);
371 uint32_t dwords = atom->cmd_size;
372
373 dwords += 4;
374 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
375 }
376
377 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
378 {
379 r200ContextPtr r200 = R200_CONTEXT(ctx);
380 BATCH_LOCALS(&r200->radeon);
381 uint32_t dwords = atom->cmd_size;
382
383 dwords += 2;
384 BEGIN_BATCH_NO_AUTOSTATE(dwords);
385 OUT_SCL(atom->cmd[0], atom->cmd+1);
386 END_BATCH();
387 }
388
389
390 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r200ContextPtr r200 = R200_CONTEXT(ctx);
393 BATCH_LOCALS(&r200->radeon);
394 uint32_t dwords = atom->cmd_size;
395
396 dwords += 4;
397 BEGIN_BATCH_NO_AUTOSTATE(dwords);
398 OUT_VEC(atom->cmd[0], atom->cmd+1);
399 END_BATCH();
400 }
401
402 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
403 {
404 r200ContextPtr r200 = R200_CONTEXT(ctx);
405 BATCH_LOCALS(&r200->radeon);
406 struct radeon_renderbuffer *rrb;
407 uint32_t cbpitch;
408 uint32_t zbpitch, depth_fmt;
409 uint32_t dwords = atom->cmd_size;
410
411 /* output the first 7 bytes of context */
412 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
413 OUT_BATCH_TABLE(atom->cmd, 5);
414
415 rrb = radeon_get_depthbuffer(&r200->radeon);
416 if (!rrb) {
417 OUT_BATCH(0);
418 OUT_BATCH(0);
419 } else {
420 zbpitch = (rrb->pitch / rrb->cpp);
421 if (r200->using_hyperz)
422 zbpitch |= RADEON_DEPTH_HYPERZ;
423 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
424 OUT_BATCH(zbpitch);
425 if (rrb->cpp == 4)
426 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
427 else
428 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
429 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
430 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
431 }
432
433 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
434 OUT_BATCH(atom->cmd[CTX_CMD_1]);
435 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
436
437 rrb = radeon_get_colorbuffer(&r200->radeon);
438 if (!rrb || !rrb->bo) {
439 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
440 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
441 } else {
442 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
443 if (rrb->cpp == 4)
444 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
445 else
446 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
447
448 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
449 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
450 }
451
452 OUT_BATCH(atom->cmd[CTX_CMD_2]);
453
454 if (!rrb || !rrb->bo) {
455 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
456 } else {
457 cbpitch = (rrb->pitch / rrb->cpp);
458 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
459 cbpitch |= R200_COLOR_TILE_ENABLE;
460 OUT_BATCH(cbpitch);
461 }
462
463 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
464 OUT_BATCH_TABLE((atom->cmd + 14), 4);
465
466 END_BATCH();
467 }
468
469 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
470 {
471 r200ContextPtr r200 = R200_CONTEXT(ctx);
472 BATCH_LOCALS(&r200->radeon);
473 struct radeon_renderbuffer *rrb, *drb;
474 uint32_t cbpitch = 0;
475 uint32_t zbpitch = 0;
476 uint32_t dwords = atom->cmd_size;
477 uint32_t depth_fmt;
478
479 rrb = radeon_get_colorbuffer(&r200->radeon);
480 if (!rrb || !rrb->bo) {
481 return;
482 }
483
484 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
485 if (rrb->cpp == 4)
486 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
487 else
488 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
489
490 cbpitch = (rrb->pitch / rrb->cpp);
491 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
492 cbpitch |= R200_COLOR_TILE_ENABLE;
493
494 drb = radeon_get_depthbuffer(&r200->radeon);
495 if (drb) {
496 zbpitch = (drb->pitch / drb->cpp);
497 if (drb->cpp == 4)
498 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
499 else
500 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
501 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
502 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
503 }
504
505 dwords = 10;
506 if (drb)
507 dwords += 6;
508 if (rrb)
509 dwords += 6;
510 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
511 dwords += 4;
512
513 /* output the first 7 bytes of context */
514 BEGIN_BATCH_NO_AUTOSTATE(dwords);
515
516 /* In the CS case we need to split this up */
517 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
518 OUT_BATCH_TABLE((atom->cmd + 1), 4);
519
520 if (drb) {
521 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
522 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
523
524 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
525 OUT_BATCH(zbpitch);
526 }
527
528 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
529 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
530 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
531 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
532 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
533
534
535 if (rrb) {
536 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
537 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
538
539 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
540 OUT_BATCH(cbpitch);
541 }
542
543 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
544 OUT_BATCH_TABLE((atom->cmd + 14), 4);
545 }
546
547 END_BATCH();
548 }
549
550 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
551 {
552 r200ContextPtr r200 = R200_CONTEXT(ctx);
553 BATCH_LOCALS(&r200->radeon);
554 uint32_t dwords = atom->cmd_size;
555 int i = atom->idx;
556 radeonTexObj *t = r200->state.texture.unit[i].texobj;
557 radeon_mipmap_level *lvl;
558
559 if (t && t->mt && !t->image_override)
560 dwords += 2;
561 BEGIN_BATCH_NO_AUTOSTATE(dwords);
562 /* is this ok even with drm older than 1.18? */
563 OUT_BATCH_TABLE(atom->cmd, 10);
564
565 if (t && t->mt && !t->image_override) {
566 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
567 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
568 } else if (!t) {
569 /* workaround for old CS mechanism */
570 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
571 } else {
572 OUT_BATCH(t->override_offset);
573 }
574
575 END_BATCH();
576 }
577
578 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
579 {
580 r200ContextPtr r200 = R200_CONTEXT(ctx);
581 BATCH_LOCALS(&r200->radeon);
582 uint32_t dwords = atom->cmd_size;
583 int i = atom->idx;
584 radeonTexObj *t = r200->state.texture.unit[i].texobj;
585 radeon_mipmap_level *lvl;
586 int hastexture = 1;
587
588 if (!r200->state.texture.unit[i].unitneeded)
589 hastexture = 0;
590 if (!t)
591 hastexture = 0;
592 else {
593 if (!t->mt && !t->bo)
594 hastexture = 0;
595 }
596
597 if (hastexture)
598 dwords += 2;
599 else
600 dwords -= 2;
601 BEGIN_BATCH_NO_AUTOSTATE(dwords);
602
603 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
604 OUT_BATCH_TABLE((atom->cmd + 1), 8);
605
606 if (hastexture) {
607 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
608 if (t->mt && !t->image_override) {
609 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
610 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
611 } else {
612 if (t->bo)
613 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
614 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
615 }
616 }
617 END_BATCH();
618 }
619
620
621 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
622 {
623 r200ContextPtr r200 = R200_CONTEXT(ctx);
624 BATCH_LOCALS(&r200->radeon);
625 uint32_t dwords = 3;
626 int i = atom->idx, j;
627 radeonTexObj *t = r200->state.texture.unit[i].texobj;
628 radeon_mipmap_level *lvl;
629
630 BEGIN_BATCH_NO_AUTOSTATE(dwords + (3 * 5));
631 /* XXX that size won't really match with image_override... */
632 OUT_BATCH_TABLE(atom->cmd, 2);
633
634 if (t && !t->image_override) {
635 lvl = &t->mt->levels[0];
636 OUT_BATCH_TABLE((atom->cmd + 2), 1);
637 for (j = 1; j <= 5; j++) {
638 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
639 RADEON_GEM_DOMAIN_VRAM, 0, 0);
640 }
641 }
642 END_BATCH();
643 }
644
645 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
646 {
647 r200ContextPtr r200 = R200_CONTEXT(ctx);
648 BATCH_LOCALS(&r200->radeon);
649 uint32_t dwords = 2;
650 int i = atom->idx, j;
651 radeonTexObj *t = r200->state.texture.unit[i].texobj;
652 radeon_mipmap_level *lvl;
653
654 BEGIN_BATCH_NO_AUTOSTATE(dwords + (4 * 5));
655 OUT_BATCH_TABLE(atom->cmd, 2);
656
657 if (t && !t->image_override) {
658 lvl = &t->mt->levels[0];
659 for (j = 1; j <= 5; j++) {
660 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
661 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
662 RADEON_GEM_DOMAIN_VRAM, 0, 0);
663 }
664 }
665 END_BATCH();
666 }
667
668 /* Initialize the context's hardware state.
669 */
670 void r200InitState( r200ContextPtr rmesa )
671 {
672 GLcontext *ctx = rmesa->radeon.glCtx;
673 GLuint i;
674
675 rmesa->radeon.state.color.clear = 0x00000000;
676
677 switch ( ctx->Visual.depthBits ) {
678 case 16:
679 rmesa->radeon.state.depth.clear = 0x0000ffff;
680 rmesa->radeon.state.stencil.clear = 0x00000000;
681 break;
682 case 24:
683 default:
684 rmesa->radeon.state.depth.clear = 0x00ffffff;
685 rmesa->radeon.state.stencil.clear = 0xffff0000;
686 break;
687 }
688
689 rmesa->radeon.Fallback = 0;
690
691 rmesa->radeon.hw.max_state_size = 0;
692
693 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
694 do { \
695 rmesa->hw.ATOM.cmd_size = SZ; \
696 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
697 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
698 rmesa->hw.ATOM.name = NM; \
699 rmesa->hw.ATOM.idx = IDX; \
700 rmesa->hw.ATOM.check = check_##CHK; \
701 rmesa->hw.ATOM.dirty = GL_FALSE; \
702 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
703 } while (0)
704
705
706 /* Allocate state buffers:
707 */
708 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
709 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
710 else
711 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
712
713 if (rmesa->radeon.radeonScreen->kernel_mm)
714 rmesa->hw.ctx.emit = ctx_emit_cs;
715 else
716 rmesa->hw.ctx.emit = ctx_emit;
717 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
718 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
719 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
720 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
721 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
722 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
723 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
724 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
725 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
726 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
727 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
728 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
729 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
730 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
731 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
732 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
733 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
734 }
735 else {
736 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
737 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
738 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
739 }
740 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
741 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
742 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
743 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
744 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
745 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
746 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
747 }
748 else {
749 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
750 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
751 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
752 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
753 }
754 else {
755 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
756 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
757 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
758 }
759 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
760 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
761 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
762 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
763 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
764 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
765 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
766 }
767
768 for (i = 0; i < 5; i++)
769 if (rmesa->radeon.radeonScreen->kernel_mm)
770 rmesa->hw.tex[i].emit = tex_emit_cs;
771 else
772 rmesa->hw.tex[i].emit = tex_emit;
773 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
774 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
775 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
776 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
777 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
778 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
779 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
780 for (i = 0; i < 5; i++)
781 if (rmesa->radeon.radeonScreen->kernel_mm)
782 rmesa->hw.cube[i].emit = cube_emit_cs;
783 else
784 rmesa->hw.cube[i].emit = cube_emit;
785 }
786 else {
787 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
788 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
789 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
790 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
791 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
792 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
793 }
794
795 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
796 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
797 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
798 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
799 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
800 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
801 }
802 else {
803 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
804 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
805 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
806 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
807 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
808 }
809 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
810 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
811 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
812 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
813 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
814 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
815 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
816 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
817 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
818 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
819 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
820 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
821 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
822 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
823 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
824 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
825 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
826 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
827 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
828 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
829 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
830 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
831 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
832 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
833 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
834 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
835 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
836 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
837 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
838 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
839 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
840 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
841 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
842 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
843 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
844 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
845 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
846 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
847 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
848 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
849 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
850 }
851 else {
852 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
853 }
854 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
855 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
856 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
857 }
858 else {
859 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
860 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
861 }
862
863 r200SetUpAtomList( rmesa );
864
865 /* Fill in the packet headers:
866 */
867 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
868 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
869 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
870 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
871 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
872 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
873 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
874 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
875 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
876 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
877 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
878 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
879 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
880 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
881 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
882 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
883 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
884 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
885 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
886 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
887 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
888 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
889 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
890 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
891 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
892 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
893 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
894 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
895 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
896 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
897 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
898 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
899 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
900 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
901 } else {
902 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
903 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
904 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
905 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
906 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
907 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
908 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
909 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
910 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
911 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
912 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
913 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
914 }
915 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
916 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
917 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
918 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
919 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
920 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
921 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
922 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
923 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
924 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
925 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
926 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
927 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
928 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
929 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
930 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
931 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
932 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
933 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
934 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
935 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
936 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
937 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
938 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
939 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
940 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
941 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
942 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
943 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
944 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
945 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
946 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
947 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
948 if (rmesa->radeon.radeonScreen->kernel_mm) {
949 rmesa->hw.mtl[0].emit = mtl_emit;
950 rmesa->hw.mtl[1].emit = mtl_emit;
951
952 rmesa->hw.vpi[0].emit = veclinear_emit;
953 rmesa->hw.vpi[1].emit = veclinear_emit;
954 rmesa->hw.vpp[0].emit = veclinear_emit;
955 rmesa->hw.vpp[1].emit = veclinear_emit;
956
957 rmesa->hw.grd.emit = scl_emit;
958 rmesa->hw.fog.emit = vec_emit;
959 rmesa->hw.glt.emit = vec_emit;
960 rmesa->hw.eye.emit = vec_emit;
961
962 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
963 rmesa->hw.mat[i].emit = vec_emit;
964
965 for (i = 0; i < 8; i++)
966 rmesa->hw.lit[i].emit = lit_emit;
967
968 for (i = 0; i < 6; i++)
969 rmesa->hw.ucp[i].emit = vec_emit;
970
971 rmesa->hw.ptp.emit = ptp_emit;
972 }
973
974
975
976 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
977 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
978 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
979 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
980 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
981 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
982 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
983 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
984
985 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
986 cmdveclinear( R200_PVS_PROG0, 64 );
987 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
988 cmdveclinear( R200_PVS_PROG1, 64 );
989 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
990 cmdveclinear( R200_PVS_PARAM0, 96 );
991 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
992 cmdveclinear( R200_PVS_PARAM1, 96 );
993
994 rmesa->hw.grd.cmd[GRD_CMD_0] =
995 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
996 rmesa->hw.fog.cmd[FOG_CMD_0] =
997 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
998 rmesa->hw.glt.cmd[GLT_CMD_0] =
999 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
1000 rmesa->hw.eye.cmd[EYE_CMD_0] =
1001 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
1002
1003 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
1004 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
1005 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1006 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1007 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1008 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1009 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1010 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1011 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1012 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1013 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1014 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1015 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1016 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1017 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1018 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1019 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1020 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1021
1022 for (i = 0 ; i < 8; i++) {
1023 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1024 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1025 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1026 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1027 }
1028
1029 for (i = 0 ; i < 6; i++) {
1030 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1031 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1032 }
1033
1034 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1035 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1036 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1037 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1038
1039 /* Initial Harware state:
1040 */
1041 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1042 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1043
1044 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1045 R200_FOG_USE_SPEC_ALPHA);
1046
1047 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1048
1049 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1050 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1051 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1052
1053 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1054 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1055 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1056 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1057 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1058 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1059 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1060 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1061 }
1062
1063 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1064 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1065
1066 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1067 ((rmesa->radeon.radeonScreen->depthPitch &
1068 R200_DEPTHPITCH_MASK) |
1069 R200_DEPTH_ENDIAN_NO_SWAP);
1070
1071 if (rmesa->using_hyperz)
1072 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1073
1074 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1075 R200_STENCIL_TEST_ALWAYS |
1076 R200_STENCIL_FAIL_KEEP |
1077 R200_STENCIL_ZPASS_KEEP |
1078 R200_STENCIL_ZFAIL_KEEP |
1079 R200_Z_WRITE_ENABLE);
1080
1081 if (rmesa->using_hyperz) {
1082 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1083 R200_Z_DECOMPRESSION_ENABLE;
1084 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1085 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1086 }
1087
1088 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1089 | R200_TEX_BLEND_0_ENABLE);
1090
1091 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1092 case DRI_CONF_DITHER_XERRORDIFFRESET:
1093 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1094 break;
1095 case DRI_CONF_DITHER_ORDERED:
1096 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1097 break;
1098 }
1099 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1100 DRI_CONF_ROUND_ROUND )
1101 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1102 else
1103 rmesa->radeon.state.color.roundEnable = 0;
1104 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1105 DRI_CONF_COLOR_REDUCTION_DITHER )
1106 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1107 else
1108 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1109
1110 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1111 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1112 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1113
1114 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1115 R200_BFACE_SOLID |
1116 R200_FFACE_SOLID |
1117 R200_FLAT_SHADE_VTX_LAST |
1118 R200_DIFFUSE_SHADE_GOURAUD |
1119 R200_ALPHA_SHADE_GOURAUD |
1120 R200_SPECULAR_SHADE_GOURAUD |
1121 R200_FOG_SHADE_GOURAUD |
1122 R200_DISC_FOG_SHADE_GOURAUD |
1123 R200_VTX_PIX_CENTER_OGL |
1124 R200_ROUND_MODE_TRUNC |
1125 R200_ROUND_PREC_8TH_PIX);
1126
1127 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1128 R200_SCISSOR_ENABLE);
1129
1130 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1131
1132 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1133 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1134 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1135
1136 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1137
1138 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1139 ((0x00 << R200_STENCIL_REF_SHIFT) |
1140 (0xff << R200_STENCIL_MASK_SHIFT) |
1141 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1142
1143 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1144 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1145
1146 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1147
1148 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1149 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1150 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1151 R200_STIPPLE_BIG_BIT_ORDER);
1152
1153
1154 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1155 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1156 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1157 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1158 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1159 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1160 #ifdef MESA_BIG_ENDIAN
1161 R200_VC_32BIT_SWAP;
1162 #else
1163 R200_VC_NO_SWAP;
1164 #endif
1165
1166 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1167 /* Bypass TCL */
1168 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1169 }
1170
1171 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1172 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1173 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1174 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1175 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1176 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1177 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1178 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1179 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1180 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1181 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1182 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1183 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1184 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1185 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1186
1187
1188 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1189 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1190 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1191 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1192 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1193 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1194
1195 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1196 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1197 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1198 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1199 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1200 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1201 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1202 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1203 (/* R200_TEXCOORD_PROJ | */
1204 0x100000); /* Small default bias */
1205 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1206 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1207 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1208 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1209 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1210 }
1211 else {
1212 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1213 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1214 }
1215
1216 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1217 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1218 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1219 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1220 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1221 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1222 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1223 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1224 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1225 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1226 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1227
1228 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1229 (R200_TXC_ARG_A_ZERO |
1230 R200_TXC_ARG_B_ZERO |
1231 R200_TXC_ARG_C_DIFFUSE_COLOR |
1232 R200_TXC_OP_MADD);
1233
1234 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1235 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1236 R200_TXC_SCALE_1X |
1237 R200_TXC_CLAMP_0_1 |
1238 R200_TXC_OUTPUT_REG_R0);
1239
1240 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1241 (R200_TXA_ARG_A_ZERO |
1242 R200_TXA_ARG_B_ZERO |
1243 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1244 R200_TXA_OP_MADD);
1245
1246 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1247 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1248 R200_TXA_SCALE_1X |
1249 R200_TXA_CLAMP_0_1 |
1250 R200_TXA_OUTPUT_REG_R0);
1251 }
1252
1253 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1254 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1255 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1256 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1257 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1258 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1259
1260 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1261 (R200_VAP_TCL_ENABLE |
1262 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1263
1264 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1265 (R200_VPORT_X_SCALE_ENA |
1266 R200_VPORT_Y_SCALE_ENA |
1267 R200_VPORT_Z_SCALE_ENA |
1268 R200_VPORT_X_OFFSET_ENA |
1269 R200_VPORT_Y_OFFSET_ENA |
1270 R200_VPORT_Z_OFFSET_ENA |
1271 /* FIXME: Turn on for tex rect only */
1272 R200_VTX_ST_DENORMALIZED |
1273 R200_VTX_W0_FMT);
1274
1275
1276 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1277 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1278 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1279 ((R200_VTX_Z0 | R200_VTX_W0 |
1280 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1281 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1282 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1283 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1284
1285
1286 /* Matrix selection */
1287 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1288 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1289
1290 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1291 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1292
1293 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1294 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1295
1296 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1297 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1298 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1299 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1300 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1301
1302 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1303 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1304 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1305
1306
1307 /* General TCL state */
1308 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1309 (R200_SPECULAR_LIGHTS |
1310 R200_DIFFUSE_SPECULAR_COMBINE |
1311 R200_LOCAL_LIGHT_VEC_GL |
1312 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1313 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1314
1315 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1316 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1317 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1318 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1319 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1320 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1321 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1322 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1323 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1324
1325 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1326 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1327 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1328 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1329
1330 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1331 (R200_UCP_IN_CLIP_SPACE |
1332 R200_CULL_FRONT_IS_CCW);
1333
1334 /* Texgen/Texmat state */
1335 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1336 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1337 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1338 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1339 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1340 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1341 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1342 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1343 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1344 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1345 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1346 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1347 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1348 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1349 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1350 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1351 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1352
1353
1354 for (i = 0 ; i < 8; i++) {
1355 struct gl_light *l = &ctx->Light.Light[i];
1356 GLenum p = GL_LIGHT0 + i;
1357 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1358
1359 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1360 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1361 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1362 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1363 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1364 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1365 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1366 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1367 &l->ConstantAttenuation );
1368 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1369 &l->LinearAttenuation );
1370 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1371 &l->QuadraticAttenuation );
1372 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1373 }
1374
1375 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1376 ctx->Light.Model.Ambient );
1377
1378 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1379
1380 for (i = 0 ; i < 6; i++) {
1381 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1382 }
1383
1384 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1385 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1386 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1387 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1388 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1389 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1390
1391 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1392 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1393 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1394 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1395
1396 rmesa->hw.eye.cmd[EYE_X] = 0;
1397 rmesa->hw.eye.cmd[EYE_Y] = 0;
1398 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1399 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1400
1401 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1402 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1403
1404 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1405 location? In any case, since point attenuation triggers _needeyecoords,
1406 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1407 isn't set */
1408 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1409 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1410 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1411 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1412 /* no idea what the ptp_vport_scale values are good for, except the
1413 PTSIZE one - hopefully doesn't matter */
1414 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1415 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1416 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1417 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1418 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1419 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1420 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1421 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1422 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1423 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1424 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1425 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1426
1427 r200LightingSpaceChange( ctx );
1428
1429 rmesa->radeon.hw.all_dirty = GL_TRUE;
1430
1431 rcommonInitCmdBuf(&rmesa->radeon);
1432 }