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r200: Add scissor to state atom list.
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169 static int cmdpkt( r200ContextPtr rmesa, int id )
170 {
171 drm_radeon_cmd_header_t h;
172
173 if (rmesa->radeon.radeonScreen->kernel_mm) {
174 return CP_PACKET0(packet[id].start, packet[id].len - 1);
175 } else {
176 h.i = 0;
177 h.packet.cmd_type = RADEON_CMD_PACKET;
178 h.packet.packet_id = id;
179 }
180 return h.i;
181 }
182
183 static int cmdvec( int offset, int stride, int count )
184 {
185 drm_radeon_cmd_header_t h;
186 h.i = 0;
187 h.vectors.cmd_type = RADEON_CMD_VECTORS;
188 h.vectors.offset = offset;
189 h.vectors.stride = stride;
190 h.vectors.count = count;
191 return h.i;
192 }
193
194 /* warning: the count here is divided by 4 compared to other cmds
195 (so it doesn't exceed the char size)! */
196 static int cmdveclinear( int offset, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
201 h.veclinear.addr_lo = offset & 0xff;
202 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
203 h.veclinear.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 static int cmdscl2( int offset, int stride, int count )
219 {
220 drm_radeon_cmd_header_t h;
221 h.i = 0;
222 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
223 h.scalars.offset = offset - 0x100;
224 h.scalars.stride = stride;
225 h.scalars.count = count;
226 return h.i;
227 }
228
229 /**
230 * Check functions are used to check if state is active.
231 * If it is active check function returns maximum emit size.
232 */
233 #define CHECK( NM, FLAG, ADD ) \
234 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
235 { \
236 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
237 (void) rmesa; \
238 return (FLAG) ? atom->cmd_size + (ADD) : 0; \
239 }
240
241 #define TCL_CHECK( NM, FLAG, ADD ) \
242 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
243 { \
244 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
245 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
246 }
247
248 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
249 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
250 { \
251 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
252 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
253 }
254
255 #define VP_CHECK( NM, FLAG, ADD ) \
256 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
257 { \
258 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
259 (void) atom; \
260 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
261 }
262
263 CHECK( always, GL_TRUE, 0 )
264 CHECK( always_add4, GL_TRUE, 4 )
265 CHECK( never, GL_FALSE, 0 )
266 CHECK( tex_any, ctx->Texture._EnabledUnits, 0 )
267 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled), 0 );
268 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
269 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
270 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
271 CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
272 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
273 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 2*5 - CUBE_STATE_SIZE )
274 TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 )
275 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
276 TCL_CHECK( tcl, GL_TRUE, 0 )
277 TCL_CHECK( tcl_add8, GL_TRUE, 8 )
278 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
279 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded, 0 )
280 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
281 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 0 )
282 TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 )
283 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
284 TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 )
285 TCL_CHECK( tcl_light_add8, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 8 )
286 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 0 )
287 TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 )
288 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 )
289 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 )
290 VP_CHECK( tcl_vp, GL_TRUE, 0 )
291 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 )
292 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 0 )
293 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 0 )
294 VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 )
295 VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start, _sz; \
311 h.i = hdr; \
312 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
313 _sz = h.veclinear.count * 4; \
314 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
315 BEGIN_BATCH_NO_AUTOSTATE(dwords); \
316 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
317 OUT_BATCH(0); \
318 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
319 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
320 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
321 OUT_BATCH_TABLE((data), _sz); \
322 END_BATCH(); \
323 } \
324 } while(0)
325
326 #define OUT_SCL(hdr, data) do { \
327 drm_radeon_cmd_header_t h; \
328 h.i = hdr; \
329 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
330 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
331 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
332 OUT_BATCH_TABLE((data), h.scalars.count); \
333 } while(0)
334
335 #define OUT_SCL2(hdr, data) do { \
336 drm_radeon_cmd_header_t h; \
337 h.i = hdr; \
338 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
339 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
340 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
341 OUT_BATCH_TABLE((data), h.scalars.count); \
342 } while(0)
343 static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom)
344 {
345 r200ContextPtr r200 = R200_CONTEXT(ctx);
346 struct radeon_renderbuffer *rrb;
347 rrb = radeon_get_colorbuffer(&r200->radeon);
348 if (!rrb || !rrb->bo)
349 return 0;
350 return atom->cmd_size;
351 }
352
353 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
354 {
355 r200ContextPtr r200 = R200_CONTEXT(ctx);
356 BATCH_LOCALS(&r200->radeon);
357 uint32_t dwords = atom->check(ctx, atom);
358
359 BEGIN_BATCH_NO_AUTOSTATE(dwords);
360 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
361 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
362 END_BATCH();
363 }
364
365 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
366 {
367 r200ContextPtr r200 = R200_CONTEXT(ctx);
368 BATCH_LOCALS(&r200->radeon);
369 uint32_t dwords = atom->check(ctx, atom);
370
371 BEGIN_BATCH_NO_AUTOSTATE(dwords);
372 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
373 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
374 END_BATCH();
375 }
376
377 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
378 {
379 r200ContextPtr r200 = R200_CONTEXT(ctx);
380 BATCH_LOCALS(&r200->radeon);
381 uint32_t dwords = atom->check(ctx, atom);
382
383 BEGIN_BATCH_NO_AUTOSTATE(dwords);
384 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
385 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
386 END_BATCH();
387 }
388
389 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
390 {
391 r200ContextPtr r200 = R200_CONTEXT(ctx);
392 BATCH_LOCALS(&r200->radeon);
393 uint32_t dwords = atom->check(ctx, atom);
394
395 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
396 }
397
398 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
399 {
400 r200ContextPtr r200 = R200_CONTEXT(ctx);
401 BATCH_LOCALS(&r200->radeon);
402 uint32_t dwords = atom->check(ctx, atom);
403
404 BEGIN_BATCH_NO_AUTOSTATE(dwords);
405 OUT_SCL(atom->cmd[0], atom->cmd+1);
406 END_BATCH();
407 }
408
409
410 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
411 {
412 r200ContextPtr r200 = R200_CONTEXT(ctx);
413 BATCH_LOCALS(&r200->radeon);
414 uint32_t dwords = atom->check(ctx, atom);
415
416 BEGIN_BATCH_NO_AUTOSTATE(dwords);
417 OUT_VEC(atom->cmd[0], atom->cmd+1);
418 END_BATCH();
419 }
420
421 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
422 {
423 r200ContextPtr r200 = R200_CONTEXT(ctx);
424 BATCH_LOCALS(&r200->radeon);
425 struct radeon_renderbuffer *rrb;
426 uint32_t cbpitch;
427 uint32_t zbpitch, depth_fmt;
428 uint32_t dwords = atom->check(ctx, atom);
429
430 /* output the first 7 bytes of context */
431 BEGIN_BATCH_NO_AUTOSTATE(dwords);
432 OUT_BATCH_TABLE(atom->cmd, 5);
433
434 rrb = radeon_get_depthbuffer(&r200->radeon);
435 if (!rrb) {
436 OUT_BATCH(0);
437 OUT_BATCH(0);
438 } else {
439 zbpitch = (rrb->pitch / rrb->cpp);
440 if (r200->using_hyperz)
441 zbpitch |= RADEON_DEPTH_HYPERZ;
442 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
443 OUT_BATCH(zbpitch);
444 if (rrb->cpp == 4)
445 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
446 else
447 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
448 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
449 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
450 }
451
452 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
453 OUT_BATCH(atom->cmd[CTX_CMD_1]);
454 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
455
456 rrb = radeon_get_colorbuffer(&r200->radeon);
457 if (!rrb || !rrb->bo) {
458 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
459 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
460 } else {
461 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
462 if (rrb->cpp == 4)
463 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
464 else
465 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
466
467 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
468 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
469 }
470
471 OUT_BATCH(atom->cmd[CTX_CMD_2]);
472
473 if (!rrb || !rrb->bo) {
474 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
475 } else {
476 cbpitch = (rrb->pitch / rrb->cpp);
477 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
478 cbpitch |= R200_COLOR_TILE_ENABLE;
479 OUT_BATCH(cbpitch);
480 }
481
482 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
483 OUT_BATCH_TABLE((atom->cmd + 14), 4);
484
485 END_BATCH();
486 }
487
488 static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
489 {
490 r200ContextPtr r200 = R200_CONTEXT(ctx);
491 struct radeon_renderbuffer *rrb, *drb;
492 uint32_t dwords;
493
494 rrb = radeon_get_colorbuffer(&r200->radeon);
495 if (!rrb || !rrb->bo) {
496 return 0;
497 }
498
499 drb = radeon_get_depthbuffer(&r200->radeon);
500
501 dwords = 10;
502 if (drb)
503 dwords += 6;
504 if (rrb)
505 dwords += 8;
506 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
507 dwords += 4;
508
509
510 return dwords;
511 }
512
513 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
514 {
515 r200ContextPtr r200 = R200_CONTEXT(ctx);
516 BATCH_LOCALS(&r200->radeon);
517 struct radeon_renderbuffer *rrb, *drb;
518 uint32_t cbpitch = 0;
519 uint32_t zbpitch = 0;
520 uint32_t dwords = atom->check(ctx, atom);
521 uint32_t depth_fmt;
522
523 rrb = radeon_get_colorbuffer(&r200->radeon);
524 if (!rrb || !rrb->bo) {
525 return;
526 }
527
528 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
529 if (rrb->cpp == 4)
530 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
531 else switch (rrb->base._ActualFormat) {
532 case GL_RGB5:
533 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
534 break;
535 case GL_RGBA4:
536 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
537 break;
538 case GL_RGB5_A1:
539 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
540 break;
541 }
542
543 cbpitch = (rrb->pitch / rrb->cpp);
544 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
545 cbpitch |= R200_COLOR_TILE_ENABLE;
546
547 drb = radeon_get_depthbuffer(&r200->radeon);
548 if (drb) {
549 zbpitch = (drb->pitch / drb->cpp);
550 if (drb->cpp == 4)
551 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
552 else
553 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
554 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
555 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
556 }
557
558 /* output the first 7 bytes of context */
559 BEGIN_BATCH_NO_AUTOSTATE(dwords);
560
561 /* In the CS case we need to split this up */
562 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
563 OUT_BATCH_TABLE((atom->cmd + 1), 4);
564
565 if (drb) {
566 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
567 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
568
569 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
570 OUT_BATCH(zbpitch);
571 }
572
573 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
574 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
575 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
576 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
577 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
578
579
580 if (rrb) {
581 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
582 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
583
584 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
585 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
586 }
587
588 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
589 OUT_BATCH_TABLE((atom->cmd + 14), 4);
590 }
591
592 END_BATCH();
593 }
594
595 static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
596 {
597 r200ContextPtr r200 = R200_CONTEXT(ctx);
598 uint32_t dwords = atom->cmd_size + 2;
599 int i = atom->idx;
600 radeonTexObj *t = r200->state.texture.unit[i].texobj;
601 if (!(t && t->mt && !t->image_override))
602 dwords -= 2;
603
604 return dwords;
605 }
606
607 static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
608 {
609 r200ContextPtr r200 = R200_CONTEXT(ctx);
610 /** XOR is bit flip operation so use it for finding pair */
611 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
612 return 0;
613
614 return get_tex_size(ctx, atom);
615 }
616
617 static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
618 {
619 r200ContextPtr r200 = R200_CONTEXT(ctx);
620 if (!(r200->state.texture.unit[atom->idx].unitneeded))
621 return 0;
622
623 return get_tex_size(ctx, atom);
624 }
625
626
627 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
628 {
629 r200ContextPtr r200 = R200_CONTEXT(ctx);
630 BATCH_LOCALS(&r200->radeon);
631 uint32_t dwords = atom->check(ctx, atom);
632 int i = atom->idx;
633 radeonTexObj *t = r200->state.texture.unit[i].texobj;
634
635 BEGIN_BATCH_NO_AUTOSTATE(dwords);
636 /* is this ok even with drm older than 1.18? */
637 OUT_BATCH_TABLE(atom->cmd, 10);
638
639 if (t && t->mt && !t->image_override) {
640 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
641 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
642 } else if (!t) {
643 /* workaround for old CS mechanism */
644 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
645 } else {
646 OUT_BATCH(t->override_offset);
647 }
648
649 END_BATCH();
650 }
651
652 static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
653 {
654 r200ContextPtr r200 = R200_CONTEXT(ctx);
655 uint32_t dwords = atom->cmd_size + 2;
656 int hastexture = 1;
657 int i = atom->idx;
658 radeonTexObj *t = r200->state.texture.unit[i].texobj;
659 if (!t)
660 hastexture = 0;
661 else {
662 if (!t->mt && !t->bo)
663 hastexture = 0;
664 }
665
666 if (!hastexture)
667 dwords -= 4;
668 return dwords;
669 }
670
671 static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
672 {
673 r200ContextPtr r200 = R200_CONTEXT(ctx);
674 /** XOR is bit flip operation so use it for finding pair */
675 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
676 return 0;
677
678 return get_tex_mm_size(ctx, atom);
679 }
680
681 static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
682 {
683 r200ContextPtr r200 = R200_CONTEXT(ctx);
684 if (!(r200->state.texture.unit[atom->idx].unitneeded))
685 return 0;
686
687 return get_tex_mm_size(ctx, atom);
688 }
689
690
691 static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
692 {
693 r200ContextPtr r200 = R200_CONTEXT(ctx);
694 BATCH_LOCALS(&r200->radeon);
695 uint32_t dwords = atom->check(ctx, atom);
696 int i = atom->idx;
697 radeonTexObj *t = r200->state.texture.unit[i].texobj;
698 if (!r200->state.texture.unit[i].unitneeded)
699 dwords -= 4;
700 BEGIN_BATCH_NO_AUTOSTATE(dwords);
701
702 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
703 OUT_BATCH_TABLE((atom->cmd + 1), 8);
704
705 if (dwords > atom->cmd_size) {
706 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
707 if (t->mt && !t->image_override) {
708 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
709 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
710 } else {
711 if (t->bo)
712 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
713 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
714 }
715 }
716 END_BATCH();
717 }
718
719
720 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
721 {
722 r200ContextPtr r200 = R200_CONTEXT(ctx);
723 BATCH_LOCALS(&r200->radeon);
724 uint32_t dwords = atom->check(ctx, atom);
725 int i = atom->idx, j;
726 radeonTexObj *t = r200->state.texture.unit[i].texobj;
727 radeon_mipmap_level *lvl;
728
729 if (!(t && !t->image_override))
730 dwords = 2;
731
732 BEGIN_BATCH_NO_AUTOSTATE(dwords);
733 /* XXX that size won't really match with image_override... */
734 OUT_BATCH_TABLE(atom->cmd, 2);
735
736 if (t && !t->image_override) {
737 lvl = &t->mt->levels[0];
738 OUT_BATCH_TABLE((atom->cmd + 2), 1);
739 for (j = 1; j <= 5; j++) {
740 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
741 RADEON_GEM_DOMAIN_VRAM, 0, 0);
742 }
743 }
744 END_BATCH();
745 }
746
747 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
748 {
749 r200ContextPtr r200 = R200_CONTEXT(ctx);
750 BATCH_LOCALS(&r200->radeon);
751 uint32_t dwords = atom->check(ctx, atom);
752 int i = atom->idx, j;
753 radeonTexObj *t = r200->state.texture.unit[i].texobj;
754 radeon_mipmap_level *lvl;
755 if (!(t && !t->image_override))
756 dwords = 2;
757
758 BEGIN_BATCH_NO_AUTOSTATE(dwords);
759 OUT_BATCH_TABLE(atom->cmd, 2);
760
761 if (t && !t->image_override) {
762 lvl = &t->mt->levels[0];
763 for (j = 1; j <= 5; j++) {
764 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
765 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
766 RADEON_GEM_DOMAIN_VRAM, 0, 0);
767 }
768 }
769 END_BATCH();
770 }
771
772 /* Initialize the context's hardware state.
773 */
774 void r200InitState( r200ContextPtr rmesa )
775 {
776 GLcontext *ctx = rmesa->radeon.glCtx;
777 GLuint i;
778
779 rmesa->radeon.state.color.clear = 0x00000000;
780
781 switch ( ctx->Visual.depthBits ) {
782 case 16:
783 rmesa->radeon.state.depth.clear = 0x0000ffff;
784 rmesa->radeon.state.stencil.clear = 0x00000000;
785 break;
786 case 24:
787 default:
788 rmesa->radeon.state.depth.clear = 0x00ffffff;
789 rmesa->radeon.state.stencil.clear = 0xffff0000;
790 break;
791 }
792
793 rmesa->radeon.Fallback = 0;
794
795 rmesa->radeon.hw.max_state_size = 0;
796
797 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
798 do { \
799 rmesa->hw.ATOM.cmd_size = SZ; \
800 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
801 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
802 rmesa->hw.ATOM.name = NM; \
803 rmesa->hw.ATOM.idx = IDX; \
804 if (check_##CHK != check_never) { \
805 rmesa->hw.ATOM.check = check_##CHK; \
806 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
807 } else { \
808 rmesa->hw.ATOM.check = NULL; \
809 } \
810 rmesa->hw.ATOM.dirty = GL_FALSE; \
811 } while (0)
812
813
814 /* Allocate state buffers:
815 */
816 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
817 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
818 else
819 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
820
821 if (rmesa->radeon.radeonScreen->kernel_mm)
822 {
823 rmesa->hw.ctx.emit = ctx_emit_cs;
824 rmesa->hw.ctx.check = check_always_ctx;
825 }
826 else
827 {
828 rmesa->hw.ctx.emit = ctx_emit;
829 }
830 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
831 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
832 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
833 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
834 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
835 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
836 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
837 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
838 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
839 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
840 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
841 {
842 int state_size = TEX_STATE_SIZE_NEWDRM;
843 if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) {
844 state_size = TEX_STATE_SIZE_OLDDRM;
845 }
846 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
847 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
848 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
849 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
850 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
851 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
852 }
853 else {
854 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
855 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
856 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
857 }
858 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
859 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
860 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
861 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
862 if (!rmesa->radeon.radeonScreen->kernel_mm)
863 {
864 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
865 rmesa->hw.tex[0].check = check_tex_pair;
866 rmesa->hw.tex[1].check = check_tex_pair;
867 } else {
868 rmesa->hw.tex[0].check = check_tex;
869 rmesa->hw.tex[1].check = check_tex;
870 }
871 rmesa->hw.tex[2].check = check_tex;
872 rmesa->hw.tex[3].check = check_tex;
873 rmesa->hw.tex[4].check = check_tex;
874 rmesa->hw.tex[5].check = check_tex;
875 }
876 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
877 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
878 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
879 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
880 } else {
881 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 );
882 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
883 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
884 }
885 }
886 }
887
888 for (i = 0; i < 6; i++)
889 if (rmesa->radeon.radeonScreen->kernel_mm)
890 rmesa->hw.tex[i].emit = tex_emit_mm;
891 else
892 rmesa->hw.tex[i].emit = tex_emit;
893 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
894 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
895 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
896 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
897 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
898 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
899 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
900 for (i = 0; i < 6; i++)
901 if (rmesa->radeon.radeonScreen->kernel_mm) {
902 rmesa->hw.cube[i].emit = cube_emit_cs;
903 rmesa->hw.cube[i].check = check_tex_cube_cs;
904 } else
905 rmesa->hw.cube[i].emit = cube_emit;
906 }
907 else {
908 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
909 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
910 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
911 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
912 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
913 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
914 }
915
916 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
917 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
918 if (rmesa->radeon.radeonScreen->kernel_mm) {
919 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
920 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
921 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
922 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
923 } else {
924 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
925 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
926 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
927 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
928 }
929 }
930 else {
931 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
932 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
933 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
934 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
935 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
936 }
937 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
938 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
939 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
940 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
941 if (rmesa->radeon.radeonScreen->kernel_mm) {
942 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 );
943 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 );
944 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 );
945 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 );
946 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 );
947 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
948 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 );
949 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
950 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 );
951 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 );
952 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
953 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 );
954 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 );
955 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 );
956 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 );
957 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
958 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
959 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
960 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
961 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
962 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
963 ALLOC_STATE( lit[0], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-0", 0 );
964 ALLOC_STATE( lit[1], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-1", 1 );
965 ALLOC_STATE( lit[2], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-2", 2 );
966 ALLOC_STATE( lit[3], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-3", 3 );
967 ALLOC_STATE( lit[4], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-4", 4 );
968 ALLOC_STATE( lit[5], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-5", 5 );
969 ALLOC_STATE( lit[6], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-6", 6 );
970 ALLOC_STATE( lit[7], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-7", 7 );
971 ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 );
972 } else {
973 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
974 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
975 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
976 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
977 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
978 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
979 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
980 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
981 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
982 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
983 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
984 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
985 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
986 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
987 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
988 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
989 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
990 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
991 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
992 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
993 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
994 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
995 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
996 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
997 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
998 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
999 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
1000 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
1001 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
1002 ALLOC_STATE( sci, never, SCI_STATE_SIZE, "SCI/scissor", 0 );
1003 }
1004 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
1005 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
1006 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
1007 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
1008 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
1009 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
1010 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
1011 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1012 }
1013 else {
1014 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1015 }
1016 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
1017 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1018 if (rmesa->radeon.radeonScreen->kernel_mm)
1019 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1020 else
1021 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1022 }
1023 else {
1024 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1025 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1026 }
1027
1028 r200SetUpAtomList( rmesa );
1029
1030 /* Fill in the packet headers:
1031 */
1032 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
1033 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
1034 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
1035 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
1036 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
1037 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
1038 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
1039 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
1040 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
1041 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
1042 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
1043 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
1044 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
1045 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
1046 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
1047 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
1048 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
1049 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
1050 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
1051 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
1052 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1053 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
1054 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
1055 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1056 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
1057 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1058 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
1059 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1060 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
1061 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1062 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
1063 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1064 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
1065 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1066 } else {
1067 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
1068 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1069 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
1070 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1071 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
1072 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1073 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
1074 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1075 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
1076 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1077 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
1078 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1079 }
1080 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
1081 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
1082 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
1083 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
1084 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
1085 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
1086 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
1087 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
1088 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
1089 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
1090 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
1091 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
1092 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
1093 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
1094 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
1095 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
1096 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
1097 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
1098 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
1099 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
1100 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
1101 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
1102 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
1103 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
1104 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
1105 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
1106 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
1107 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
1108 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
1109 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
1110 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
1111 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
1112 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
1113
1114 rmesa->hw.sci.cmd[SCI_CMD_0] = CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0);
1115 rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
1116 rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
1117
1118 if (rmesa->radeon.radeonScreen->kernel_mm) {
1119 rmesa->hw.mtl[0].emit = mtl_emit;
1120 rmesa->hw.mtl[1].emit = mtl_emit;
1121
1122 rmesa->hw.vpi[0].emit = veclinear_emit;
1123 rmesa->hw.vpi[1].emit = veclinear_emit;
1124 rmesa->hw.vpp[0].emit = veclinear_emit;
1125 rmesa->hw.vpp[1].emit = veclinear_emit;
1126
1127 rmesa->hw.grd.emit = scl_emit;
1128 rmesa->hw.fog.emit = vec_emit;
1129 rmesa->hw.glt.emit = vec_emit;
1130 rmesa->hw.eye.emit = vec_emit;
1131
1132 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
1133 rmesa->hw.mat[i].emit = vec_emit;
1134
1135 for (i = 0; i < 8; i++)
1136 rmesa->hw.lit[i].emit = lit_emit;
1137
1138 for (i = 0; i < 6; i++)
1139 rmesa->hw.ucp[i].emit = vec_emit;
1140
1141 rmesa->hw.ptp.emit = ptp_emit;
1142 }
1143
1144
1145
1146 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
1147 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
1148 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
1149 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
1150 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
1151 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
1152 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
1153 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
1154
1155 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
1156 cmdveclinear( R200_PVS_PROG0, 64 );
1157 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
1158 cmdveclinear( R200_PVS_PROG1, 64 );
1159 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
1160 cmdveclinear( R200_PVS_PARAM0, 96 );
1161 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
1162 cmdveclinear( R200_PVS_PARAM1, 96 );
1163
1164 rmesa->hw.grd.cmd[GRD_CMD_0] =
1165 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
1166 rmesa->hw.fog.cmd[FOG_CMD_0] =
1167 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
1168 rmesa->hw.glt.cmd[GLT_CMD_0] =
1169 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
1170 rmesa->hw.eye.cmd[EYE_CMD_0] =
1171 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
1172
1173 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
1174 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
1175 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1176 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1177 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1178 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1179 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1180 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1181 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1182 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1183 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1184 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1185 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1186 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1187 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1188 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1189 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1190 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1191
1192 for (i = 0 ; i < 8; i++) {
1193 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1194 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1195 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1196 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1197 }
1198
1199 for (i = 0 ; i < 6; i++) {
1200 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1201 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1202 }
1203
1204 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1205 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1206 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1207 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1208
1209 /* Initial Harware state:
1210 */
1211 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1212 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1213
1214 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1215 R200_FOG_USE_SPEC_ALPHA);
1216
1217 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1218
1219 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1220 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1221 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1222
1223 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1224 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1225 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1226 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1227 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1228 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1229 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1230 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1231 }
1232
1233 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1234 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1235
1236 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1237 ((rmesa->radeon.radeonScreen->depthPitch &
1238 R200_DEPTHPITCH_MASK) |
1239 R200_DEPTH_ENDIAN_NO_SWAP);
1240
1241 if (rmesa->using_hyperz)
1242 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1243
1244 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1245 R200_STENCIL_TEST_ALWAYS |
1246 R200_STENCIL_FAIL_KEEP |
1247 R200_STENCIL_ZPASS_KEEP |
1248 R200_STENCIL_ZFAIL_KEEP |
1249 R200_Z_WRITE_ENABLE);
1250
1251 if (rmesa->using_hyperz) {
1252 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1253 R200_Z_DECOMPRESSION_ENABLE;
1254 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1255 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1256 }
1257
1258 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1259 | R200_TEX_BLEND_0_ENABLE);
1260
1261 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1262 case DRI_CONF_DITHER_XERRORDIFFRESET:
1263 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1264 break;
1265 case DRI_CONF_DITHER_ORDERED:
1266 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1267 break;
1268 }
1269 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1270 DRI_CONF_ROUND_ROUND )
1271 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1272 else
1273 rmesa->radeon.state.color.roundEnable = 0;
1274 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1275 DRI_CONF_COLOR_REDUCTION_DITHER )
1276 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1277 else
1278 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1279
1280 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1281 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1282 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1283
1284 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1285 R200_BFACE_SOLID |
1286 R200_FFACE_SOLID |
1287 R200_FLAT_SHADE_VTX_LAST |
1288 R200_DIFFUSE_SHADE_GOURAUD |
1289 R200_ALPHA_SHADE_GOURAUD |
1290 R200_SPECULAR_SHADE_GOURAUD |
1291 R200_FOG_SHADE_GOURAUD |
1292 R200_DISC_FOG_SHADE_GOURAUD |
1293 R200_VTX_PIX_CENTER_OGL |
1294 R200_ROUND_MODE_TRUNC |
1295 R200_ROUND_PREC_8TH_PIX);
1296
1297 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1298 R200_SCISSOR_ENABLE);
1299
1300 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1301
1302 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1303 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1304 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1305
1306 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1307
1308 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1309 ((0x00 << R200_STENCIL_REF_SHIFT) |
1310 (0xff << R200_STENCIL_MASK_SHIFT) |
1311 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1312
1313 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1314 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1315
1316 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1317
1318 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1319 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1320 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1321 R200_STIPPLE_BIG_BIT_ORDER);
1322
1323
1324 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1325 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1326 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1327 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1328 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1329 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1330 #ifdef MESA_BIG_ENDIAN
1331 R200_VC_32BIT_SWAP;
1332 #else
1333 R200_VC_NO_SWAP;
1334 #endif
1335
1336 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1337 /* Bypass TCL */
1338 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1339 }
1340
1341 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1342 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1343 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1344 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1345 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1346 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1347 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1348 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1349 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1350 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1351 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1352 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1353 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1354 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1355 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1356
1357
1358 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1359 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1360 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1361 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1362 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1363 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1364
1365 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1366 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1367 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1368 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1369 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1370 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1371 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1372 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1373 (/* R200_TEXCOORD_PROJ | */
1374 0x100000); /* Small default bias */
1375 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1376 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1377 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1378 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1379 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1380 }
1381 else {
1382 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1383 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1384 }
1385
1386 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1387 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1388 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1389 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1390 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1391 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1392 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1393 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1394 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1395 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1396 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1397
1398 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1399 (R200_TXC_ARG_A_ZERO |
1400 R200_TXC_ARG_B_ZERO |
1401 R200_TXC_ARG_C_DIFFUSE_COLOR |
1402 R200_TXC_OP_MADD);
1403
1404 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1405 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1406 R200_TXC_SCALE_1X |
1407 R200_TXC_CLAMP_0_1 |
1408 R200_TXC_OUTPUT_REG_R0);
1409
1410 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1411 (R200_TXA_ARG_A_ZERO |
1412 R200_TXA_ARG_B_ZERO |
1413 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1414 R200_TXA_OP_MADD);
1415
1416 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1417 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1418 R200_TXA_SCALE_1X |
1419 R200_TXA_CLAMP_0_1 |
1420 R200_TXA_OUTPUT_REG_R0);
1421 }
1422
1423 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1424 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1425 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1426 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1427 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1428 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1429
1430 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1431 (R200_VAP_TCL_ENABLE |
1432 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1433
1434 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1435 (R200_VPORT_X_SCALE_ENA |
1436 R200_VPORT_Y_SCALE_ENA |
1437 R200_VPORT_Z_SCALE_ENA |
1438 R200_VPORT_X_OFFSET_ENA |
1439 R200_VPORT_Y_OFFSET_ENA |
1440 R200_VPORT_Z_OFFSET_ENA |
1441 /* FIXME: Turn on for tex rect only */
1442 R200_VTX_ST_DENORMALIZED |
1443 R200_VTX_W0_FMT);
1444
1445
1446 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1447 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1448 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1449 ((R200_VTX_Z0 | R200_VTX_W0 |
1450 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1451 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1452 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1453 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1454
1455
1456 /* Matrix selection */
1457 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1458 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1459
1460 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1461 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1462
1463 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1464 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1465
1466 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1467 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1468 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1469 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1470 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1471
1472 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1473 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1474 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1475
1476
1477 /* General TCL state */
1478 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1479 (R200_SPECULAR_LIGHTS |
1480 R200_DIFFUSE_SPECULAR_COMBINE |
1481 R200_LOCAL_LIGHT_VEC_GL |
1482 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1483 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1484
1485 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1486 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1487 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1488 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1489 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1490 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1491 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1492 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1493 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1494
1495 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1496 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1497 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1498 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1499
1500 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1501 (R200_UCP_IN_CLIP_SPACE |
1502 R200_CULL_FRONT_IS_CCW);
1503
1504 /* Texgen/Texmat state */
1505 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1506 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1507 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1508 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1509 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1510 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1511 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1512 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1513 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1514 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1515 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1516 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1517 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1518 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1519 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1520 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1521 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1522
1523
1524 for (i = 0 ; i < 8; i++) {
1525 struct gl_light *l = &ctx->Light.Light[i];
1526 GLenum p = GL_LIGHT0 + i;
1527 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1528
1529 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1530 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1531 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1532 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1533 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1534 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1535 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1536 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1537 &l->ConstantAttenuation );
1538 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1539 &l->LinearAttenuation );
1540 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1541 &l->QuadraticAttenuation );
1542 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1543 }
1544
1545 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1546 ctx->Light.Model.Ambient );
1547
1548 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1549
1550 for (i = 0 ; i < 6; i++) {
1551 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1552 }
1553
1554 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1555 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1556 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1557 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1558 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1559 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1560
1561 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1562 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1563 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1564 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1565
1566 rmesa->hw.eye.cmd[EYE_X] = 0;
1567 rmesa->hw.eye.cmd[EYE_Y] = 0;
1568 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1569 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1570
1571 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1572 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1573
1574 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1575 location? In any case, since point attenuation triggers _needeyecoords,
1576 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1577 isn't set */
1578 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1579 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1580 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1581 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1582 /* no idea what the ptp_vport_scale values are good for, except the
1583 PTSIZE one - hopefully doesn't matter */
1584 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1585 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1586 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1587 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1588 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1589 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1590 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1591 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1592 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1593 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1594 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1595 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1596
1597 r200LightingSpaceChange( ctx );
1598
1599 rmesa->radeon.hw.all_dirty = GL_TRUE;
1600
1601 rcommonInitCmdBuf(&rmesa->radeon);
1602 }