b7200990c2256fbb7e104cc0e5c408e00ca88608
[mesa.git] / src / mesa / drivers / dri / r300 / compiler / radeon_opcodes.c
1 /*
2 * Copyright (C) 2009 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "radeon_opcodes.h"
29
30 struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
31 {
32 .Opcode = RC_OPCODE_NOP,
33 .Name = "NOP"
34 },
35 {
36 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
37 .Name = "ILLEGAL OPCODE"
38 },
39 {
40 .Opcode = RC_OPCODE_ABS,
41 .Name = "ABS",
42 .NumSrcRegs = 1,
43 .HasDstReg = 1,
44 .IsComponentwise = 1
45 },
46 {
47 .Opcode = RC_OPCODE_ADD,
48 .Name = "ADD",
49 .NumSrcRegs = 2,
50 .HasDstReg = 1,
51 .IsComponentwise = 1
52 },
53 {
54 .Opcode = RC_OPCODE_ARL,
55 .Name = "ARL",
56 .NumSrcRegs = 1,
57 .HasDstReg = 1
58 },
59 {
60 .Opcode = RC_OPCODE_CMP,
61 .Name = "CMP",
62 .NumSrcRegs = 3,
63 .HasDstReg = 1,
64 .IsComponentwise = 1
65 },
66 {
67 .Opcode = RC_OPCODE_COS,
68 .Name = "COS",
69 .NumSrcRegs = 1,
70 .HasDstReg = 1,
71 .IsStandardScalar = 1
72 },
73 {
74 .Opcode = RC_OPCODE_DDX,
75 .Name = "DDX",
76 .NumSrcRegs = 1,
77 .HasDstReg = 1,
78 .IsComponentwise = 1
79 },
80 {
81 .Opcode = RC_OPCODE_DDY,
82 .Name = "DDY",
83 .NumSrcRegs = 1,
84 .HasDstReg = 1,
85 .IsComponentwise = 1
86 },
87 {
88 .Opcode = RC_OPCODE_DP3,
89 .Name = "DP3",
90 .NumSrcRegs = 2,
91 .HasDstReg = 1
92 },
93 {
94 .Opcode = RC_OPCODE_DP4,
95 .Name = "DP4",
96 .NumSrcRegs = 2,
97 .HasDstReg = 1
98 },
99 {
100 .Opcode = RC_OPCODE_DPH,
101 .Name = "DPH",
102 .NumSrcRegs = 2,
103 .HasDstReg = 1
104 },
105 {
106 .Opcode = RC_OPCODE_DST,
107 .Name = "DST",
108 .NumSrcRegs = 2,
109 .HasDstReg = 1
110 },
111 {
112 .Opcode = RC_OPCODE_EX2,
113 .Name = "EX2",
114 .NumSrcRegs = 1,
115 .HasDstReg = 1,
116 .IsStandardScalar = 1
117 },
118 {
119 .Opcode = RC_OPCODE_EXP,
120 .Name = "EXP",
121 .NumSrcRegs = 1,
122 .HasDstReg = 1
123 },
124 {
125 .Opcode = RC_OPCODE_FLR,
126 .Name = "FLR",
127 .NumSrcRegs = 1,
128 .HasDstReg = 1,
129 .IsComponentwise = 1
130 },
131 {
132 .Opcode = RC_OPCODE_FRC,
133 .Name = "FRC",
134 .NumSrcRegs = 1,
135 .HasDstReg = 1,
136 .IsComponentwise = 1
137 },
138 {
139 .Opcode = RC_OPCODE_KIL,
140 .Name = "KIL",
141 .NumSrcRegs = 1
142 },
143 {
144 .Opcode = RC_OPCODE_LG2,
145 .Name = "LG2",
146 .NumSrcRegs = 1,
147 .HasDstReg = 1,
148 .IsStandardScalar = 1
149 },
150 {
151 .Opcode = RC_OPCODE_LIT,
152 .Name = "LIT",
153 .NumSrcRegs = 1,
154 .HasDstReg = 1
155 },
156 {
157 .Opcode = RC_OPCODE_LOG,
158 .Name = "LOG",
159 .NumSrcRegs = 1,
160 .HasDstReg = 1
161 },
162 {
163 .Opcode = RC_OPCODE_LRP,
164 .Name = "LRP",
165 .NumSrcRegs = 3,
166 .HasDstReg = 1,
167 .IsComponentwise = 1
168 },
169 {
170 .Opcode = RC_OPCODE_MAD,
171 .Name = "MAD",
172 .NumSrcRegs = 3,
173 .HasDstReg = 1,
174 .IsComponentwise = 1
175 },
176 {
177 .Opcode = RC_OPCODE_MAX,
178 .Name = "MAX",
179 .NumSrcRegs = 2,
180 .HasDstReg = 1,
181 .IsComponentwise = 1
182 },
183 {
184 .Opcode = RC_OPCODE_MIN,
185 .Name = "MIN",
186 .NumSrcRegs = 2,
187 .HasDstReg = 1,
188 .IsComponentwise = 1
189 },
190 {
191 .Opcode = RC_OPCODE_MOV,
192 .Name = "MOV",
193 .NumSrcRegs = 1,
194 .HasDstReg = 1,
195 .IsComponentwise = 1
196 },
197 {
198 .Opcode = RC_OPCODE_MUL,
199 .Name = "MUL",
200 .NumSrcRegs = 2,
201 .HasDstReg = 1,
202 .IsComponentwise = 1
203 },
204 {
205 .Opcode = RC_OPCODE_POW,
206 .Name = "POW",
207 .NumSrcRegs = 2,
208 .HasDstReg = 1,
209 .IsStandardScalar = 1
210 },
211 {
212 .Opcode = RC_OPCODE_RCP,
213 .Name = "RCP",
214 .NumSrcRegs = 1,
215 .HasDstReg = 1,
216 .IsStandardScalar = 1
217 },
218 {
219 .Opcode = RC_OPCODE_RSQ,
220 .Name = "RSQ",
221 .NumSrcRegs = 1,
222 .HasDstReg = 1,
223 .IsStandardScalar = 1
224 },
225 {
226 .Opcode = RC_OPCODE_SCS,
227 .Name = "SCS",
228 .NumSrcRegs = 1,
229 .HasDstReg = 1
230 },
231 {
232 .Opcode = RC_OPCODE_SEQ,
233 .Name = "SEQ",
234 .NumSrcRegs = 2,
235 .HasDstReg = 1,
236 .IsComponentwise = 1
237 },
238 {
239 .Opcode = RC_OPCODE_SFL,
240 .Name = "SFL",
241 .NumSrcRegs = 0,
242 .HasDstReg = 1,
243 .IsComponentwise = 1
244 },
245 {
246 .Opcode = RC_OPCODE_SGE,
247 .Name = "SGE",
248 .NumSrcRegs = 2,
249 .HasDstReg = 1,
250 .IsComponentwise = 1
251 },
252 {
253 .Opcode = RC_OPCODE_SGT,
254 .Name = "SGT",
255 .NumSrcRegs = 2,
256 .HasDstReg = 1,
257 .IsComponentwise = 1
258 },
259 {
260 .Opcode = RC_OPCODE_SIN,
261 .Name = "SIN",
262 .NumSrcRegs = 1,
263 .HasDstReg = 1,
264 .IsStandardScalar = 1
265 },
266 {
267 .Opcode = RC_OPCODE_SLE,
268 .Name = "SLE",
269 .NumSrcRegs = 2,
270 .HasDstReg = 1,
271 .IsComponentwise = 1
272 },
273 {
274 .Opcode = RC_OPCODE_SLT,
275 .Name = "SLT",
276 .NumSrcRegs = 2,
277 .HasDstReg = 1,
278 .IsComponentwise = 1
279 },
280 {
281 .Opcode = RC_OPCODE_SNE,
282 .Name = "SNE",
283 .NumSrcRegs = 2,
284 .HasDstReg = 1,
285 .IsComponentwise = 1
286 },
287 {
288 .Opcode = RC_OPCODE_SUB,
289 .Name = "SUB",
290 .NumSrcRegs = 2,
291 .HasDstReg = 1,
292 .IsComponentwise = 1
293 },
294 {
295 .Opcode = RC_OPCODE_SWZ,
296 .Name = "SWZ",
297 .NumSrcRegs = 1,
298 .HasDstReg = 1,
299 .IsComponentwise = 1
300 },
301 {
302 .Opcode = RC_OPCODE_XPD,
303 .Name = "XPD",
304 .NumSrcRegs = 2,
305 .HasDstReg = 1
306 },
307 {
308 .Opcode = RC_OPCODE_TEX,
309 .Name = "TEX",
310 .HasTexture = 1,
311 .NumSrcRegs = 1,
312 .HasDstReg = 1
313 },
314 {
315 .Opcode = RC_OPCODE_TXB,
316 .Name = "TXB",
317 .HasTexture = 1,
318 .NumSrcRegs = 1,
319 .HasDstReg = 1
320 },
321 {
322 .Opcode = RC_OPCODE_TXD,
323 .Name = "TXD",
324 .HasTexture = 1,
325 .NumSrcRegs = 3,
326 .HasDstReg = 1
327 },
328 {
329 .Opcode = RC_OPCODE_TXL,
330 .Name = "TXL",
331 .HasTexture = 1,
332 .NumSrcRegs = 1,
333 .HasDstReg = 1
334 },
335 {
336 .Opcode = RC_OPCODE_TXP,
337 .Name = "TXP",
338 .HasTexture = 1,
339 .NumSrcRegs = 1,
340 .HasDstReg = 1
341 },
342 {
343 .Opcode = RC_OPCODE_REPL_ALPHA,
344 .Name = "REPL_ALPHA",
345 .HasDstReg = 1
346 }
347 };