src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c

   1 /*
   2  * Copyright (C) 2009 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_opcodes.h"
  29
  30 #include "radeon_program_constants.h"
  31
  32 struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
  33         {
  34                 .Opcode = RC_OPCODE_NOP,
  35                 .Name = "NOP"
  36         },
  37         {
  38                 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
  39                 .Name = "ILLEGAL OPCODE"
  40         },
  41         {
  42                 .Opcode = RC_OPCODE_ABS,
  43                 .Name = "ABS",
  44                 .NumSrcRegs = 1,
  45                 .HasDstReg = 1,
  46                 .IsComponentwise = 1
  47         },
  48         {
  49                 .Opcode = RC_OPCODE_ADD,
  50                 .Name = "ADD",
  51                 .NumSrcRegs = 2,
  52                 .HasDstReg = 1,
  53                 .IsComponentwise = 1
  54         },
  55         {
  56                 .Opcode = RC_OPCODE_ARL,
  57                 .Name = "ARL",
  58                 .NumSrcRegs = 1,
  59                 .HasDstReg = 1
  60         },
  61         {
  62                 .Opcode = RC_OPCODE_CMP,
  63                 .Name = "CMP",
  64                 .NumSrcRegs = 3,
  65                 .HasDstReg = 1,
  66                 .IsComponentwise = 1
  67         },
  68         {
  69                 .Opcode = RC_OPCODE_COS,
  70                 .Name = "COS",
  71                 .NumSrcRegs = 1,
  72                 .HasDstReg = 1,
  73                 .IsStandardScalar = 1
  74         },
  75         {
  76                 .Opcode = RC_OPCODE_DDX,
  77                 .Name = "DDX",
  78                 .NumSrcRegs = 1,
  79                 .HasDstReg = 1,
  80                 .IsComponentwise = 1
  81         },
  82         {
  83                 .Opcode = RC_OPCODE_DDY,
  84                 .Name = "DDY",
  85                 .NumSrcRegs = 1,
  86                 .HasDstReg = 1,
  87                 .IsComponentwise = 1
  88         },
  89         {
  90                 .Opcode = RC_OPCODE_DP3,
  91                 .Name = "DP3",
  92                 .NumSrcRegs = 2,
  93                 .HasDstReg = 1
  94         },
  95         {
  96                 .Opcode = RC_OPCODE_DP4,
  97                 .Name = "DP4",
  98                 .NumSrcRegs = 2,
  99                 .HasDstReg = 1
 100         },
 101         {
 102                 .Opcode = RC_OPCODE_DPH,
 103                 .Name = "DPH",
 104                 .NumSrcRegs = 2,
 105                 .HasDstReg = 1
 106         },
 107         {
 108                 .Opcode = RC_OPCODE_DST,
 109                 .Name = "DST",
 110                 .NumSrcRegs = 2,
 111                 .HasDstReg = 1
 112         },
 113         {
 114                 .Opcode = RC_OPCODE_EX2,
 115                 .Name = "EX2",
 116                 .NumSrcRegs = 1,
 117                 .HasDstReg = 1,
 118                 .IsStandardScalar = 1
 119         },
 120         {
 121                 .Opcode = RC_OPCODE_EXP,
 122                 .Name = "EXP",
 123                 .NumSrcRegs = 1,
 124                 .HasDstReg = 1
 125         },
 126         {
 127                 .Opcode = RC_OPCODE_FLR,
 128                 .Name = "FLR",
 129                 .NumSrcRegs = 1,
 130                 .HasDstReg = 1,
 131                 .IsComponentwise = 1
 132         },
 133         {
 134                 .Opcode = RC_OPCODE_FRC,
 135                 .Name = "FRC",
 136                 .NumSrcRegs = 1,
 137                 .HasDstReg = 1,
 138                 .IsComponentwise = 1
 139         },
 140         {
 141                 .Opcode = RC_OPCODE_KIL,
 142                 .Name = "KIL",
 143                 .NumSrcRegs = 1
 144         },
 145         {
 146                 .Opcode = RC_OPCODE_LG2,
 147                 .Name = "LG2",
 148                 .NumSrcRegs = 1,
 149                 .HasDstReg = 1,
 150                 .IsStandardScalar = 1
 151         },
 152         {
 153                 .Opcode = RC_OPCODE_LIT,
 154                 .Name = "LIT",
 155                 .NumSrcRegs = 1,
 156                 .HasDstReg = 1
 157         },
 158         {
 159                 .Opcode = RC_OPCODE_LOG,
 160                 .Name = "LOG",
 161                 .NumSrcRegs = 1,
 162                 .HasDstReg = 1
 163         },
 164         {
 165                 .Opcode = RC_OPCODE_LRP,
 166                 .Name = "LRP",
 167                 .NumSrcRegs = 3,
 168                 .HasDstReg = 1,
 169                 .IsComponentwise = 1
 170         },
 171         {
 172                 .Opcode = RC_OPCODE_MAD,
 173                 .Name = "MAD",
 174                 .NumSrcRegs = 3,
 175                 .HasDstReg = 1,
 176                 .IsComponentwise = 1
 177         },
 178         {
 179                 .Opcode = RC_OPCODE_MAX,
 180                 .Name = "MAX",
 181                 .NumSrcRegs = 2,
 182                 .HasDstReg = 1,
 183                 .IsComponentwise = 1
 184         },
 185         {
 186                 .Opcode = RC_OPCODE_MIN,
 187                 .Name = "MIN",
 188                 .NumSrcRegs = 2,
 189                 .HasDstReg = 1,
 190                 .IsComponentwise = 1
 191         },
 192         {
 193                 .Opcode = RC_OPCODE_MOV,
 194                 .Name = "MOV",
 195                 .NumSrcRegs = 1,
 196                 .HasDstReg = 1,
 197                 .IsComponentwise = 1
 198         },
 199         {
 200                 .Opcode = RC_OPCODE_MUL,
 201                 .Name = "MUL",
 202                 .NumSrcRegs = 2,
 203                 .HasDstReg = 1,
 204                 .IsComponentwise = 1
 205         },
 206         {
 207                 .Opcode = RC_OPCODE_POW,
 208                 .Name = "POW",
 209                 .NumSrcRegs = 2,
 210                 .HasDstReg = 1,
 211                 .IsStandardScalar = 1
 212         },
 213         {
 214                 .Opcode = RC_OPCODE_RCP,
 215                 .Name = "RCP",
 216                 .NumSrcRegs = 1,
 217                 .HasDstReg = 1,
 218                 .IsStandardScalar = 1
 219         },
 220         {
 221                 .Opcode = RC_OPCODE_RSQ,
 222                 .Name = "RSQ",
 223                 .NumSrcRegs = 1,
 224                 .HasDstReg = 1,
 225                 .IsStandardScalar = 1
 226         },
 227         {
 228                 .Opcode = RC_OPCODE_SCS,
 229                 .Name = "SCS",
 230                 .NumSrcRegs = 1,
 231                 .HasDstReg = 1
 232         },
 233         {
 234                 .Opcode = RC_OPCODE_SEQ,
 235                 .Name = "SEQ",
 236                 .NumSrcRegs = 2,
 237                 .HasDstReg = 1,
 238                 .IsComponentwise = 1
 239         },
 240         {
 241                 .Opcode = RC_OPCODE_SFL,
 242                 .Name = "SFL",
 243                 .NumSrcRegs = 0,
 244                 .HasDstReg = 1,
 245                 .IsComponentwise = 1
 246         },
 247         {
 248                 .Opcode = RC_OPCODE_SGE,
 249                 .Name = "SGE",
 250                 .NumSrcRegs = 2,
 251                 .HasDstReg = 1,
 252                 .IsComponentwise = 1
 253         },
 254         {
 255                 .Opcode = RC_OPCODE_SGT,
 256                 .Name = "SGT",
 257                 .NumSrcRegs = 2,
 258                 .HasDstReg = 1,
 259                 .IsComponentwise = 1
 260         },
 261         {
 262                 .Opcode = RC_OPCODE_SIN,
 263                 .Name = "SIN",
 264                 .NumSrcRegs = 1,
 265                 .HasDstReg = 1,
 266                 .IsStandardScalar = 1
 267         },
 268         {
 269                 .Opcode = RC_OPCODE_SLE,
 270                 .Name = "SLE",
 271                 .NumSrcRegs = 2,
 272                 .HasDstReg = 1,
 273                 .IsComponentwise = 1
 274         },
 275         {
 276                 .Opcode = RC_OPCODE_SLT,
 277                 .Name = "SLT",
 278                 .NumSrcRegs = 2,
 279                 .HasDstReg = 1,
 280                 .IsComponentwise = 1
 281         },
 282         {
 283                 .Opcode = RC_OPCODE_SNE,
 284                 .Name = "SNE",
 285                 .NumSrcRegs = 2,
 286                 .HasDstReg = 1,
 287                 .IsComponentwise = 1
 288         },
 289         {
 290                 .Opcode = RC_OPCODE_SUB,
 291                 .Name = "SUB",
 292                 .NumSrcRegs = 2,
 293                 .HasDstReg = 1,
 294                 .IsComponentwise = 1
 295         },
 296         {
 297                 .Opcode = RC_OPCODE_SWZ,
 298                 .Name = "SWZ",
 299                 .NumSrcRegs = 1,
 300                 .HasDstReg = 1,
 301                 .IsComponentwise = 1
 302         },
 303         {
 304                 .Opcode = RC_OPCODE_XPD,
 305                 .Name = "XPD",
 306                 .NumSrcRegs = 2,
 307                 .HasDstReg = 1
 308         },
 309         {
 310                 .Opcode = RC_OPCODE_TEX,
 311                 .Name = "TEX",
 312                 .HasTexture = 1,
 313                 .NumSrcRegs = 1,
 314                 .HasDstReg = 1
 315         },
 316         {
 317                 .Opcode = RC_OPCODE_TXB,
 318                 .Name = "TXB",
 319                 .HasTexture = 1,
 320                 .NumSrcRegs = 1,
 321                 .HasDstReg = 1
 322         },
 323         {
 324                 .Opcode = RC_OPCODE_TXD,
 325                 .Name = "TXD",
 326                 .HasTexture = 1,
 327                 .NumSrcRegs = 3,
 328                 .HasDstReg = 1
 329         },
 330         {
 331                 .Opcode = RC_OPCODE_TXL,
 332                 .Name = "TXL",
 333                 .HasTexture = 1,
 334                 .NumSrcRegs = 1,
 335                 .HasDstReg = 1
 336         },
 337         {
 338                 .Opcode = RC_OPCODE_TXP,
 339                 .Name = "TXP",
 340                 .HasTexture = 1,
 341                 .NumSrcRegs = 1,
 342                 .HasDstReg = 1
 343         },
 344         {
 345                 .Opcode = RC_OPCODE_IF,
 346                 .Name = "IF",
 347                 .IsFlowControl = 1,
 348                 .NumSrcRegs = 1
 349         },
 350         {
 351                 .Opcode = RC_OPCODE_ELSE,
 352                 .Name = "ELSE",
 353                 .IsFlowControl = 1,
 354                 .NumSrcRegs = 0
 355         },
 356         {
 357                 .Opcode = RC_OPCODE_ENDIF,
 358                 .Name = "ENDIF",
 359                 .IsFlowControl = 1,
 360                 .NumSrcRegs = 0
 361         },
 362         {
 363                 .Opcode = RC_OPCODE_REPL_ALPHA,
 364                 .Name = "REPL_ALPHA",
 365                 .HasDstReg = 1
 366         },
 367         {
 368                 .Opcode = RC_OPCODE_BEGIN_TEX,
 369                 .Name = "BEGIN_TEX"
 370         }
 371 };
 372
 373 void rc_compute_sources_for_writemask(
 374                 const struct rc_opcode_info * opcode,
 375                 unsigned int writemask,
 376                 unsigned int *srcmasks)
 377 {
 378         srcmasks[0] = 0;
 379         srcmasks[1] = 0;
 380         srcmasks[2] = 0;
 381
 382         if (opcode->Opcode == RC_OPCODE_KIL)
 383                 srcmasks[0] |= RC_MASK_XYZW;
 384         else if (opcode->Opcode == RC_OPCODE_IF)
 385                 srcmasks[0] |= RC_MASK_X;
 386
 387         if (!writemask)
 388                 return;
 389
 390         if (opcode->IsComponentwise) {
 391                 for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
 392                         srcmasks[src] |= writemask;
 393         } else if (opcode->IsStandardScalar) {
 394                 for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
 395                         srcmasks[src] |= RC_MASK_X;
 396         } else {
 397                 switch(opcode->Opcode) {
 398                 case RC_OPCODE_ARL:
 399                         srcmasks[0] |= RC_MASK_X;
 400                         break;
 401                 case RC_OPCODE_DP3:
 402                         srcmasks[0] |= RC_MASK_XYZ;
 403                         srcmasks[1] |= RC_MASK_XYZ;
 404                         break;
 405                 case RC_OPCODE_DP4:
 406                         srcmasks[0] |= RC_MASK_XYZW;
 407                         srcmasks[1] |= RC_MASK_XYZW;
 408                         break;
 409                 case RC_OPCODE_TEX:
 410                 case RC_OPCODE_TXB:
 411                 case RC_OPCODE_TXP:
 412                         srcmasks[0] |= RC_MASK_XYZW;
 413                         break;
 414                 case RC_OPCODE_DST:
 415                         srcmasks[0] |= 0x6;
 416                         srcmasks[1] |= 0xa;
 417                         break;
 418                 case RC_OPCODE_EXP:
 419                 case RC_OPCODE_LOG:
 420                         srcmasks[0] |= RC_MASK_XY;
 421                         break;
 422                 case RC_OPCODE_LIT:
 423                         srcmasks[0] |= 0xb;
 424                         break;
 425                 default:
 426                         break;
 427                 }
 428         }
 429 }