src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c

   1 /*
   2  * Copyright (C) 2009 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_program_pair.h"
  29
  30 #include "radeon_compiler.h"
  31
  32
  33 /**
  34  * Finally rewrite ADD, MOV, MUL as the appropriate native instruction
  35  * and reverse the order of arguments for CMP.
  36  */
  37 static void final_rewrite(struct rc_sub_instruction *inst)
  38 {
  39         struct rc_src_register tmp;
  40
  41         switch(inst->Opcode) {
  42         case RC_OPCODE_ADD:
  43                 inst->SrcReg[2] = inst->SrcReg[1];
  44                 inst->SrcReg[1].File = RC_FILE_NONE;
  45                 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
  46                 inst->SrcReg[1].Negate = RC_MASK_NONE;
  47                 inst->Opcode = RC_OPCODE_MAD;
  48                 break;
  49         case RC_OPCODE_CMP:
  50                 tmp = inst->SrcReg[2];
  51                 inst->SrcReg[2] = inst->SrcReg[0];
  52                 inst->SrcReg[0] = tmp;
  53                 break;
  54         case RC_OPCODE_MOV:
  55                 /* AMD say we should use CMP.
  56                  * However, when we transform
  57                  *  KIL -r0;
  58                  * into
  59                  *  CMP tmp, -r0, -r0, 0;
  60                  *  KIL tmp;
  61                  * we get incorrect behaviour on R500 when r0 == 0.0.
  62                  * It appears that the R500 KIL hardware treats -0.0 as less
  63                  * than zero.
  64                  */
  65                 inst->SrcReg[1].File = RC_FILE_NONE;
  66                 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
  67                 inst->SrcReg[2].File = RC_FILE_NONE;
  68                 inst->SrcReg[2].Swizzle = RC_SWIZZLE_0000;
  69                 inst->Opcode = RC_OPCODE_MAD;
  70                 break;
  71         case RC_OPCODE_MUL:
  72                 inst->SrcReg[2].File = RC_FILE_NONE;
  73                 inst->SrcReg[2].Swizzle = RC_SWIZZLE_0000;
  74                 inst->Opcode = RC_OPCODE_MAD;
  75                 break;
  76         default:
  77                 /* nothing to do */
  78                 break;
  79         }
  80 }
  81
  82
  83 /**
  84  * Classify an instruction according to which ALUs etc. it needs
  85  */
  86 static void classify_instruction(struct rc_sub_instruction * inst,
  87         int * needrgb, int * needalpha, int * istranscendent)
  88 {
  89         *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
  90         *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
  91         *istranscendent = 0;
  92
  93         if (inst->WriteALUResult == RC_ALURESULT_X)
  94                 *needrgb = 1;
  95         else if (inst->WriteALUResult == RC_ALURESULT_W)
  96                 *needalpha = 1;
  97
  98         switch(inst->Opcode) {
  99         case RC_OPCODE_ADD:
 100         case RC_OPCODE_CMP:
 101         case RC_OPCODE_DDX:
 102         case RC_OPCODE_DDY:
 103         case RC_OPCODE_FRC:
 104         case RC_OPCODE_MAD:
 105         case RC_OPCODE_MAX:
 106         case RC_OPCODE_MIN:
 107         case RC_OPCODE_MOV:
 108         case RC_OPCODE_MUL:
 109                 break;
 110         case RC_OPCODE_COS:
 111         case RC_OPCODE_EX2:
 112         case RC_OPCODE_LG2:
 113         case RC_OPCODE_RCP:
 114         case RC_OPCODE_RSQ:
 115         case RC_OPCODE_SIN:
 116                 *istranscendent = 1;
 117                 *needalpha = 1;
 118                 break;
 119         case RC_OPCODE_DP4:
 120                 *needalpha = 1;
 121                 /* fall through */
 122         case RC_OPCODE_DP3:
 123                 *needrgb = 1;
 124                 break;
 125         default:
 126                 break;
 127         }
 128 }
 129
 130
 131 /**
 132  * Fill the given ALU instruction's opcodes and source operands into the given pair,
 133  * if possible.
 134  */
 135 static void set_pair_instruction(struct r300_fragment_program_compiler *c,
 136         struct rc_pair_instruction * pair,
 137         struct rc_sub_instruction * inst)
 138 {
 139         memset(pair, 0, sizeof(struct rc_pair_instruction));
 140
 141         int needrgb, needalpha, istranscendent;
 142         classify_instruction(inst, &needrgb, &needalpha, &istranscendent);
 143
 144         if (needrgb) {
 145                 if (istranscendent)
 146                         pair->RGB.Opcode = RC_OPCODE_REPL_ALPHA;
 147                 else
 148                         pair->RGB.Opcode = inst->Opcode;
 149                 if (inst->SaturateMode == RC_SATURATE_ZERO_ONE)
 150                         pair->RGB.Saturate = 1;
 151         }
 152         if (needalpha) {
 153                 pair->Alpha.Opcode = inst->Opcode;
 154                 if (inst->SaturateMode == RC_SATURATE_ZERO_ONE)
 155                         pair->Alpha.Saturate = 1;
 156         }
 157
 158         const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode);
 159         int nargs = opcode->NumSrcRegs;
 160         int i;
 161
 162         /* Special case for DDX/DDY (MDH/MDV). */
 163         if (inst->Opcode == RC_OPCODE_DDX || inst->Opcode == RC_OPCODE_DDY) {
 164                 nargs++;
 165         }
 166
 167         for(i = 0; i < opcode->NumSrcRegs; ++i) {
 168                 int source;
 169                 if (needrgb && !istranscendent) {
 170                         unsigned int srcrgb = 0;
 171                         unsigned int srcalpha = 0;
 172                         int j;
 173                         for(j = 0; j < 3; ++j) {
 174                                 unsigned int swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
 175                                 if (swz < 3)
 176                                         srcrgb = 1;
 177                                 else if (swz < 4)
 178                                         srcalpha = 1;
 179                         }
 180                         source = rc_pair_alloc_source(pair, srcrgb, srcalpha,
 181                                                         inst->SrcReg[i].File, inst->SrcReg[i].Index);
 182                         pair->RGB.Arg[i].Source = source;
 183                         pair->RGB.Arg[i].Swizzle = inst->SrcReg[i].Swizzle & 0x1ff;
 184                         pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs;
 185                         pair->RGB.Arg[i].Negate = !!(inst->SrcReg[i].Negate & (RC_MASK_X | RC_MASK_Y | RC_MASK_Z));
 186                 }
 187                 if (needalpha) {
 188                         unsigned int srcrgb = 0;
 189                         unsigned int srcalpha = 0;
 190                         unsigned int swz = GET_SWZ(inst->SrcReg[i].Swizzle, istranscendent ? 0 : 3);
 191                         if (swz < 3)
 192                                 srcrgb = 1;
 193                         else if (swz < 4)
 194                                 srcalpha = 1;
 195                         source = rc_pair_alloc_source(pair, srcrgb, srcalpha,
 196                                                         inst->SrcReg[i].File, inst->SrcReg[i].Index);
 197                         pair->Alpha.Arg[i].Source = source;
 198                         pair->Alpha.Arg[i].Swizzle = swz;
 199                         pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs;
 200                         pair->Alpha.Arg[i].Negate = !!(inst->SrcReg[i].Negate & RC_MASK_W);
 201                 }
 202         }
 203
 204         /* Destination handling */
 205         if (inst->DstReg.File == RC_FILE_OUTPUT) {
 206                 if (inst->DstReg.Index == c->OutputColor) {
 207                         pair->RGB.OutputWriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
 208                         pair->Alpha.OutputWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
 209                 } else if (inst->DstReg.Index == c->OutputDepth) {
 210                         pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
 211                 }
 212         } else {
 213                 if (needrgb) {
 214                         pair->RGB.DestIndex = inst->DstReg.Index;
 215                         pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
 216                 }
 217                 if (needalpha) {
 218                         pair->Alpha.DestIndex = inst->DstReg.Index;
 219                         pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
 220                 }
 221         }
 222
 223         if (inst->WriteALUResult) {
 224                 pair->WriteALUResult = inst->WriteALUResult;
 225                 pair->ALUResultCompare = inst->ALUResultCompare;
 226         }
 227 }
 228
 229
 230 /**
 231  * Translate all ALU instructions into corresponding pair instructions,
 232  * performing no other changes.
 233  */
 234 void rc_pair_translate(struct r300_fragment_program_compiler *c)
 235 {
 236         for(struct rc_instruction * inst = c->Base.Program.Instructions.Next;
 237             inst != &c->Base.Program.Instructions;
 238             inst = inst->Next) {
 239                 if (inst->Type != RC_INSTRUCTION_NORMAL)
 240                         continue;
 241
 242                 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
 243
 244                 if (opcode->HasTexture || opcode->IsFlowControl || opcode->Opcode == RC_OPCODE_KIL)
 245                         continue;
 246
 247                 struct rc_sub_instruction copy = inst->U.I;
 248
 249                 final_rewrite(&copy);
 250                 inst->Type = RC_INSTRUCTION_PAIR;
 251                 set_pair_instruction(c, &inst->U.P, &copy);
 252         }
 253 }