src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c

   1 /*
   2  * Copyright (C) 2008 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /**
  29  * @file
  30  *
  31  * Shareable transformations that transform "special" ALU instructions
  32  * into ALU instructions that are supported by hardware.
  33  *
  34  */
  35
  36 #include "radeon_program_alu.h"
  37
  38 #include "radeon_compiler.h"
  39
  40
  41 static struct rc_instruction *emit1(
  42         struct radeon_compiler * c, struct rc_instruction * after,
  43         rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
  44         struct rc_src_register SrcReg)
  45 {
  46         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  47
  48         fpi->U.I.Opcode = Opcode;
  49         fpi->U.I.SaturateMode = Saturate;
  50         fpi->U.I.DstReg = DstReg;
  51         fpi->U.I.SrcReg[0] = SrcReg;
  52         return fpi;
  53 }
  54
  55 static struct rc_instruction *emit2(
  56         struct radeon_compiler * c, struct rc_instruction * after,
  57         rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
  58         struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
  59 {
  60         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  61
  62         fpi->U.I.Opcode = Opcode;
  63         fpi->U.I.SaturateMode = Saturate;
  64         fpi->U.I.DstReg = DstReg;
  65         fpi->U.I.SrcReg[0] = SrcReg0;
  66         fpi->U.I.SrcReg[1] = SrcReg1;
  67         return fpi;
  68 }
  69
  70 static struct rc_instruction *emit3(
  71         struct radeon_compiler * c, struct rc_instruction * after,
  72         rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
  73         struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
  74         struct rc_src_register SrcReg2)
  75 {
  76         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  77
  78         fpi->U.I.Opcode = Opcode;
  79         fpi->U.I.SaturateMode = Saturate;
  80         fpi->U.I.DstReg = DstReg;
  81         fpi->U.I.SrcReg[0] = SrcReg0;
  82         fpi->U.I.SrcReg[1] = SrcReg1;
  83         fpi->U.I.SrcReg[2] = SrcReg2;
  84         return fpi;
  85 }
  86
  87 static struct rc_dst_register dstreg(int file, int index)
  88 {
  89         struct rc_dst_register dst;
  90         dst.File = file;
  91         dst.Index = index;
  92         dst.WriteMask = RC_MASK_XYZW;
  93         dst.RelAddr = 0;
  94         return dst;
  95 }
  96
  97 static struct rc_dst_register dstregtmpmask(int index, int mask)
  98 {
  99         struct rc_dst_register dst = {0};
 100         dst.File = RC_FILE_TEMPORARY;
 101         dst.Index = index;
 102         dst.WriteMask = mask;
 103         dst.RelAddr = 0;
 104         return dst;
 105 }
 106
 107 static const struct rc_src_register builtin_zero = {
 108         .File = RC_FILE_NONE,
 109         .Index = 0,
 110         .Swizzle = RC_SWIZZLE_0000
 111 };
 112 static const struct rc_src_register builtin_one = {
 113         .File = RC_FILE_NONE,
 114         .Index = 0,
 115         .Swizzle = RC_SWIZZLE_1111
 116 };
 117 static const struct rc_src_register srcreg_undefined = {
 118         .File = RC_FILE_NONE,
 119         .Index = 0,
 120         .Swizzle = RC_SWIZZLE_XYZW
 121 };
 122
 123 static struct rc_src_register srcreg(int file, int index)
 124 {
 125         struct rc_src_register src = srcreg_undefined;
 126         src.File = file;
 127         src.Index = index;
 128         return src;
 129 }
 130
 131 static struct rc_src_register srcregswz(int file, int index, int swz)
 132 {
 133         struct rc_src_register src = srcreg_undefined;
 134         src.File = file;
 135         src.Index = index;
 136         src.Swizzle = swz;
 137         return src;
 138 }
 139
 140 static struct rc_src_register absolute(struct rc_src_register reg)
 141 {
 142         struct rc_src_register newreg = reg;
 143         newreg.Abs = 1;
 144         newreg.Negate = RC_MASK_NONE;
 145         return newreg;
 146 }
 147
 148 static struct rc_src_register negate(struct rc_src_register reg)
 149 {
 150         struct rc_src_register newreg = reg;
 151         newreg.Negate = newreg.Negate ^ RC_MASK_XYZW;
 152         return newreg;
 153 }
 154
 155 static struct rc_src_register swizzle(struct rc_src_register reg,
 156                 rc_swizzle x, rc_swizzle y, rc_swizzle z, rc_swizzle w)
 157 {
 158         struct rc_src_register swizzled = reg;
 159         swizzled.Swizzle = combine_swizzles4(reg.Swizzle, x, y, z, w);
 160         return swizzled;
 161 }
 162
 163 static struct rc_src_register scalar(struct rc_src_register reg)
 164 {
 165         return swizzle(reg, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X);
 166 }
 167
 168 static void transform_ABS(struct radeon_compiler* c,
 169         struct rc_instruction* inst)
 170 {
 171         struct rc_src_register src = inst->U.I.SrcReg[0];
 172         src.Abs = 1;
 173         src.Negate = RC_MASK_NONE;
 174         emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, src);
 175         rc_remove_instruction(inst);
 176 }
 177
 178 static void transform_CEIL(struct radeon_compiler* c,
 179         struct rc_instruction* inst)
 180 {
 181         /* Assuming:
 182          *     ceil(x) = -floor(-x)
 183          *
 184          * After inlining floor:
 185          *     ceil(x) = -(-x-frac(-x))
 186          *
 187          * After simplification:
 188          *     ceil(x) = x+frac(-x)
 189          */
 190
 191         int tempreg = rc_find_free_temporary(c);
 192         emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]));
 193         emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
 194                 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg));
 195         rc_remove_instruction(inst);
 196 }
 197
 198 static void transform_DP3(struct radeon_compiler* c,
 199         struct rc_instruction* inst)
 200 {
 201         struct rc_src_register src0 = inst->U.I.SrcReg[0];
 202         struct rc_src_register src1 = inst->U.I.SrcReg[1];
 203         src0.Negate &= ~RC_MASK_W;
 204         src0.Swizzle &= ~(7 << (3 * 3));
 205         src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
 206         src1.Negate &= ~RC_MASK_W;
 207         src1.Swizzle &= ~(7 << (3 * 3));
 208         src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
 209         emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
 210         rc_remove_instruction(inst);
 211 }
 212
 213 static void transform_DPH(struct radeon_compiler* c,
 214         struct rc_instruction* inst)
 215 {
 216         struct rc_src_register src0 = inst->U.I.SrcReg[0];
 217         src0.Negate &= ~RC_MASK_W;
 218         src0.Swizzle &= ~(7 << (3 * 3));
 219         src0.Swizzle |= RC_SWIZZLE_ONE << (3 * 3);
 220         emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
 221         rc_remove_instruction(inst);
 222 }
 223
 224 /**
 225  * [1, src0.y*src1.y, src0.z, src1.w]
 226  * So basically MUL with lotsa swizzling.
 227  */
 228 static void transform_DST(struct radeon_compiler* c,
 229         struct rc_instruction* inst)
 230 {
 231         emit2(c, inst->Prev, RC_OPCODE_MUL, inst->U.I.SaturateMode, inst->U.I.DstReg,
 232                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
 233                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
 234         rc_remove_instruction(inst);
 235 }
 236
 237 static void transform_FLR(struct radeon_compiler* c,
 238         struct rc_instruction* inst)
 239 {
 240         int tempreg = rc_find_free_temporary(c);
 241         emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0]);
 242         emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
 243                 inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
 244         rc_remove_instruction(inst);
 245 }
 246
 247 /**
 248  * Definition of LIT (from ARB_fragment_program):
 249  *
 250  *  tmp = VectorLoad(op0);
 251  *  if (tmp.x < 0) tmp.x = 0;
 252  *  if (tmp.y < 0) tmp.y = 0;
 253  *  if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
 254  *  else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
 255  *  result.x = 1.0;
 256  *  result.y = tmp.x;
 257  *  result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
 258  *  result.w = 1.0;
 259  *
 260  * The longest path of computation is the one leading to result.z,
 261  * consisting of 5 operations. This implementation of LIT takes
 262  * 5 slots, if the subsequent optimization passes are clever enough
 263  * to pair instructions correctly.
 264  */
 265 static void transform_LIT(struct radeon_compiler* c,
 266         struct rc_instruction* inst)
 267 {
 268         unsigned int constant;
 269         unsigned int constant_swizzle;
 270         unsigned int temp;
 271         struct rc_src_register srctemp;
 272
 273         constant = rc_constants_add_immediate_scalar(&c->Program.Constants, -127.999999, &constant_swizzle);
 274
 275         if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
 276                 struct rc_instruction * inst_mov;
 277
 278                 inst_mov = emit1(c, inst,
 279                         RC_OPCODE_MOV, 0, inst->U.I.DstReg,
 280                         srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c)));
 281
 282                 inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
 283                 inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
 284                 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
 285         }
 286
 287         temp = inst->U.I.DstReg.Index;
 288         srctemp = srcreg(RC_FILE_TEMPORARY, temp);
 289
 290         /* tmp.x = max(0.0, Src.x); */
 291         /* tmp.y = max(0.0, Src.y); */
 292         /* tmp.w = clamp(Src.z, -128+eps, 128-eps); */
 293         emit2(c, inst->Prev, RC_OPCODE_MAX, 0,
 294                 dstregtmpmask(temp, RC_MASK_XYW),
 295                 inst->U.I.SrcReg[0],
 296                 swizzle(srcreg(RC_FILE_CONSTANT, constant),
 297                         RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, constant_swizzle&3));
 298         emit2(c, inst->Prev, RC_OPCODE_MIN, 0,
 299                 dstregtmpmask(temp, RC_MASK_Z),
 300                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 301                 negate(srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle)));
 302
 303         /* tmp.w = Pow(tmp.y, tmp.w) */
 304         emit1(c, inst->Prev, RC_OPCODE_LG2, 0,
 305                 dstregtmpmask(temp, RC_MASK_W),
 306                 swizzle(srctemp, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y));
 307         emit2(c, inst->Prev, RC_OPCODE_MUL, 0,
 308                 dstregtmpmask(temp, RC_MASK_W),
 309                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 310                 swizzle(srctemp, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z));
 311         emit1(c, inst->Prev, RC_OPCODE_EX2, 0,
 312                 dstregtmpmask(temp, RC_MASK_W),
 313                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
 314
 315         /* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */
 316         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode,
 317                 dstregtmpmask(temp, RC_MASK_Z),
 318                 negate(swizzle(srctemp, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 319                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 320                 builtin_zero);
 321
 322         /* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */
 323         emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode,
 324                 dstregtmpmask(temp, RC_MASK_XYW),
 325                 swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
 326
 327         rc_remove_instruction(inst);
 328 }
 329
 330 static void transform_LRP(struct radeon_compiler* c,
 331         struct rc_instruction* inst)
 332 {
 333         int tempreg = rc_find_free_temporary(c);
 334
 335         emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
 336                 dstreg(RC_FILE_TEMPORARY, tempreg),
 337                 inst->U.I.SrcReg[1], negate(inst->U.I.SrcReg[2]));
 338         emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
 339                 inst->U.I.DstReg,
 340                 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[2]);
 341
 342         rc_remove_instruction(inst);
 343 }
 344
 345 static void transform_POW(struct radeon_compiler* c,
 346         struct rc_instruction* inst)
 347 {
 348         int tempreg = rc_find_free_temporary(c);
 349         struct rc_dst_register tempdst = dstreg(RC_FILE_TEMPORARY, tempreg);
 350         struct rc_src_register tempsrc = srcreg(RC_FILE_TEMPORARY, tempreg);
 351         tempdst.WriteMask = RC_MASK_W;
 352         tempsrc.Swizzle = RC_SWIZZLE_WWWW;
 353
 354         emit1(c, inst->Prev, RC_OPCODE_LG2, 0, tempdst, scalar(inst->U.I.SrcReg[0]));
 355         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, tempdst, tempsrc, scalar(inst->U.I.SrcReg[1]));
 356         emit1(c, inst->Prev, RC_OPCODE_EX2, inst->U.I.SaturateMode, inst->U.I.DstReg, tempsrc);
 357
 358         rc_remove_instruction(inst);
 359 }
 360
 361 static void transform_RSQ(struct radeon_compiler* c,
 362         struct rc_instruction* inst)
 363 {
 364         inst->U.I.SrcReg[0] = absolute(inst->U.I.SrcReg[0]);
 365 }
 366
 367 static void transform_SEQ(struct radeon_compiler* c,
 368         struct rc_instruction* inst)
 369 {
 370         int tempreg = rc_find_free_temporary(c);
 371
 372         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 373         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 374                 negate(absolute(srcreg(RC_FILE_TEMPORARY, tempreg))), builtin_zero, builtin_one);
 375
 376         rc_remove_instruction(inst);
 377 }
 378
 379 static void transform_SFL(struct radeon_compiler* c,
 380         struct rc_instruction* inst)
 381 {
 382         emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, builtin_zero);
 383         rc_remove_instruction(inst);
 384 }
 385
 386 static void transform_SGE(struct radeon_compiler* c,
 387         struct rc_instruction* inst)
 388 {
 389         int tempreg = rc_find_free_temporary(c);
 390
 391         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 392         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 393                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
 394
 395         rc_remove_instruction(inst);
 396 }
 397
 398 static void transform_SGT(struct radeon_compiler* c,
 399         struct rc_instruction* inst)
 400 {
 401         int tempreg = rc_find_free_temporary(c);
 402
 403         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 404         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 405                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
 406
 407         rc_remove_instruction(inst);
 408 }
 409
 410 static void transform_SLE(struct radeon_compiler* c,
 411         struct rc_instruction* inst)
 412 {
 413         int tempreg = rc_find_free_temporary(c);
 414
 415         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 416         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 417                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
 418
 419         rc_remove_instruction(inst);
 420 }
 421
 422 static void transform_SLT(struct radeon_compiler* c,
 423         struct rc_instruction* inst)
 424 {
 425         int tempreg = rc_find_free_temporary(c);
 426
 427         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 428         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 429                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
 430
 431         rc_remove_instruction(inst);
 432 }
 433
 434 static void transform_SNE(struct radeon_compiler* c,
 435         struct rc_instruction* inst)
 436 {
 437         int tempreg = rc_find_free_temporary(c);
 438
 439         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 440         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 441                 negate(absolute(srcreg(RC_FILE_TEMPORARY, tempreg))), builtin_one, builtin_zero);
 442
 443         rc_remove_instruction(inst);
 444 }
 445
 446 static void transform_SUB(struct radeon_compiler* c,
 447         struct rc_instruction* inst)
 448 {
 449         inst->U.I.Opcode = RC_OPCODE_ADD;
 450         inst->U.I.SrcReg[1] = negate(inst->U.I.SrcReg[1]);
 451 }
 452
 453 static void transform_SWZ(struct radeon_compiler* c,
 454         struct rc_instruction* inst)
 455 {
 456         inst->U.I.Opcode = RC_OPCODE_MOV;
 457 }
 458
 459 static void transform_XPD(struct radeon_compiler* c,
 460         struct rc_instruction* inst)
 461 {
 462         int tempreg = rc_find_free_temporary(c);
 463
 464         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstreg(RC_FILE_TEMPORARY, tempreg),
 465                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
 466                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
 467         emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode, inst->U.I.DstReg,
 468                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
 469                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
 470                 negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
 471
 472         rc_remove_instruction(inst);
 473 }
 474
 475
 476 /**
 477  * Can be used as a transformation for @ref radeonClauseLocalTransform,
 478  * no userData necessary.
 479  *
 480  * Eliminates the following ALU instructions:
 481  *  ABS, CEIL, DPH, DST, FLR, LIT, LRP, POW, SEQ, SFL, SGE, SGT, SLE, SLT, SNE, SUB, SWZ, XPD
 482  * using:
 483  *  MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
 484  *
 485  * Transforms RSQ to Radeon's native RSQ by explicitly setting
 486  * absolute value.
 487  *
 488  * @note should be applicable to R300 and R500 fragment programs.
 489  */
 490 int radeonTransformALU(
 491         struct radeon_compiler * c,
 492         struct rc_instruction* inst,
 493         void* unused)
 494 {
 495         switch(inst->U.I.Opcode) {
 496         case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
 497         case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
 498         case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 499         case RC_OPCODE_DST: transform_DST(c, inst); return 1;
 500         case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 501         case RC_OPCODE_LIT: transform_LIT(c, inst); return 1;
 502         case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
 503         case RC_OPCODE_POW: transform_POW(c, inst); return 1;
 504         case RC_OPCODE_RSQ: transform_RSQ(c, inst); return 1;
 505         case RC_OPCODE_SEQ: transform_SEQ(c, inst); return 1;
 506         case RC_OPCODE_SFL: transform_SFL(c, inst); return 1;
 507         case RC_OPCODE_SGE: transform_SGE(c, inst); return 1;
 508         case RC_OPCODE_SGT: transform_SGT(c, inst); return 1;
 509         case RC_OPCODE_SLE: transform_SLE(c, inst); return 1;
 510         case RC_OPCODE_SLT: transform_SLT(c, inst); return 1;
 511         case RC_OPCODE_SNE: transform_SNE(c, inst); return 1;
 512         case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 513         case RC_OPCODE_SWZ: transform_SWZ(c, inst); return 1;
 514         case RC_OPCODE_XPD: transform_XPD(c, inst); return 1;
 515         default:
 516                 return 0;
 517         }
 518 }
 519
 520
 521 static void transform_r300_vertex_ABS(struct radeon_compiler* c,
 522         struct rc_instruction* inst)
 523 {
 524         /* Note: r500 can take absolute values, but r300 cannot. */
 525         inst->U.I.Opcode = RC_OPCODE_MAX;
 526         inst->U.I.SrcReg[1] = inst->U.I.SrcReg[0];
 527         inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
 528 }
 529
 530 static void transform_r300_vertex_CMP(struct radeon_compiler* c,
 531         struct rc_instruction* inst)
 532 {
 533         /* There is no decent CMP available, so let's rig one up.
 534          * CMP is defined as dst = src0 < 0.0 ? src1 : src2
 535          * The following sequence consumes two temps and two extra slots
 536          * (the second temp and the second slot is consumed by transform_LRP),
 537          * but should be equivalent:
 538          *
 539          * SLT tmp0, src0, 0.0
 540          * LRP dst, tmp0, src1, src2
 541          *
 542          * Yes, I know, I'm a mad scientist. ~ C. & M. */
 543         int tempreg0 = rc_find_free_temporary(c);
 544
 545         /* SLT tmp0, src0, 0.0 */
 546         emit2(c, inst->Prev, RC_OPCODE_SLT, 0,
 547                 dstreg(RC_FILE_TEMPORARY, tempreg0),
 548                 inst->U.I.SrcReg[0], builtin_zero);
 549
 550         /* LRP dst, tmp0, src1, src2 */
 551         transform_LRP(c,
 552                 emit3(c, inst->Prev, RC_OPCODE_LRP, 0,
 553                       inst->U.I.DstReg,
 554                       srcreg(RC_FILE_TEMPORARY, tempreg0), inst->U.I.SrcReg[1],  inst->U.I.SrcReg[2]));
 555
 556         rc_remove_instruction(inst);
 557 }
 558
 559 /**
 560  * For use with radeonLocalTransform, this transforms non-native ALU
 561  * instructions of the r300 up to r500 vertex engine.
 562  */
 563 int r300_transform_vertex_alu(
 564         struct radeon_compiler * c,
 565         struct rc_instruction* inst,
 566         void* unused)
 567 {
 568         switch(inst->U.I.Opcode) {
 569         case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
 570         case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
 571         case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
 572         case RC_OPCODE_DP3: transform_DP3(c, inst); return 1;
 573         case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 574         case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 575         case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
 576         case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 577         case RC_OPCODE_SWZ: transform_SWZ(c, inst); return 1;
 578         case RC_OPCODE_XPD: transform_XPD(c, inst); return 1;
 579         default:
 580                 return 0;
 581         }
 582 }
 583
 584 static void sincos_constants(struct radeon_compiler* c, unsigned int *constants)
 585 {
 586         static const float SinCosConsts[2][4] = {
 587                 {
 588                         1.273239545,            /* 4/PI */
 589                         -0.405284735,           /* -4/(PI*PI) */
 590                         3.141592654,            /* PI */
 591                         0.2225                  /* weight */
 592                 },
 593                 {
 594                         0.75,
 595                         0.5,
 596                         0.159154943,            /* 1/(2*PI) */
 597                         6.283185307             /* 2*PI */
 598                 }
 599         };
 600         int i;
 601
 602         for(i = 0; i < 2; ++i)
 603                 constants[i] = rc_constants_add_immediate_vec4(&c->Program.Constants, SinCosConsts[i]);
 604 }
 605
 606 /**
 607  * Approximate sin(x), where x is clamped to (-pi/2, pi/2).
 608  *
 609  * MUL tmp.xy, src, { 4/PI, -4/(PI^2) }
 610  * MAD tmp.x, tmp.y, |src|, tmp.x
 611  * MAD tmp.y, tmp.x, |tmp.x|, -tmp.x
 612  * MAD dest, tmp.y, weight, tmp.x
 613  */
 614 static void sin_approx(
 615         struct radeon_compiler* c, struct rc_instruction * inst,
 616         struct rc_dst_register dst, struct rc_src_register src, const unsigned int* constants)
 617 {
 618         unsigned int tempreg = rc_find_free_temporary(c);
 619
 620         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 621                 swizzle(src, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 622                 srcreg(RC_FILE_CONSTANT, constants[0]));
 623         emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_X),
 624                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 625                 absolute(swizzle(src, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 626                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
 627         emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_Y),
 628                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 629                 absolute(swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 630                 negate(swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)));
 631         emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dst,
 632                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 633                 swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 634                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
 635 }
 636
 637 /**
 638  * Translate the trigonometric functions COS, SIN, and SCS
 639  * using only the basic instructions
 640  *  MOV, ADD, MUL, MAD, FRC
 641  */
 642 int radeonTransformTrigSimple(struct radeon_compiler* c,
 643         struct rc_instruction* inst,
 644         void* unused)
 645 {
 646         if (inst->U.I.Opcode != RC_OPCODE_COS &&
 647             inst->U.I.Opcode != RC_OPCODE_SIN &&
 648             inst->U.I.Opcode != RC_OPCODE_SCS)
 649                 return 0;
 650
 651         unsigned int constants[2];
 652         unsigned int tempreg = rc_find_free_temporary(c);
 653
 654         sincos_constants(c, constants);
 655
 656         if (inst->U.I.Opcode == RC_OPCODE_COS) {
 657                 /* MAD tmp.x, src, 1/(2*PI), 0.75 */
 658                 /* FRC tmp.x, tmp.x */
 659                 /* MAD tmp.z, tmp.x, 2*PI, -PI */
 660                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 661                         swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 662                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
 663                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
 664                 emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_W),
 665                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
 666                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 667                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 668                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 669                         negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 670
 671                 sin_approx(c, inst, inst->U.I.DstReg,
 672                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 673                         constants);
 674         } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
 675                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 676                         swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 677                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
 678                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y));
 679                 emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_W),
 680                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
 681                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 682                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 683                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 684                         negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 685
 686                 sin_approx(c, inst, inst->U.I.DstReg,
 687                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 688                         constants);
 689         } else {
 690                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 691                         swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 692                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
 693                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W));
 694                 emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 695                         srcreg(RC_FILE_TEMPORARY, tempreg));
 696                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 697                         srcreg(RC_FILE_TEMPORARY, tempreg),
 698                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 699                         negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 700
 701                 struct rc_dst_register dst = inst->U.I.DstReg;
 702
 703                 dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_X;
 704                 sin_approx(c, inst, dst,
 705                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 706                         constants);
 707
 708                 dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_Y;
 709                 sin_approx(c, inst, dst,
 710                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 711                         constants);
 712         }
 713
 714         rc_remove_instruction(inst);
 715
 716         return 1;
 717 }
 718
 719
 720 /**
 721  * Transform the trigonometric functions COS, SIN, and SCS
 722  * to include pre-scaling by 1/(2*PI) and taking the fractional
 723  * part, so that the input to COS and SIN is always in the range [0,1).
 724  * SCS is replaced by one COS and one SIN instruction.
 725  *
 726  * @warning This transformation implicitly changes the semantics of SIN and COS!
 727  */
 728 int radeonTransformTrigScale(struct radeon_compiler* c,
 729         struct rc_instruction* inst,
 730         void* unused)
 731 {
 732         if (inst->U.I.Opcode != RC_OPCODE_COS &&
 733             inst->U.I.Opcode != RC_OPCODE_SIN &&
 734             inst->U.I.Opcode != RC_OPCODE_SCS)
 735                 return 0;
 736
 737         static const float RCP_2PI = 0.15915494309189535;
 738         unsigned int temp;
 739         unsigned int constant;
 740         unsigned int constant_swizzle;
 741
 742         temp = rc_find_free_temporary(c);
 743         constant = rc_constants_add_immediate_scalar(&c->Program.Constants, RCP_2PI, &constant_swizzle);
 744
 745         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstregtmpmask(temp, RC_MASK_W),
 746                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 747                 srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
 748         emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(temp, RC_MASK_W),
 749                 srcreg(RC_FILE_TEMPORARY, temp));
 750
 751         if (inst->U.I.Opcode == RC_OPCODE_COS) {
 752                 emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, inst->U.I.DstReg,
 753                         srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 754         } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
 755                 emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode,
 756                         inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 757         } else if (inst->U.I.Opcode == RC_OPCODE_SCS) {
 758                 struct rc_dst_register moddst = inst->U.I.DstReg;
 759
 760                 if (inst->U.I.DstReg.WriteMask & RC_MASK_X) {
 761                         moddst.WriteMask = RC_MASK_X;
 762                         emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, moddst,
 763                                 srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 764                 }
 765                 if (inst->U.I.DstReg.WriteMask & RC_MASK_Y) {
 766                         moddst.WriteMask = RC_MASK_Y;
 767                         emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode, moddst,
 768                                 srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 769                 }
 770         }
 771
 772         rc_remove_instruction(inst);
 773
 774         return 1;
 775 }
 776
 777 /**
 778  * Rewrite DDX/DDY instructions to properly work with r5xx shaders.
 779  * The r5xx MDH/MDV instruction provides per-quad partial derivatives.
 780  * It takes the form A*B+C. A and C are set by setting src0. B should be -1.
 781  *
 782  * @warning This explicitly changes the form of DDX and DDY!
 783  */
 784
 785 int radeonTransformDeriv(struct radeon_compiler* c,
 786         struct rc_instruction* inst,
 787         void* unused)
 788 {
 789         if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
 790                 return 0;
 791
 792         inst->U.I.SrcReg[1].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE);
 793         inst->U.I.SrcReg[1].Negate = RC_MASK_XYZW;
 794
 795         return 1;
 796 }