src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r300_context.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r300_reg.h"
  51 #include "r300_cmdbuf.h"
  52 #include "r300_emit.h"
  53 #include "radeon_bocs_wrapper.h"
  54 #include "radeon_mipmap_tree.h"
  55 #include "r300_state.h"
  56 #include "radeon_reg.h"
  57
  58 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
  59 #   define RADEON_ONE_REG_WR        (1 << 15)
  60
  61 /** # of dwords reserved for additional instructions that may need to be written
  62  * during flushing.
  63  */
  64 #define SPACE_FOR_FLUSHING      4
  65
  66 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  67 {
  68     if (r300->radeon.radeonScreen->kernel_mm) {
  69         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  70     } else {
  71         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  72         return t->packet0.count;
  73     }
  74     return 0;
  75 }
  76
  77 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  78 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  79
  80 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
  81 {
  82         r300ContextPtr r300 = R300_CONTEXT(ctx);
  83         BATCH_LOCALS(&r300->radeon);
  84         drm_r300_cmd_header_t cmd;
  85         uint32_t addr, ndw, i;
  86
  87         if (!r300->radeon.radeonScreen->kernel_mm) {
  88                 uint32_t dwords;
  89                 dwords = (*atom->check) (ctx, atom);
  90                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
  91                 OUT_BATCH_TABLE(atom->cmd, dwords);
  92                 END_BATCH();
  93                 return;
  94         }
  95
  96         cmd.u = atom->cmd[0];
  97         addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
  98         ndw = cmd.vpu.count * 4;
  99         if (ndw) {
 100
 101                 if (r300->vap_flush_needed) {
 102                         BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
 103
 104                         /* flush processing vertices */
 105                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
 106                         OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 107                         OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 108                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
 109                         OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 110                         r300->vap_flush_needed = GL_FALSE;
 111                 } else {
 112                         BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
 113                 }
 114                 OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
 115                 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 116                 for (i = 0; i < ndw; i++) {
 117                         OUT_BATCH(atom->cmd[i+1]);
 118                 }
 119                 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 120                 END_BATCH();
 121         }
 122 }
 123
 124 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 125 {
 126         r300ContextPtr r300 = R300_CONTEXT(ctx);
 127         BATCH_LOCALS(&r300->radeon);
 128         drm_r300_cmd_header_t cmd;
 129         uint32_t addr, ndw, i, sz;
 130         int type, clamp, stride;
 131
 132         if (!r300->radeon.radeonScreen->kernel_mm) {
 133                 uint32_t dwords;
 134                 dwords = (*atom->check) (ctx, atom);
 135                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
 136                 OUT_BATCH_TABLE(atom->cmd, dwords);
 137                 END_BATCH();
 138                 return;
 139         }
 140
 141         cmd.u = atom->cmd[0];
 142         sz = cmd.r500fp.count;
 143         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 144         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 145         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 146
 147         addr |= (type << 16);
 148         addr |= (clamp << 17);
 149
 150         stride = type ? 4 : 6;
 151
 152         ndw = sz * stride;
 153         if (ndw) {
 154
 155                 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
 156                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 157                 OUT_BATCH(addr);
 158                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 159                 for (i = 0; i < ndw; i++) {
 160                         OUT_BATCH(atom->cmd[i+1]);
 161                 }
 162                 END_BATCH();
 163         }
 164 }
 165
 166 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 167 {
 168         r300ContextPtr r300 = R300_CONTEXT(ctx);
 169         BATCH_LOCALS(&r300->radeon);
 170         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 171         int notexture = 0;
 172
 173         if (numtmus) {
 174                 int i;
 175
 176                 for(i = 0; i < numtmus; ++i) {
 177                     radeonTexObj *t = r300->hw.textures[i];
 178
 179                     if (!t)
 180                         notexture = 1;
 181                 }
 182
 183                 if (r300->radeon.radeonScreen->kernel_mm && notexture) {
 184                         return;
 185                 }
 186                 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
 187                 for(i = 0; i < numtmus; ++i) {
 188                     radeonTexObj *t = r300->hw.textures[i];
 189                     OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 190                     if (t && !t->image_override) {
 191                             OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 192                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 193                     } else if (!t) {
 194                             OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 195                     } else { /* override cases */
 196                             if (t->bo) {
 197                                     OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 198                                                     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 199                             } else if (!r300->radeon.radeonScreen->kernel_mm) {
 200                                     OUT_BATCH(t->override_offset);
 201                             }
 202                             else
 203                                 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 204                     }
 205                 }
 206                 END_BATCH();
 207         }
 208 }
 209
 210 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 211 {
 212         r300ContextPtr r300 = R300_CONTEXT(ctx);
 213         BATCH_LOCALS(&r300->radeon);
 214         struct radeon_renderbuffer *rrb;
 215         uint32_t cbpitch;
 216         uint32_t offset = r300->radeon.state.color.draw_offset;
 217         uint32_t dw = 6;
 218     int i;
 219
 220         rrb = radeon_get_colorbuffer(&r300->radeon);
 221         if (!rrb || !rrb->bo) {
 222                 fprintf(stderr, "no rrb\n");
 223                 return;
 224         }
 225
 226         cbpitch = (rrb->pitch / rrb->cpp);
 227         if (rrb->cpp == 4)
 228                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 229         else
 230                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 231
 232         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 233                 cbpitch |= R300_COLOR_TILE_ENABLE;
 234
 235         if (r300->radeon.radeonScreen->kernel_mm)
 236                 dw += 2;
 237         BEGIN_BATCH_NO_AUTOSTATE(dw);
 238         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 239         OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 240         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 241         if (!r300->radeon.radeonScreen->kernel_mm)
 242                 OUT_BATCH(cbpitch);
 243         else
 244                 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 245         END_BATCH();
 246     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 247         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 248             BEGIN_BATCH_NO_AUTOSTATE(3);
 249             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 250             OUT_BATCH(0);
 251             OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) |
 252                     ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT));
 253             END_BATCH();
 254             BEGIN_BATCH_NO_AUTOSTATE(16);
 255             for (i = 0; i < 4; i++) {
 256                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 257                 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 258                 OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
 259             }
 260             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 261             OUT_BATCH(0xAAAA);
 262             OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 263             OUT_BATCH(0xffffff);
 264             END_BATCH();
 265         } else {
 266             BEGIN_BATCH_NO_AUTOSTATE(3);
 267             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 268             OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 269                     (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 270             OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 271                     ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 272             END_BATCH();
 273             BEGIN_BATCH_NO_AUTOSTATE(16);
 274             for (i = 0; i < 4; i++) {
 275                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 276                 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 277                 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) |
 278                           ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
 279             }
 280             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 281             OUT_BATCH(0xAAAA);
 282             OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 283             OUT_BATCH(0xffffff);
 284             END_BATCH();
 285         }
 286     }
 287 }
 288
 289 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 290 {
 291         r300ContextPtr r300 = R300_CONTEXT(ctx);
 292         BATCH_LOCALS(&r300->radeon);
 293         struct radeon_renderbuffer *rrb;
 294         uint32_t zbpitch;
 295
 296         rrb = radeon_get_depthbuffer(&r300->radeon);
 297         if (!rrb)
 298                 return;
 299
 300         zbpitch = (rrb->pitch / rrb->cpp);
 301         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 302                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 303         }
 304         if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 305                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 306         }
 307
 308         BEGIN_BATCH_NO_AUTOSTATE(6);
 309         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 310         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 311         OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
 312         END_BATCH();
 313 }
 314
 315 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 316 {
 317         r300ContextPtr r300 = R300_CONTEXT(ctx);
 318         BATCH_LOCALS(&r300->radeon);
 319         struct radeon_renderbuffer *rrb;
 320         uint32_t format = 0;
 321
 322         rrb = radeon_get_depthbuffer(&r300->radeon);
 323         if (!rrb)
 324           format = 0;
 325         else {
 326           if (rrb->cpp == 2)
 327             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 328           else if (rrb->cpp == 4)
 329             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 330         }
 331
 332         OUT_BATCH(atom->cmd[0]);
 333         atom->cmd[1] &= ~0xf;
 334         atom->cmd[1] |= format;
 335         OUT_BATCH(atom->cmd[1]);
 336         OUT_BATCH(atom->cmd[2]);
 337         OUT_BATCH(atom->cmd[3]);
 338         OUT_BATCH(atom->cmd[4]);
 339 }
 340
 341 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 342 {
 343         return atom->cmd_size;
 344 }
 345
 346 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 347 {
 348         r300ContextPtr r300 = R300_CONTEXT(ctx);
 349         int cnt;
 350         if (atom->cmd[0] == CP_PACKET2) {
 351                 return 0;
 352         }
 353         cnt = packet0_count(r300, atom->cmd);
 354         return cnt ? cnt + 1 : 0;
 355 }
 356
 357 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 358 {
 359         int cnt;
 360
 361         cnt = vpu_count(atom->cmd);
 362         return cnt ? (cnt * 4) + 1 : 0;
 363 }
 364
 365 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 366 {
 367         int cnt;
 368
 369         cnt = r500fp_count(atom->cmd);
 370         return cnt ? (cnt * 6) + 1 : 0;
 371 }
 372
 373 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 374 {
 375         int cnt;
 376
 377         cnt = r500fp_count(atom->cmd);
 378         return cnt ? (cnt * 4) + 1 : 0;
 379 }
 380
 381 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 382    do {                                                                 \
 383       r300->hw.ATOM.cmd_size = (SZ);                                    \
 384       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 385       r300->hw.ATOM.name = #ATOM;                                       \
 386       r300->hw.ATOM.idx = (IDX);                                        \
 387       r300->hw.ATOM.check = check_##CHK;                                \
 388       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 389       r300->radeon.hw.max_state_size += (SZ);                                   \
 390       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 391    } while (0)
 392 /**
 393  * Allocate memory for the command buffer and initialize the state atom
 394  * list. Note that the initial hardware state is set by r300InitState().
 395  */
 396 void r300InitCmdBuf(r300ContextPtr r300)
 397 {
 398         int mtu;
 399         int has_tcl = 1;
 400         int is_r500 = 0;
 401         int i;
 402
 403         if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
 404                 has_tcl = 0;
 405
 406         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 407                 is_r500 = 1;
 408
 409         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 410
 411         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 412         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 413                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 414         }
 415
 416         /* Setup the atom linked list */
 417         make_empty_list(&r300->radeon.hw.atomlist);
 418         r300->radeon.hw.atomlist.name = "atom-list";
 419
 420         /* Initialize state atoms */
 421         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 422         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 423         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 424         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 425         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 426         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 427         if (is_r500) {
 428             ALLOC_STATE(vap_index_offset, always, 2, 0);
 429             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 430             r300->hw.vap_index_offset.cmd[1] = 0;
 431         }
 432         ALLOC_STATE(vte, always, 3, 0);
 433         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 434         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 435         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 436         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 437         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 438         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 439         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 440             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 441         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 442         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 443             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 444         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 445         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 446         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 447         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 448
 449         if (has_tcl) {
 450                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 451                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 452                 ALLOC_STATE(vap_clip, always, 5, 0);
 453                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 454                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 455                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 456         }
 457
 458         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 459         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 460             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 461
 462         if (has_tcl) {
 463                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 464                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 465                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 466         }
 467
 468         ALLOC_STATE(gb_enable, always, 2, 0);
 469         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 470         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 471         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
 472         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 473         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 474         ALLOC_STATE(ga_point_s0, always, 5, 0);
 475         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 476         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 477         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 478         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 479         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 480         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 481         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 482         ALLOC_STATE(lcntl, always, 2, 0);
 483         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 484         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 485         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 486         ALLOC_STATE(shade, always, 5, 0);
 487         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
 488         ALLOC_STATE(polygon_mode, always, 4, 0);
 489         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 490         ALLOC_STATE(fogp, always, 3, 0);
 491         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 492         ALLOC_STATE(zbias_cntl, always, 2, 0);
 493         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 494         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 495         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 496             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 497         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 498         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 499         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 500         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 501         ALLOC_STATE(su_depth_scale, always, 3, 0);
 502         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 503         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 504         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 505         if (is_r500) {
 506                 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
 507                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 508                 for (i = 0; i < 8; i++) {
 509                         r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
 510                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 511                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 512                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 513                           (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
 514                 }
 515                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 516                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 517         } else {
 518                 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 519                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 520                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 521                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 522         }
 523         ALLOC_STATE(sc_hyperz, always, 3, 0);
 524         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 525         ALLOC_STATE(sc_screendoor, always, 2, 0);
 526         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 527         ALLOC_STATE(us_out_fmt, always, 6, 0);
 528         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 529
 530         if (is_r500) {
 531                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 532                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 533                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 534                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 535                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 536                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 537
 538                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 539                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 540                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 541                 r300->hw.r500fp.emit = emit_r500fp;
 542                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 543                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 544                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 545                 r300->hw.r500fp_const.emit = emit_r500fp;
 546         } else {
 547                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 548                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 549                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 550
 551                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 552                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 553
 554                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 555                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 556                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 557                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 558                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 559                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 560                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 561                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 562                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 563                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 564         }
 565         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 566         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 567         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 568         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 569         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 570         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 571         ALLOC_STATE(fg_depth_src, always, 2, 0);
 572         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 573         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 574         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 575         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 576         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 577         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 578         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 579         if (is_r500) {
 580                 ALLOC_STATE(blend_color, always, 3, 0);
 581                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 582         } else {
 583                 ALLOC_STATE(blend_color, always, 2, 0);
 584                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 585         }
 586         ALLOC_STATE(rop, always, 2, 0);
 587         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 588         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 589         r300->hw.cb.emit = &emit_cb_offset;
 590         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 591         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 592         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 593         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 594         ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 595         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 596         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 597         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 598             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 599
 600         ALLOC_STATE(zstencil_format, always, 5, 0);
 601         r300->hw.zstencil_format.cmd[0] =
 602             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 603         r300->hw.zstencil_format.emit = emit_zstencil_format;
 604
 605         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 606         r300->hw.zb.emit = emit_zb_offset;
 607         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 608         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 609         ALLOC_STATE(unk4F30, always, 3, 0);
 610         r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
 611         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 612         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 613         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 614         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 615
 616         /* VPU only on TCL */
 617         if (has_tcl) {
 618                 int i;
 619                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 620                 r300->hw.vpi.cmd[0] =
 621                     cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 622                 r300->hw.vpi.emit = emit_vpu;
 623
 624                 if (is_r500) {
 625                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 626                     r300->hw.vpp.cmd[0] =
 627                         cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 628                     r300->hw.vpp.emit = emit_vpu;
 629
 630                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 631                     r300->hw.vps.cmd[0] =
 632                         cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 633                     r300->hw.vps.emit = emit_vpu;
 634
 635                         for (i = 0; i < 6; i++) {
 636                           ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 637                           r300->hw.vpucp[i].cmd[0] =
 638                                   cmdvpu(r300->radeon.radeonScreen,
 639                            R500_PVS_UCP_START + i, 1);
 640                                 r300->hw.vpucp[i].emit = emit_vpu;
 641                         }
 642                 } else {
 643                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 644                     r300->hw.vpp.cmd[0] =
 645                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 646                     r300->hw.vpp.emit = emit_vpu;
 647
 648                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 649                     r300->hw.vps.cmd[0] =
 650                         cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 651                     r300->hw.vps.emit = emit_vpu;
 652
 653                         for (i = 0; i < 6; i++) {
 654                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 655                                 r300->hw.vpucp[i].cmd[0] =
 656                                         cmdvpu(r300->radeon.radeonScreen,
 657                                                R300_PVS_UCP_START + i, 1);
 658                                 r300->hw.vpucp[i].emit = emit_vpu;
 659                         }
 660                 }
 661         }
 662
 663         /* Textures */
 664         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 665         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 666             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 667
 668         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 669         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 670             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 671
 672         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 673         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 674
 675         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 676         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 677             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 678
 679         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 680         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 681
 682         ALLOC_STATE(tex.offset, variable, 1, 0);
 683         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 684             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 685         r300->hw.tex.offset.emit = &emit_tex_offsets;
 686
 687         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 688         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 689             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 690
 691         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 692         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 693             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 694
 695         r300->radeon.hw.is_dirty = GL_TRUE;
 696         r300->radeon.hw.all_dirty = GL_TRUE;
 697
 698         rcommonInitCmdBuf(&r300->radeon);
 699 }