src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r300_context.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r300_reg.h"
  51 #include "r300_cmdbuf.h"
  52 #include "r300_emit.h"
  53 #include "radeon_bocs_wrapper.h"
  54 #include "radeon_mipmap_tree.h"
  55 #include "r300_state.h"
  56 #include "radeon_reg.h"
  57
  58 /** # of dwords reserved for additional instructions that may need to be written
  59  * during flushing.
  60  */
  61 #define SPACE_FOR_FLUSHING      4
  62
  63 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  64 {
  65     if (r300->radeon.radeonScreen->kernel_mm) {
  66         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  67     } else {
  68         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  69         return t->packet0.count;
  70     }
  71 }
  72
  73 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  74 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  75
  76 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
  77 {
  78         r300ContextPtr r300 = R300_CONTEXT(ctx);
  79         BATCH_LOCALS(&r300->radeon);
  80         drm_r300_cmd_header_t cmd;
  81         uint32_t addr, ndw, i;
  82
  83         if (!r300->radeon.radeonScreen->kernel_mm) {
  84                 uint32_t dwords;
  85                 dwords = (*atom->check) (ctx, atom);
  86                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
  87                 OUT_BATCH_TABLE(atom->cmd, dwords);
  88                 END_BATCH();
  89                 return;
  90         }
  91
  92         cmd.u = atom->cmd[0];
  93         addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
  94         ndw = cmd.vpu.count * 4;
  95         if (ndw) {
  96
  97                 if (r300->vap_flush_needed) {
  98                         BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
  99
 100                         /* flush processing vertices */
 101                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
 102                         OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 103                         OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 104                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
 105                         OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 106                         r300->vap_flush_needed = GL_FALSE;
 107                 } else {
 108                         BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
 109                 }
 110                 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
 111                 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 112                 for (i = 0; i < ndw; i++) {
 113                         OUT_BATCH(atom->cmd[i+1]);
 114                 }
 115                 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 116                 END_BATCH();
 117         }
 118 }
 119
 120 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 121 {
 122         r300ContextPtr r300 = R300_CONTEXT(ctx);
 123         BATCH_LOCALS(&r300->radeon);
 124         drm_r300_cmd_header_t cmd;
 125         uint32_t addr, ndw, i, sz;
 126         int type, clamp, stride;
 127
 128         if (!r300->radeon.radeonScreen->kernel_mm) {
 129                 uint32_t dwords;
 130                 dwords = (*atom->check) (ctx, atom);
 131                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
 132                 OUT_BATCH_TABLE(atom->cmd, dwords);
 133                 END_BATCH();
 134                 return;
 135         }
 136
 137         cmd.u = atom->cmd[0];
 138         sz = cmd.r500fp.count;
 139         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 140         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 141         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 142
 143         addr |= (type << 16);
 144         addr |= (clamp << 17);
 145
 146         stride = type ? 4 : 6;
 147
 148         ndw = sz * stride;
 149         if (ndw) {
 150
 151                 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
 152                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 153                 OUT_BATCH(addr);
 154                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 155                 for (i = 0; i < ndw; i++) {
 156                         OUT_BATCH(atom->cmd[i+1]);
 157                 }
 158                 END_BATCH();
 159         }
 160 }
 161
 162 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 163 {
 164         r300ContextPtr r300 = R300_CONTEXT(ctx);
 165         BATCH_LOCALS(&r300->radeon);
 166         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 167         int notexture = 0;
 168
 169         if (numtmus) {
 170                 int i;
 171
 172                 for(i = 0; i < numtmus; ++i) {
 173                     radeonTexObj *t = r300->hw.textures[i];
 174
 175                     if (!t)
 176                         notexture = 1;
 177                 }
 178
 179                 if (r300->radeon.radeonScreen->kernel_mm && notexture) {
 180                         return;
 181                 }
 182                 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
 183                 for(i = 0; i < numtmus; ++i) {
 184                     radeonTexObj *t = r300->hw.textures[i];
 185                     OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 186                     if (t && !t->image_override) {
 187                             OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 188                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 189                     } else if (!t) {
 190                             OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 191                     } else { /* override cases */
 192                             if (t->bo) {
 193                                     OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 194                                                     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 195                             } else if (!r300->radeon.radeonScreen->kernel_mm) {
 196                                     OUT_BATCH(t->override_offset);
 197                             }
 198                             else
 199                                 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 200                     }
 201                 }
 202                 END_BATCH();
 203         }
 204 }
 205
 206 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 207 {
 208         r300ContextPtr r300 = R300_CONTEXT(ctx);
 209         BATCH_LOCALS(&r300->radeon);
 210         struct radeon_renderbuffer *rrb;
 211         uint32_t cbpitch;
 212         uint32_t offset = r300->radeon.state.color.draw_offset;
 213         uint32_t dw = 6;
 214     int i;
 215
 216         rrb = radeon_get_colorbuffer(&r300->radeon);
 217         if (!rrb || !rrb->bo) {
 218                 fprintf(stderr, "no rrb\n");
 219                 return;
 220         }
 221
 222         cbpitch = (rrb->pitch / rrb->cpp);
 223         if (rrb->cpp == 4)
 224                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 225         else
 226                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 227
 228         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 229                 cbpitch |= R300_COLOR_TILE_ENABLE;
 230
 231         if (r300->radeon.radeonScreen->kernel_mm)
 232                 dw += 2;
 233         BEGIN_BATCH_NO_AUTOSTATE(dw);
 234         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 235         OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 236         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 237         if (!r300->radeon.radeonScreen->kernel_mm)
 238                 OUT_BATCH(cbpitch);
 239         else
 240                 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 241         END_BATCH();
 242     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 243         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 244             BEGIN_BATCH_NO_AUTOSTATE(3);
 245             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 246             OUT_BATCH(0);
 247             OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) |
 248                     ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT));
 249             END_BATCH();
 250             BEGIN_BATCH_NO_AUTOSTATE(16);
 251             for (i = 0; i < 4; i++) {
 252                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 253                 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 254                 OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
 255             }
 256             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 257             OUT_BATCH(0xAAAA);
 258             OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 259             OUT_BATCH(0xffffff);
 260             END_BATCH();
 261         } else {
 262             BEGIN_BATCH_NO_AUTOSTATE(3);
 263             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 264             OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 265                     (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 266             OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 267                     ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 268             END_BATCH();
 269             BEGIN_BATCH_NO_AUTOSTATE(16);
 270             for (i = 0; i < 4; i++) {
 271                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 272                 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 273                 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) |
 274                           ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
 275             }
 276             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 277             OUT_BATCH(0xAAAA);
 278             OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 279             OUT_BATCH(0xffffff);
 280             END_BATCH();
 281         }
 282     }
 283 }
 284
 285 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 286 {
 287         r300ContextPtr r300 = R300_CONTEXT(ctx);
 288         BATCH_LOCALS(&r300->radeon);
 289         struct radeon_renderbuffer *rrb;
 290         uint32_t zbpitch;
 291
 292         rrb = radeon_get_depthbuffer(&r300->radeon);
 293         if (!rrb)
 294                 return;
 295
 296         zbpitch = (rrb->pitch / rrb->cpp);
 297         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 298                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 299         }
 300         if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 301                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 302         }
 303
 304         BEGIN_BATCH_NO_AUTOSTATE(6);
 305         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 306         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 307         OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
 308         END_BATCH();
 309 }
 310
 311 static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom)
 312 {
 313         r300ContextPtr r300 = R300_CONTEXT(ctx);
 314         BATCH_LOCALS(&r300->radeon);
 315     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 316         BEGIN_BATCH_NO_AUTOSTATE(4);
 317         OUT_BATCH(atom->cmd[0]);
 318         OUT_BATCH(atom->cmd[1]);
 319         OUT_BATCH(atom->cmd[2]);
 320         OUT_BATCH(atom->cmd[3]);
 321         END_BATCH();
 322     }
 323 }
 324
 325 static void emit_threshold_misc(GLcontext *ctx, struct radeon_state_atom * atom)
 326 {
 327         r300ContextPtr r300 = R300_CONTEXT(ctx);
 328         BATCH_LOCALS(&r300->radeon);
 329     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 330         BEGIN_BATCH_NO_AUTOSTATE(3);
 331         OUT_BATCH(atom->cmd[0]);
 332         OUT_BATCH(atom->cmd[1]);
 333         OUT_BATCH(atom->cmd[2]);
 334         END_BATCH();
 335     }
 336 }
 337
 338 static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom)
 339 {
 340         r300ContextPtr r300 = R300_CONTEXT(ctx);
 341         BATCH_LOCALS(&r300->radeon);
 342
 343     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 344         BEGIN_BATCH_NO_AUTOSTATE(2);
 345         OUT_BATCH(atom->cmd[0]);
 346         OUT_BATCH(atom->cmd[1]);
 347         END_BATCH();
 348     }
 349 }
 350
 351 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 352 {
 353         r300ContextPtr r300 = R300_CONTEXT(ctx);
 354         BATCH_LOCALS(&r300->radeon);
 355         struct radeon_renderbuffer *rrb;
 356         uint32_t format = 0;
 357
 358         rrb = radeon_get_depthbuffer(&r300->radeon);
 359         if (!rrb)
 360           format = 0;
 361         else {
 362           if (rrb->cpp == 2)
 363             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 364           else if (rrb->cpp == 4)
 365             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 366         }
 367
 368         OUT_BATCH(atom->cmd[0]);
 369         atom->cmd[1] &= ~0xf;
 370         atom->cmd[1] |= format;
 371         OUT_BATCH(atom->cmd[1]);
 372         OUT_BATCH(atom->cmd[2]);
 373         OUT_BATCH(atom->cmd[3]);
 374         OUT_BATCH(atom->cmd[4]);
 375 }
 376
 377 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 378 {
 379         return atom->cmd_size;
 380 }
 381
 382 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 383 {
 384         r300ContextPtr r300 = R300_CONTEXT(ctx);
 385         int cnt;
 386         if (atom->cmd[0] == CP_PACKET2) {
 387                 return 0;
 388         }
 389         cnt = packet0_count(r300, atom->cmd);
 390         return cnt ? cnt + 1 : 0;
 391 }
 392
 393 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 394 {
 395         int cnt;
 396
 397         cnt = vpu_count(atom->cmd);
 398         return cnt ? (cnt * 4) + 1 : 0;
 399 }
 400
 401 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 402 {
 403         int cnt;
 404
 405         cnt = r500fp_count(atom->cmd);
 406         return cnt ? (cnt * 6) + 1 : 0;
 407 }
 408
 409 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 410 {
 411         int cnt;
 412
 413         cnt = r500fp_count(atom->cmd);
 414         return cnt ? (cnt * 4) + 1 : 0;
 415 }
 416
 417 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 418    do {                                                                 \
 419       r300->hw.ATOM.cmd_size = (SZ);                                    \
 420       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 421       r300->hw.ATOM.name = #ATOM;                                       \
 422       r300->hw.ATOM.idx = (IDX);                                        \
 423       r300->hw.ATOM.check = check_##CHK;                                \
 424       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 425       r300->radeon.hw.max_state_size += (SZ);                                   \
 426       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 427    } while (0)
 428 /**
 429  * Allocate memory for the command buffer and initialize the state atom
 430  * list. Note that the initial hardware state is set by r300InitState().
 431  */
 432 void r300InitCmdBuf(r300ContextPtr r300)
 433 {
 434         int mtu;
 435         int has_tcl;
 436         int is_r500 = 0;
 437         int i;
 438
 439         has_tcl = r300->options.hw_tcl_enabled;
 440
 441         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 442                 is_r500 = 1;
 443
 444         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 445
 446         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 447         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 448                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 449         }
 450
 451         /* Setup the atom linked list */
 452         make_empty_list(&r300->radeon.hw.atomlist);
 453         r300->radeon.hw.atomlist.name = "atom-list";
 454
 455         /* Initialize state atoms */
 456         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 457         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 458         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 459         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 460         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 461         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 462         if (is_r500) {
 463             ALLOC_STATE(vap_index_offset, always, 2, 0);
 464             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 465             r300->hw.vap_index_offset.cmd[1] = 0;
 466         }
 467         ALLOC_STATE(vte, always, 3, 0);
 468         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 469         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 470         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 471         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 472         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 473         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 474         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 475             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 476         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 477         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 478             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 479         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 480         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 481         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 482         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 483
 484         if (has_tcl) {
 485                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 486                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 487                 ALLOC_STATE(vap_clip, always, 5, 0);
 488                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 489                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 490                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 491         }
 492
 493         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 494         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 495             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 496
 497         if (has_tcl) {
 498                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 499                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 500                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 501         }
 502
 503         ALLOC_STATE(gb_enable, always, 2, 0);
 504         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 505         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 506         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
 507         r300->hw.gb_misc.emit = emit_gb_misc;
 508         ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
 509     r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
 510         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 511         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 512         ALLOC_STATE(ga_point_s0, always, 5, 0);
 513         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 514         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 515         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 516         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 517         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 518         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 519         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 520         ALLOC_STATE(lcntl, always, 2, 0);
 521         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 522         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 523         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 524         ALLOC_STATE(shade, always, 2, 0);
 525         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
 526         r300->hw.shade.emit = emit_shade_misc;
 527         ALLOC_STATE(shade2, always, 4, 0);
 528         r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
 529         ALLOC_STATE(polygon_mode, always, 4, 0);
 530         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 531         ALLOC_STATE(fogp, always, 3, 0);
 532         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 533         ALLOC_STATE(zbias_cntl, always, 2, 0);
 534         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 535         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 536         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 537             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 538         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 539         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 540         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 541         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 542         ALLOC_STATE(su_depth_scale, always, 3, 0);
 543         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 544         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 545         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 546         if (is_r500) {
 547                 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
 548                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 549                 for (i = 0; i < 8; i++) {
 550                         r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
 551                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 552                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 553                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 554                           (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
 555                 }
 556                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 557                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 558         } else {
 559                 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 560                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 561                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 562                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 563         }
 564         ALLOC_STATE(sc_hyperz, always, 3, 0);
 565         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 566         ALLOC_STATE(sc_screendoor, always, 2, 0);
 567         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 568         ALLOC_STATE(us_out_fmt, always, 6, 0);
 569         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 570
 571         if (is_r500) {
 572                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 573                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 574                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 575                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 576                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 577                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 578
 579                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 580                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 581                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 582                 r300->hw.r500fp.emit = emit_r500fp;
 583                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 584                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 585                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 586                 r300->hw.r500fp_const.emit = emit_r500fp;
 587         } else {
 588                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 589                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 590                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 591
 592                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 593                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 594
 595                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 596                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 597                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 598                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 599                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 600                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 601                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 602                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 603                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 604                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 605         }
 606         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 607         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 608         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 609         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 610         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 611         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 612         ALLOC_STATE(fg_depth_src, always, 2, 0);
 613         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 614         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 615         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 616         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 617         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 618         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 619         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 620         if (is_r500) {
 621                 ALLOC_STATE(blend_color, always, 3, 0);
 622                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 623         } else {
 624                 ALLOC_STATE(blend_color, always, 2, 0);
 625                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 626         }
 627         ALLOC_STATE(rop, always, 2, 0);
 628         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 629         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 630         r300->hw.cb.emit = &emit_cb_offset;
 631         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 632         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 633         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 634         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 635     ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 636     r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 637         r300->hw.rb3d_discard_src_pixel_lte_threshold.emit = emit_threshold_misc;
 638         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 639         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 640             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 641
 642         ALLOC_STATE(zstencil_format, always, 5, 0);
 643         r300->hw.zstencil_format.cmd[0] =
 644             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 645         r300->hw.zstencil_format.emit = emit_zstencil_format;
 646
 647         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 648         r300->hw.zb.emit = emit_zb_offset;
 649         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 650         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 651         ALLOC_STATE(zb_zmask, always, 3, 0);
 652         r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
 653         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 654         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 655         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 656         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 657
 658         /* VPU only on TCL */
 659         if (has_tcl) {
 660                 int i;
 661                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 662                 r300->hw.vpi.cmd[0] =
 663                     cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 664                 r300->hw.vpi.emit = emit_vpu;
 665
 666                 if (is_r500) {
 667                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 668                     r300->hw.vpp.cmd[0] =
 669                         cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 670                     r300->hw.vpp.emit = emit_vpu;
 671
 672                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 673                     r300->hw.vps.cmd[0] =
 674                         cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 675                     r300->hw.vps.emit = emit_vpu;
 676
 677                         for (i = 0; i < 6; i++) {
 678                           ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 679                           r300->hw.vpucp[i].cmd[0] =
 680                                   cmdvpu(r300->radeon.radeonScreen,
 681                            R500_PVS_UCP_START + i, 1);
 682                                 r300->hw.vpucp[i].emit = emit_vpu;
 683                         }
 684                 } else {
 685                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 686                     r300->hw.vpp.cmd[0] =
 687                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 688                     r300->hw.vpp.emit = emit_vpu;
 689
 690                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 691                     r300->hw.vps.cmd[0] =
 692                         cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 693                     r300->hw.vps.emit = emit_vpu;
 694
 695                         for (i = 0; i < 6; i++) {
 696                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 697                                 r300->hw.vpucp[i].cmd[0] =
 698                                         cmdvpu(r300->radeon.radeonScreen,
 699                                                R300_PVS_UCP_START + i, 1);
 700                                 r300->hw.vpucp[i].emit = emit_vpu;
 701                         }
 702                 }
 703         }
 704
 705         /* Textures */
 706         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 707         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 708             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 709
 710         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 711         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 712             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 713
 714         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 715         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 716
 717         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 718         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 719             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 720
 721         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 722         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 723
 724         ALLOC_STATE(tex.offset, variable, 1, 0);
 725         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 726             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 727         r300->hw.tex.offset.emit = &emit_tex_offsets;
 728
 729         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 730         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 731             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 732
 733         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 734         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 735             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 736
 737         r300->radeon.hw.is_dirty = GL_TRUE;
 738         r300->radeon.hw.all_dirty = GL_TRUE;
 739
 740         rcommonInitCmdBuf(&r300->radeon);
 741 }