2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Nicolai Haehnle <prefect_@gmx.net>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/extensions.h"
44 #include "main/bufferobj.h"
45 #include "main/texobj.h"
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
52 #include "tnl/t_pipeline.h"
54 #include "drivers/common/driverfuncs.h"
56 #include "r300_context.h"
57 #include "radeon_span.h"
58 #include "r300_cmdbuf.h"
59 #include "r300_state.h"
60 #include "r300_ioctl.h"
62 #include "r300_emit.h"
63 #include "r300_swtcl.h"
64 #include "radeon_bocs_wrapper.h"
65 #include "radeon_buffer_objects.h"
66 #include "radeon_queryobj.h"
69 #include "xmlpool.h" /* for symbolic values of enum-type options */
71 #define need_GL_VERSION_2_0
72 #define need_GL_ARB_occlusion_query
73 #define need_GL_ARB_point_parameters
74 #define need_GL_ARB_vertex_program
75 #define need_GL_EXT_blend_equation_separate
76 #define need_GL_EXT_blend_func_separate
77 #define need_GL_EXT_blend_minmax
78 #define need_GL_EXT_framebuffer_blit
79 #define need_GL_EXT_framebuffer_object
80 #define need_GL_EXT_fog_coord
81 #define need_GL_EXT_gpu_program_parameters
82 #define need_GL_EXT_provoking_vertex
83 #define need_GL_EXT_secondary_color
84 #define need_GL_EXT_stencil_two_side
85 #define need_GL_ATI_separate_stencil
86 #define need_GL_NV_vertex_program
88 #include "main/remap_helper.h"
91 static const struct dri_extension card_extensions
[] = {
93 {"GL_ARB_depth_texture", NULL
},
94 {"GL_ARB_fragment_program", NULL
},
95 {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions
},
96 {"GL_ARB_multitexture", NULL
},
97 {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions
},
98 {"GL_ARB_shadow", NULL
},
99 {"GL_ARB_shadow_ambient", NULL
},
100 {"GL_ARB_texture_border_clamp", NULL
},
101 {"GL_ARB_texture_cube_map", NULL
},
102 {"GL_ARB_texture_env_add", NULL
},
103 {"GL_ARB_texture_env_combine", NULL
},
104 {"GL_ARB_texture_env_crossbar", NULL
},
105 {"GL_ARB_texture_env_dot3", NULL
},
106 {"GL_ARB_texture_mirrored_repeat", NULL
},
107 {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions
},
108 {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions
},
109 {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions
},
110 {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions
},
111 {"GL_EXT_blend_subtract", NULL
},
112 {"GL_EXT_packed_depth_stencil", NULL
},
113 {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions
},
114 {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions
},
115 {"GL_EXT_provoking_vertex", GL_EXT_provoking_vertex_functions
},
116 {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions
},
117 {"GL_EXT_shadow_funcs", NULL
},
118 {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions
},
119 {"GL_EXT_stencil_wrap", NULL
},
120 {"GL_EXT_texture_edge_clamp", NULL
},
121 {"GL_EXT_texture_env_combine", NULL
},
122 {"GL_EXT_texture_env_dot3", NULL
},
123 {"GL_EXT_texture_filter_anisotropic", NULL
},
124 {"GL_EXT_texture_lod_bias", NULL
},
125 {"GL_EXT_texture_mirror_clamp", NULL
},
126 {"GL_EXT_texture_rectangle", NULL
},
127 {"GL_EXT_texture_sRGB", NULL
},
128 {"GL_EXT_vertex_array_bgra", NULL
},
129 {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions
},
130 {"GL_ATI_texture_env_combine3", NULL
},
131 {"GL_ATI_texture_mirror_once", NULL
},
132 {"GL_MESA_pack_invert", NULL
},
133 {"GL_MESA_ycbcr_texture", NULL
},
134 {"GL_MESAX_texture_float", NULL
},
135 {"GL_NV_blend_square", NULL
},
136 {"GL_NV_vertex_program", GL_NV_vertex_program_functions
},
137 {"GL_SGIS_generate_mipmap", NULL
},
143 static const struct dri_extension mm_extensions
[] = {
144 { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions
},
145 { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions
},
150 * The GL 2.0 functions are needed to make display lists work with
151 * functions added by GL_ATI_separate_stencil.
153 static const struct dri_extension gl_20_extension
[] = {
154 {"GL_VERSION_2_0", GL_VERSION_2_0_functions
},
157 static const struct tnl_pipeline_stage
*r300_pipeline
[] = {
158 /* Catch any t&l fallbacks
160 &_tnl_vertex_transform_stage
,
161 &_tnl_normal_transform_stage
,
162 &_tnl_lighting_stage
,
163 &_tnl_fog_coordinate_stage
,
165 &_tnl_texture_transform_stage
,
166 &_tnl_point_attenuation_stage
,
167 &_tnl_vertex_program_stage
,
172 static void r300_get_lock(radeonContextPtr rmesa
)
174 drm_radeon_sarea_t
*sarea
= rmesa
->sarea
;
176 if (sarea
->ctx_owner
!= rmesa
->dri
.hwContext
) {
177 sarea
->ctx_owner
= rmesa
->dri
.hwContext
;
178 if (!rmesa
->radeonScreen
->kernel_mm
)
179 radeon_bo_legacy_texture_age(rmesa
->radeonScreen
->bom
);
183 static void r300_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
185 /* please flush pipe do all pending work */
186 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
187 R300_SC_SCREENDOOR
, 1));
188 radeon_cs_write_dword(cs
, 0x0);
189 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
190 R300_SC_SCREENDOOR
, 1));
191 radeon_cs_write_dword(cs
, 0x00FFFFFF);
192 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
194 radeon_cs_write_dword(cs
, 0x0);
195 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
197 radeon_cs_write_dword(cs
, 0x0);
198 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
200 radeon_cs_write_dword(cs
, 0x0);
201 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
, R300_WAIT_3D
));
202 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
203 R300_RB3D_DSTCACHE_CTLSTAT
, 1));
204 radeon_cs_write_dword(cs
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
205 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
206 R300_ZB_ZCACHE_CTLSTAT
, 1));
207 radeon_cs_write_dword(cs
, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
);
208 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
,
209 R300_WAIT_3D
| R300_WAIT_3D_CLEAN
));
212 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon
)
214 BATCH_LOCALS(radeon
);
216 cp_wait(radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
217 BEGIN_BATCH_NO_AUTOSTATE(2);
218 OUT_BATCH_REGVAL(R300_TX_INVALTAGS
, R300_TX_FLUSH
);
223 static void r300_fallback(GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
225 r300ContextPtr r300
= R300_CONTEXT(ctx
);
227 r300
->radeon
.Fallback
|= bit
;
229 r300
->radeon
.Fallback
&= ~bit
;
232 static void r300_emit_query_finish(radeonContextPtr radeon
)
234 r300ContextPtr r300
= (r300ContextPtr
)radeon
;
235 struct radeon_query_object
*query
= radeon
->query
.current
;
236 BATCH_LOCALS(radeon
);
238 BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300
->radeon
.radeonScreen
->num_gb_pipes
+ 2);
239 switch (r300
->radeon
.radeonScreen
->num_gb_pipes
) {
241 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
242 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
243 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
245 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_2
);
246 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
247 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
249 if (r300
->radeon
.radeonScreen
->chip_family
<= CHIP_FAMILY_RV380
) {
250 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
252 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_1
);
254 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
255 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
258 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_0
);
259 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
260 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
263 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
265 query
->curr_offset
+= r300
->radeon
.radeonScreen
->num_gb_pipes
* sizeof(uint32_t);
266 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
267 query
->emitted_begin
= GL_FALSE
;
270 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon
)
272 BATCH_LOCALS(radeon
);
273 struct radeon_query_object
*query
= radeon
->query
.current
;
275 BEGIN_BATCH_NO_AUTOSTATE(8);
276 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
277 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
278 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
279 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
282 query
->curr_offset
+= sizeof(uint32_t);
283 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
284 query
->emitted_begin
= GL_FALSE
;
287 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon
)
289 BATCH_LOCALS(radeon
);
290 struct radeon_query_object
*query
= radeon
->query
.current
;
292 BEGIN_BATCH_NO_AUTOSTATE(14);
293 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
294 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
295 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
296 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
297 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
298 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
299 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
302 query
->curr_offset
+= 2 * sizeof(uint32_t);
303 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
304 query
->emitted_begin
= GL_FALSE
;
307 static void r300_init_vtbl(radeonContextPtr radeon
)
309 radeon
->vtbl
.get_lock
= r300_get_lock
;
310 radeon
->vtbl
.update_viewport_offset
= r300UpdateViewportOffset
;
311 radeon
->vtbl
.emit_cs_header
= r300_vtbl_emit_cs_header
;
312 radeon
->vtbl
.swtcl_flush
= r300_swtcl_flush
;
313 radeon
->vtbl
.pre_emit_atoms
= r300_vtbl_pre_emit_atoms
;
314 radeon
->vtbl
.fallback
= r300_fallback
;
315 if (radeon
->radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
316 if (radeon
->radeonScreen
->num_z_pipes
== 2)
317 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_double_z
;
319 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_single_z
;
321 radeon
->vtbl
.emit_query_finish
= r300_emit_query_finish
;
324 static void r300InitConstValues(GLcontext
*ctx
, radeonScreenPtr screen
)
326 r300ContextPtr r300
= R300_CONTEXT(ctx
);
328 ctx
->Const
.MaxTextureImageUnits
=
329 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_image_units");
330 ctx
->Const
.MaxTextureCoordUnits
=
331 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_coord_units");
332 ctx
->Const
.MaxTextureUnits
= MIN2(ctx
->Const
.MaxTextureImageUnits
,
333 ctx
->Const
.MaxTextureCoordUnits
);
335 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
336 ctx
->Const
.MaxTextureLodBias
= 16.0;
338 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
339 ctx
->Const
.MaxTextureLevels
= 13;
340 ctx
->Const
.MaxCubeTextureLevels
= 13;
341 ctx
->Const
.MaxTextureRectSize
= 4096;
344 ctx
->Const
.MaxTextureLevels
= 12;
345 ctx
->Const
.MaxCubeTextureLevels
= 12;
346 ctx
->Const
.MaxTextureRectSize
= 2048;
349 ctx
->Const
.MinPointSize
= 1.0;
350 ctx
->Const
.MinPointSizeAA
= 1.0;
351 ctx
->Const
.MaxPointSize
= R300_POINTSIZE_MAX
;
352 ctx
->Const
.MaxPointSizeAA
= R300_POINTSIZE_MAX
;
354 ctx
->Const
.MinLineWidth
= 1.0;
355 ctx
->Const
.MinLineWidthAA
= 1.0;
356 ctx
->Const
.MaxLineWidth
= R300_LINESIZE_MAX
;
357 ctx
->Const
.MaxLineWidthAA
= R300_LINESIZE_MAX
;
359 ctx
->Const
.MaxDrawBuffers
= 1;
361 /* currently bogus data */
362 if (r300
->options
.hw_tcl_enabled
) {
363 ctx
->Const
.VertexProgram
.MaxNativeInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
364 ctx
->Const
.VertexProgram
.MaxNativeAluInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
365 ctx
->Const
.VertexProgram
.MaxNativeAttribs
= 16; /* r420 */
366 ctx
->Const
.VertexProgram
.MaxNativeTemps
= 32;
367 ctx
->Const
.VertexProgram
.MaxNativeParameters
= 256; /* r420 */
368 ctx
->Const
.VertexProgram
.MaxNativeAddressRegs
= 1;
371 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
372 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R500_PFS_NUM_TEMP_REGS
;
373 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
375 /* The hardware limits are higher than this,
376 * but the non-KMS DRM interface artificially limits us
377 * to this many instructions.
379 * We could of course work around it in the KMS path,
380 * but it would be a mess, so it seems wiser
381 * to leave it as is. Going forward, the Gallium driver
382 * will not be subject to these limitations.
384 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= 255;
385 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= 255;
386 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= 255;
387 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= 255;
388 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= 255;
389 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
391 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R300_PFS_NUM_TEMP_REGS
;
392 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
393 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= R300_PFS_NUM_CONST_REGS
;
394 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= R300_PFS_MAX_ALU_INST
;
395 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= R300_PFS_MAX_TEX_INST
;
396 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= R300_PFS_MAX_ALU_INST
+ R300_PFS_MAX_TEX_INST
;
397 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= R300_PFS_MAX_TEX_INDIRECT
;
398 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
403 static void r300ParseOptions(r300ContextPtr r300
, radeonScreenPtr screen
)
405 struct r300_options options
= { 0 };
407 driParseConfigFiles(&r300
->radeon
.optionCache
, &screen
->optionCache
,
408 screen
->driScreen
->myNum
, "r300");
410 r300
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&r300
->radeon
.optionCache
, "def_max_anisotropy");
412 options
.stencil_two_side_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_stencil_two_side");
413 options
.s3tc_force_enabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "force_s3tc_enable");
414 options
.s3tc_force_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_s3tc");
416 if (!(screen
->chip_flags
& RADEON_CHIPSET_TCL
) || driQueryOptioni(&r300
->radeon
.optionCache
, "tcl_mode") == DRI_CONF_TCL_SW
)
417 options
.hw_tcl_enabled
= 0;
419 options
.hw_tcl_enabled
= 1;
421 options
.conformance_mode
= !driQueryOptionb(&r300
->radeon
.optionCache
, "disable_lowimpact_fallback");
423 r300
->options
= options
;
426 static void r300InitGLExtensions(GLcontext
*ctx
)
428 r300ContextPtr r300
= R300_CONTEXT(ctx
);
430 driInitExtensions(ctx
, card_extensions
, GL_TRUE
);
431 if (r300
->radeon
.radeonScreen
->kernel_mm
)
432 driInitExtensions(ctx
, mm_extensions
, GL_FALSE
);
434 if (r300
->options
.stencil_two_side_disabled
)
435 _mesa_disable_extension(ctx
, "GL_EXT_stencil_two_side");
437 if (r300
->options
.s3tc_force_disabled
) {
438 _mesa_disable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
439 } else if (ctx
->Mesa_DXTn
|| r300
->options
.s3tc_force_enabled
) {
440 _mesa_enable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
441 _mesa_enable_extension(ctx
, "GL_S3_s3tc");
444 if (!r300
->radeon
.radeonScreen
->drmSupportsOcclusionQueries
) {
445 _mesa_disable_extension(ctx
, "GL_ARB_occlusion_query");
449 /* Create the device specific rendering context.
451 GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
452 __DRIcontextPrivate
* driContextPriv
,
453 void *sharedContextPrivate
)
455 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
456 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
457 struct dd_function_table functions
;
462 assert(driContextPriv
);
465 r300
= (r300ContextPtr
) CALLOC(sizeof(*r300
));
469 r300ParseOptions(r300
, screen
);
471 r300
->radeon
.radeonScreen
= screen
;
472 r300_init_vtbl(&r300
->radeon
);
474 _mesa_init_driver_functions(&functions
);
475 r300InitIoctlFuncs(&functions
);
476 r300InitStateFuncs(&functions
);
477 r300InitTextureFuncs(&functions
);
478 r300InitShaderFuncs(&functions
);
479 radeonInitQueryObjFunctions(&functions
);
480 radeonInitBufferObjectFuncs(&functions
);
482 if (!radeonInitContext(&r300
->radeon
, &functions
,
483 glVisual
, driContextPriv
,
484 sharedContextPrivate
)) {
489 ctx
= r300
->radeon
.glCtx
;
492 if (r300
->options
.hw_tcl_enabled
)
493 ctx
->VertexProgram
._MaintainTnlProgram
= GL_TRUE
;
495 ctx
->FragmentProgram
._MaintainTexEnvProgram
= GL_TRUE
;
497 r300InitConstValues(ctx
, screen
);
499 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
501 /* Initialize the software rasterizer and helper modules.
503 _swrast_CreateContext(ctx
);
504 _vbo_CreateContext(ctx
);
505 _tnl_CreateContext(ctx
);
506 _swsetup_CreateContext(ctx
);
507 _swsetup_Wakeup(ctx
);
509 /* Install the customized pipeline:
511 _tnl_destroy_pipeline(ctx
);
512 _tnl_install_pipeline(ctx
, r300_pipeline
);
513 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= _tnl_run_pipeline
;
515 /* Configure swrast and TNL to match hardware characteristics:
517 _swrast_allow_pixel_fog(ctx
, GL_FALSE
);
518 _swrast_allow_vertex_fog(ctx
, GL_TRUE
);
519 _tnl_allow_pixel_fog(ctx
, GL_FALSE
);
520 _tnl_allow_vertex_fog(ctx
, GL_TRUE
);
522 if (r300
->options
.hw_tcl_enabled
) {
528 radeon_fbo_init(&r300
->radeon
);
529 radeonInitSpanFuncs( ctx
);
530 r300InitCmdBuf(r300
);
532 r300InitShaderFunctions(r300
);
534 r300InitGLExtensions(ctx
);