src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/extensions.h"
  44 #include "main/bufferobj.h"
  45 #include "main/texobj.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55 #include "drivers/common/meta.h"
  56
  57 #include "r300_context.h"
  58 #include "radeon_span.h"
  59 #include "r300_blit.h"
  60 #include "r300_cmdbuf.h"
  61 #include "r300_state.h"
  62 #include "r300_tex.h"
  63 #include "r300_emit.h"
  64 #include "r300_render.h"
  65 #include "r300_swtcl.h"
  66 #include "radeon_bocs_wrapper.h"
  67 #include "radeon_buffer_objects.h"
  68 #include "radeon_queryobj.h"
  69
  70 #include "utils.h"
  71 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  72
  73 #define need_GL_VERSION_2_0
  74 #define need_GL_ARB_occlusion_query
  75 #define need_GL_ARB_point_parameters
  76 #define need_GL_ARB_vertex_program
  77 #define need_GL_EXT_blend_equation_separate
  78 #define need_GL_EXT_blend_func_separate
  79 #define need_GL_EXT_blend_minmax
  80 #define need_GL_EXT_framebuffer_blit
  81 #define need_GL_EXT_framebuffer_object
  82 #define need_GL_EXT_fog_coord
  83 #define need_GL_EXT_gpu_program_parameters
  84 #define need_GL_EXT_provoking_vertex
  85 #define need_GL_EXT_secondary_color
  86 #define need_GL_EXT_stencil_two_side
  87 #define need_GL_ATI_separate_stencil
  88 #define need_GL_NV_vertex_program
  89
  90 #include "main/remap_helper.h"
  91
  92 static const struct dri_extension card_extensions[] = {
  93   /* *INDENT-OFF* */
  94   {"GL_ARB_depth_texture",              NULL},
  95   {"GL_ARB_fragment_program",           NULL},
  96   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  97   {"GL_ARB_multitexture",               NULL},
  98   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
  99   {"GL_ARB_shadow",                     NULL},
 100   {"GL_ARB_shadow_ambient",             NULL},
 101   {"GL_ARB_texture_border_clamp",       NULL},
 102   {"GL_ARB_texture_cube_map",           NULL},
 103   {"GL_ARB_texture_env_add",            NULL},
 104   {"GL_ARB_texture_env_combine",        NULL},
 105   {"GL_ARB_texture_env_crossbar",       NULL},
 106   {"GL_ARB_texture_env_dot3",           NULL},
 107   {"GL_ARB_texture_mirrored_repeat",    NULL},
 108   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 109   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 110   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 111   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 112   {"GL_EXT_blend_subtract",             NULL},
 113   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 114   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 115   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 116   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 117   {"GL_EXT_shadow_funcs",               NULL},
 118   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 119   {"GL_EXT_stencil_wrap",               NULL},
 120   {"GL_EXT_texture_edge_clamp",         NULL},
 121   {"GL_EXT_texture_env_combine",        NULL},
 122   {"GL_EXT_texture_env_dot3",           NULL},
 123   {"GL_EXT_texture_filter_anisotropic", NULL},
 124   {"GL_EXT_texture_lod_bias",           NULL},
 125   {"GL_EXT_texture_mirror_clamp",       NULL},
 126   {"GL_EXT_texture_rectangle",          NULL},
 127   {"GL_EXT_texture_sRGB",               NULL},
 128   {"GL_EXT_vertex_array_bgra",          NULL},
 129   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 130   {"GL_ATI_texture_env_combine3",       NULL},
 131   {"GL_ATI_texture_mirror_once",        NULL},
 132   {"GL_MESA_pack_invert",               NULL},
 133   {"GL_MESA_ycbcr_texture",             NULL},
 134   {"GL_MESAX_texture_float",            NULL},
 135   {"GL_NV_blend_square",                NULL},
 136   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 137   {NULL,                                NULL}
 138   /* *INDENT-ON* */
 139 };
 140
 141
 142 static const struct dri_extension mm_extensions[] = {
 143   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 144   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 145   { NULL, NULL }
 146 };
 147
 148 /**
 149  * The GL 2.0 functions are needed to make display lists work with
 150  * functions added by GL_ATI_separate_stencil.
 151  */
 152 static const struct dri_extension gl_20_extension[] = {
 153   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 154 };
 155
 156 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 157         /* Catch any t&l fallbacks
 158          */
 159         &_tnl_vertex_transform_stage,
 160         &_tnl_normal_transform_stage,
 161         &_tnl_lighting_stage,
 162         &_tnl_fog_coordinate_stage,
 163         &_tnl_texgen_stage,
 164         &_tnl_texture_transform_stage,
 165         &_tnl_point_attenuation_stage,
 166         &_tnl_vertex_program_stage,
 167         &_tnl_render_stage,
 168         0,
 169 };
 170
 171 static void r300_get_lock(radeonContextPtr rmesa)
 172 {
 173         drm_radeon_sarea_t *sarea = rmesa->sarea;
 174
 175         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 176                 sarea->ctx_owner = rmesa->dri.hwContext;
 177                 if (!rmesa->radeonScreen->kernel_mm)
 178                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 179         }
 180 }
 181
 182 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 183 {
 184     /* please flush pipe do all pending work */
 185     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 186                                   R300_SC_SCREENDOOR, 1));
 187     radeon_cs_write_dword(cs, 0x0);
 188     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 189                                   R300_SC_SCREENDOOR, 1));
 190     radeon_cs_write_dword(cs, 0x00FFFFFF);
 191     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 192                                   R300_SC_HYPERZ, 1));
 193     radeon_cs_write_dword(cs, 0x0);
 194     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 195                                   R300_US_CONFIG, 1));
 196     radeon_cs_write_dword(cs, 0x0);
 197     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 198                                   R300_ZB_CNTL, 1));
 199     radeon_cs_write_dword(cs, 0x0);
 200     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 201     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 202                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 203     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 204     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 205                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 206     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 207     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 208                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 209 }
 210
 211 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 212 {
 213         BATCH_LOCALS(radeon);
 214
 215         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 216         BEGIN_BATCH_NO_AUTOSTATE(2);
 217         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 218         END_BATCH();
 219         end_3d(radeon);
 220 }
 221
 222 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 223 {
 224         r300ContextPtr r300 = R300_CONTEXT(ctx);
 225         if (mode)
 226                 r300->radeon.Fallback |= bit;
 227         else
 228                 r300->radeon.Fallback &= ~bit;
 229
 230         r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode);
 231 }
 232
 233 static void r300_emit_query_finish(radeonContextPtr radeon)
 234 {
 235         r300ContextPtr r300 = (r300ContextPtr)radeon;
 236         struct radeon_query_object *query = radeon->query.current;
 237         BATCH_LOCALS(radeon);
 238
 239         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 240         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 241         case 4:
 242                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 243                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 244                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 245         case 3:
 246                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 247                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 248                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 249         case 2:
 250                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 251                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 252                 } else {
 253                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 254                 }
 255                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 256                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 257         case 1:
 258         default:
 259                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 260                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 261                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 262                 break;
 263         }
 264         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 265         END_BATCH();
 266         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 267         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 268         query->emitted_begin = GL_FALSE;
 269 }
 270
 271 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 272 {
 273         BATCH_LOCALS(radeon);
 274         struct radeon_query_object *query = radeon->query.current;
 275
 276         BEGIN_BATCH_NO_AUTOSTATE(8);
 277         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 278         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 279         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 280         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 281         END_BATCH();
 282
 283         query->curr_offset += sizeof(uint32_t);
 284         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 285         query->emitted_begin = GL_FALSE;
 286 }
 287
 288 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 289 {
 290         BATCH_LOCALS(radeon);
 291         struct radeon_query_object *query = radeon->query.current;
 292
 293         BEGIN_BATCH_NO_AUTOSTATE(14);
 294         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 295         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 296         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 297         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 298         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 299         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 300         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 301         END_BATCH();
 302
 303         query->curr_offset += 2 * sizeof(uint32_t);
 304         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 305         query->emitted_begin = GL_FALSE;
 306 }
 307
 308 static void r300_init_vtbl(radeonContextPtr radeon)
 309 {
 310         radeon->vtbl.get_lock = r300_get_lock;
 311         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 312         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 313         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 314         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 315         radeon->vtbl.fallback = r300_fallback;
 316         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 317                 if (radeon->radeonScreen->num_z_pipes == 2)
 318                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 319                 else
 320                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 321         } else
 322                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 323
 324         radeon->vtbl.check_blit = r300_check_blit;
 325         radeon->vtbl.blit = r300_blit;
 326
 327         if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 328                 radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
 329         } else {
 330                 radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
 331         }
 332 }
 333
 334 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 335 {
 336         r300ContextPtr r300 = R300_CONTEXT(ctx);
 337
 338         ctx->Const.MaxTextureImageUnits =
 339             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 340         ctx->Const.MaxTextureCoordUnits =
 341             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 342         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 343                  ctx->Const.MaxTextureCoordUnits);
 344         ctx->Const.MaxCombinedTextureImageUnits =
 345                 ctx->Const.MaxVertexTextureImageUnits +
 346                 ctx->Const.MaxTextureImageUnits;
 347
 348
 349         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 350         ctx->Const.MaxTextureLodBias = 16.0;
 351
 352         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 353                 ctx->Const.MaxTextureLevels = 13;
 354                 ctx->Const.MaxCubeTextureLevels = 13;
 355                 ctx->Const.MaxTextureRectSize = 4096;
 356                 ctx->Const.MaxRenderbufferSize = 4096;
 357         }
 358         else {
 359                 ctx->Const.MaxTextureLevels = 12;
 360                 ctx->Const.MaxCubeTextureLevels = 12;
 361                 ctx->Const.MaxTextureRectSize = 2048;
 362                 ctx->Const.MaxRenderbufferSize = 2048;
 363         }
 364
 365         ctx->Const.MinPointSize = 1.0;
 366         ctx->Const.MinPointSizeAA = 1.0;
 367         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 368         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 369
 370         ctx->Const.MinLineWidth = 1.0;
 371         ctx->Const.MinLineWidthAA = 1.0;
 372         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 373         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 374
 375         ctx->Const.MaxDrawBuffers = 1;
 376         ctx->Const.MaxColorAttachments = 1;
 377
 378         if (r300->options.hw_tcl_enabled) {
 379                 ctx->Const.VertexProgram.MaxNativeInstructions = 255;
 380                 ctx->Const.VertexProgram.MaxNativeAluInstructions = 255;
 381                 ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 382                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 383                 ctx->Const.VertexProgram.MaxNativeParameters = 256;
 384                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 385         }
 386
 387         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 388                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 389                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 390
 391                 /* The hardware limits are higher than this,
 392                  * but the non-KMS DRM interface artificially limits us
 393                  * to this many instructions.
 394                  *
 395                  * We could of course work around it in the KMS path,
 396                  * but it would be a mess, so it seems wiser
 397                  * to leave it as is. Going forward, the Gallium driver
 398                  * will not be subject to these limitations.
 399                  */
 400                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 401                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 402                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 403                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 404                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 405                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 406         } else {
 407                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 408                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 409                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 410                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 411                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 412                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 413                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 414                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 415         }
 416
 417 }
 418
 419 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 420 {
 421         struct r300_options options = { 0 };
 422
 423         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 424                             screen->driScreen->myNum, "r300");
 425
 426         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 427
 428         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 429         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 430         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 431
 432         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 433                 options.hw_tcl_enabled = 0;
 434         else
 435                 options.hw_tcl_enabled = 1;
 436
 437         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 438
 439         r300->options = options;
 440 }
 441
 442 static void r300InitGLExtensions(GLcontext *ctx)
 443 {
 444         r300ContextPtr r300 = R300_CONTEXT(ctx);
 445
 446         driInitExtensions(ctx, card_extensions, GL_TRUE);
 447         if (r300->radeon.radeonScreen->kernel_mm)
 448                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 449
 450         if (r300->options.stencil_two_side_disabled)
 451                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 452
 453         if (r300->options.s3tc_force_disabled) {
 454                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 455         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 456                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 457                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 458         }
 459
 460         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 461                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 462         }
 463         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_R420)
 464                 _mesa_enable_extension(ctx, "GL_ARB_half_float_vertex");
 465
 466         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 467                 _mesa_enable_extension(ctx, "GL_EXT_packed_depth_stencil");
 468 }
 469
 470 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 471 {
 472         functions->Clear = _mesa_meta_Clear;
 473         functions->Finish = radeonFinish;
 474         functions->Flush = radeonFlush;
 475 }
 476
 477 /* Create the device specific rendering context.
 478  */
 479 GLboolean r300CreateContext(gl_api api,
 480                             const __GLcontextModes * glVisual,
 481                             __DRIcontext * driContextPriv,
 482                             void *sharedContextPrivate)
 483 {
 484         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 485         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 486         struct dd_function_table functions;
 487         r300ContextPtr r300;
 488         GLcontext *ctx;
 489
 490         assert(glVisual);
 491         assert(driContextPriv);
 492         assert(screen);
 493
 494         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 495         if (!r300)
 496                 return GL_FALSE;
 497
 498         r300ParseOptions(r300, screen);
 499
 500         r300->radeon.radeonScreen = screen;
 501         r300_init_vtbl(&r300->radeon);
 502
 503         _mesa_init_driver_functions(&functions);
 504         r300InitIoctlFuncs(&functions);
 505         r300InitStateFuncs(&r300->radeon, &functions);
 506         r300InitTextureFuncs(&r300->radeon, &functions);
 507         r300InitShaderFuncs(&functions);
 508         radeonInitQueryObjFunctions(&functions);
 509         radeonInitBufferObjectFuncs(&functions);
 510
 511         if (!radeonInitContext(&r300->radeon, &functions,
 512                                glVisual, driContextPriv,
 513                                sharedContextPrivate)) {
 514                 FREE(r300);
 515                 return GL_FALSE;
 516         }
 517
 518         ctx = r300->radeon.glCtx;
 519
 520         r300->fallback = 0;
 521         if (r300->options.hw_tcl_enabled)
 522                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 523
 524         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 525
 526         r300InitConstValues(ctx, screen);
 527
 528         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 529
 530         /* Initialize the software rasterizer and helper modules.
 531          */
 532         _swrast_CreateContext(ctx);
 533         _vbo_CreateContext(ctx);
 534         _tnl_CreateContext(ctx);
 535         _swsetup_CreateContext(ctx);
 536         _swsetup_Wakeup(ctx);
 537
 538         /* Install the customized pipeline:
 539          */
 540         _tnl_destroy_pipeline(ctx);
 541         _tnl_install_pipeline(ctx, r300_pipeline);
 542         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 543
 544         /* Configure swrast and TNL to match hardware characteristics:
 545          */
 546         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 547         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 548         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 549         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 550
 551         if (r300->options.hw_tcl_enabled) {
 552                 r300InitDraw(ctx);
 553         } else {
 554                 r300InitSwtcl(ctx);
 555         }
 556
 557         r300_blit_init(r300);
 558         radeon_fbo_init(&r300->radeon);
 559         radeonInitSpanFuncs( ctx );
 560         r300InitCmdBuf(r300);
 561         r300InitState(r300);
 562         r300InitShaderFunctions(r300);
 563
 564         r300InitGLExtensions(ctx);
 565
 566         return GL_TRUE;
 567 }
 568