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Merge commit 'nha/r300-compiler-gallium'
[mesa.git] / src / mesa / drivers / dri / r300 / r300_ioctl.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
4 All Rights Reserved.
5
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
9
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
17
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
21
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
30 **************************************************************************/
31
32 /**
33 * \file
34 *
35 * \author Keith Whitwell <keith@tungstengraphics.com>
36 *
37 * \author Nicolai Haehnle <prefect_@gmx.net>
38 */
39
40 #include <sched.h>
41 #include <errno.h>
42
43 #include "main/glheader.h"
44 #include "main/imports.h"
45 #include "main/macros.h"
46 #include "main/context.h"
47 #include "swrast/swrast.h"
48
49 #include "radeon_common.h"
50 #include "radeon_lock.h"
51 #include "r300_context.h"
52 #include "r300_ioctl.h"
53 #include "r300_cmdbuf.h"
54 #include "r300_state.h"
55 #include "r300_vertprog.h"
56 #include "radeon_reg.h"
57 #include "r300_emit.h"
58 #include "r300_context.h"
59
60 #include "vblank.h"
61
62 #define R200_3D_DRAW_IMMD_2 0xC0003500
63
64 #define CLEARBUFFER_COLOR 0x1
65 #define CLEARBUFFER_DEPTH 0x2
66 #define CLEARBUFFER_STENCIL 0x4
67
68 #if 1
69
70 /**
71 * Fragment program helper macros
72 */
73
74 /* Produce unshifted source selectors */
75 #define FP_TMP(idx) (idx)
76 #define FP_CONST(idx) ((idx) | (1 << 5))
77
78 /* Produce source/dest selector dword */
79 #define FP_SELC_MASK_NO 0
80 #define FP_SELC_MASK_X 1
81 #define FP_SELC_MASK_Y 2
82 #define FP_SELC_MASK_XY 3
83 #define FP_SELC_MASK_Z 4
84 #define FP_SELC_MASK_XZ 5
85 #define FP_SELC_MASK_YZ 6
86 #define FP_SELC_MASK_XYZ 7
87
88 #define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
89 (((destidx) << R300_ALU_DSTC_SHIFT) | \
90 (FP_SELC_MASK_##regmask << 23) | \
91 (FP_SELC_MASK_##outmask << 26) | \
92 ((src0) << R300_ALU_SRC0C_SHIFT) | \
93 ((src1) << R300_ALU_SRC1C_SHIFT) | \
94 ((src2) << R300_ALU_SRC2C_SHIFT))
95
96 #define FP_SELA_MASK_NO 0
97 #define FP_SELA_MASK_W 1
98
99 #define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
100 (((destidx) << R300_ALU_DSTA_SHIFT) | \
101 (FP_SELA_MASK_##regmask << 23) | \
102 (FP_SELA_MASK_##outmask << 24) | \
103 ((src0) << R300_ALU_SRC0A_SHIFT) | \
104 ((src1) << R300_ALU_SRC1A_SHIFT) | \
105 ((src2) << R300_ALU_SRC2A_SHIFT))
106
107 /* Produce unshifted argument selectors */
108 #define FP_ARGC(source) R300_ALU_ARGC_##source
109 #define FP_ARGA(source) R300_ALU_ARGA_##source
110 #define FP_ABS(arg) ((arg) | (1 << 6))
111 #define FP_NEG(arg) ((arg) ^ (1 << 5))
112
113 /* Produce instruction dword */
114 #define FP_INSTRC(opcode,arg0,arg1,arg2) \
115 (R300_ALU_OUTC_##opcode | \
116 ((arg0) << R300_ALU_ARG0C_SHIFT) | \
117 ((arg1) << R300_ALU_ARG1C_SHIFT) | \
118 ((arg2) << R300_ALU_ARG2C_SHIFT))
119
120 #define FP_INSTRA(opcode,arg0,arg1,arg2) \
121 (R300_ALU_OUTA_##opcode | \
122 ((arg0) << R300_ALU_ARG0A_SHIFT) | \
123 ((arg1) << R300_ALU_ARG1A_SHIFT) | \
124 ((arg2) << R300_ALU_ARG2A_SHIFT))
125
126 #endif
127
128 static void r300EmitClearState(GLcontext * ctx);
129
130 static void r300ClearBuffer(r300ContextPtr r300, int flags,
131 struct radeon_renderbuffer *rrb,
132 struct radeon_renderbuffer *rrbd)
133 {
134 BATCH_LOCALS(&r300->radeon);
135 GLcontext *ctx = r300->radeon.glCtx;
136 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
137 GLuint cbpitch = 0;
138 r300ContextPtr rmesa = r300;
139
140 if (RADEON_DEBUG & DEBUG_IOCTL)
141 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
142 __FUNCTION__, rrb, dPriv->x, dPriv->y,
143 dPriv->w, dPriv->h);
144
145 if (rrb) {
146 cbpitch = (rrb->pitch / rrb->cpp);
147 if (rrb->cpp == 4)
148 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
149 else
150 cbpitch |= R300_COLOR_FORMAT_RGB565;
151
152 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
153 cbpitch |= R300_COLOR_TILE_ENABLE;
154 }
155 }
156
157 /* TODO in bufmgr */
158 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
159 end_3d(&rmesa->radeon);
160
161 if (flags & CLEARBUFFER_COLOR) {
162 assert(rrb != 0);
163 BEGIN_BATCH_NO_AUTOSTATE(6);
164 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
165 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
166 OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
167 END_BATCH();
168 }
169 #if 1
170 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
171 uint32_t zbpitch = (rrbd->pitch / rrbd->cpp);
172 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
173 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
174 }
175 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
176 zbpitch |= R300_DEPTHMICROTILE_TILED;
177 }
178 BEGIN_BATCH_NO_AUTOSTATE(6);
179 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
180 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
181 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
182 if (!r300->radeon.radeonScreen->kernel_mm)
183 OUT_BATCH(zbpitch);
184 else
185 OUT_BATCH_RELOC(zbpitch, rrbd->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
186 END_BATCH();
187 }
188 #endif
189 BEGIN_BATCH_NO_AUTOSTATE(6);
190 OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
191 if (flags & CLEARBUFFER_COLOR) {
192 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
193 (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
194 (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
195 (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
196 } else {
197 OUT_BATCH(0);
198 }
199
200
201 {
202 uint32_t t1, t2;
203
204 t1 = 0x0;
205 t2 = 0x0;
206
207 if (flags & CLEARBUFFER_DEPTH) {
208 t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
209 t2 |=
210 (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
211 }
212
213 if (flags & CLEARBUFFER_STENCIL) {
214 t1 |= R300_STENCIL_ENABLE;
215 t2 |=
216 (R300_ZS_ALWAYS <<
217 R300_S_FRONT_FUNC_SHIFT) |
218 (R300_ZS_REPLACE <<
219 R300_S_FRONT_SFAIL_OP_SHIFT) |
220 (R300_ZS_REPLACE <<
221 R300_S_FRONT_ZPASS_OP_SHIFT) |
222 (R300_ZS_REPLACE <<
223 R300_S_FRONT_ZFAIL_OP_SHIFT);
224 }
225
226 OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
227 OUT_BATCH(t1);
228 OUT_BATCH(t2);
229 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
230 R300_STENCILWRITEMASK_SHIFT) |
231 (ctx->Stencil.Clear & R300_STENCILREF_MASK));
232 END_BATCH();
233 }
234
235 if (!rmesa->radeon.radeonScreen->kernel_mm) {
236 BEGIN_BATCH_NO_AUTOSTATE(9);
237 OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
238 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
239 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
240 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
241 OUT_BATCH_FLOAT32(1.0);
242 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
243 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
244 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
245 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
246 END_BATCH();
247 } else {
248 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
249 OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
250 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
251 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
252 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
253 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
254 OUT_BATCH_FLOAT32(1.0);
255 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
256 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
257 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
258 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
259 }
260
261 r300EmitCacheFlush(rmesa);
262 cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
263
264 R300_STATECHANGE(r300, cb);
265 R300_STATECHANGE(r300, cmk);
266 R300_STATECHANGE(r300, zs);
267 }
268
269 static void r300EmitClearState(GLcontext * ctx)
270 {
271 r300ContextPtr r300 = R300_CONTEXT(ctx);
272 BATCH_LOCALS(&r300->radeon);
273 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
274 int i;
275 int has_tcl;
276 int is_r500 = 0;
277 GLuint vap_cntl;
278
279 has_tcl = r300->options.hw_tcl_enabled;
280
281 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
282 is_r500 = 1;
283
284 /* State atom dirty tracking is a little subtle here.
285 *
286 * On the one hand, we need to make sure base state is emitted
287 * here if we start with an empty batch buffer, otherwise clear
288 * works incorrectly with multiple processes. Therefore, the first
289 * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
290 *
291 * On the other hand, implicit state emission clears the state atom
292 * dirty bits, so we have to call R300_STATECHANGE later than the
293 * first BEGIN_BATCH.
294 *
295 * The final trickiness is that, because we change state, we need
296 * to ensure that any stored swtcl primitives are flushed properly
297 * before we start changing state. See the R300_NEWPRIM in r300Clear
298 * for this.
299 */
300 BEGIN_BATCH(31);
301 OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
302 if (!has_tcl)
303 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
304 ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
305 else
306 OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
307 ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
308
309 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
310 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
311 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
312 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
313 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
314 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
315 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
316 << R300_SWIZZLE0_SHIFT) |
317 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
318 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
319 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
320 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
321 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
322 << R300_SWIZZLE1_SHIFT)));
323
324 /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
325 OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
326 OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
327 OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
328
329 /* comes from fglrx startup of clear */
330 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
331 OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
332 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
333 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
334 R300_VPORT_Z_OFFSET_ENA);
335 OUT_BATCH(0x8);
336
337 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
338
339 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
340 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
341 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
342 OUT_BATCH(0); /* no textures */
343
344 OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
345
346 OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
347 OUT_BATCH_FLOAT32(1.0);
348 OUT_BATCH_FLOAT32(dPriv->x);
349 OUT_BATCH_FLOAT32(1.0);
350 OUT_BATCH_FLOAT32(dPriv->y);
351 OUT_BATCH_FLOAT32(1.0);
352 OUT_BATCH_FLOAT32(0.0);
353
354 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
355
356 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
357 OUT_BATCH(0x0);
358 OUT_BATCH(0x0);
359 END_BATCH();
360
361 R300_STATECHANGE(r300, vir[0]);
362 R300_STATECHANGE(r300, fogs);
363 R300_STATECHANGE(r300, vir[1]);
364 R300_STATECHANGE(r300, vic);
365 R300_STATECHANGE(r300, vte);
366 R300_STATECHANGE(r300, vof);
367 R300_STATECHANGE(r300, txe);
368 R300_STATECHANGE(r300, vpt);
369 R300_STATECHANGE(r300, at);
370 R300_STATECHANGE(r300, bld);
371 R300_STATECHANGE(r300, ps);
372
373 if (has_tcl) {
374 R300_STATECHANGE(r300, vap_clip_cntl);
375
376 BEGIN_BATCH_NO_AUTOSTATE(2);
377 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
378 END_BATCH();
379 }
380
381 BEGIN_BATCH_NO_AUTOSTATE(2);
382 OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
383 ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
384 ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
385 END_BATCH();
386
387 if (!is_r500) {
388 R300_STATECHANGE(r300, ri);
389 R300_STATECHANGE(r300, rc);
390 R300_STATECHANGE(r300, rr);
391
392 BEGIN_BATCH(14);
393 OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
394 for (i = 0; i < 8; ++i)
395 OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
396
397 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
398 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
399 OUT_BATCH(0x0);
400
401 OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
402 END_BATCH();
403 } else {
404 R300_STATECHANGE(r300, ri);
405 R300_STATECHANGE(r300, rc);
406 R300_STATECHANGE(r300, rr);
407
408 BEGIN_BATCH(14);
409 OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
410 for (i = 0; i < 8; ++i) {
411 OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
412 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
413 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
414 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
415 }
416
417 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
418 OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
419 OUT_BATCH(0x0);
420
421 OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
422 END_BATCH();
423 }
424
425 if (!is_r500) {
426 R300_STATECHANGE(r300, fp);
427 R300_STATECHANGE(r300, fpi[0]);
428 R300_STATECHANGE(r300, fpi[1]);
429 R300_STATECHANGE(r300, fpi[2]);
430 R300_STATECHANGE(r300, fpi[3]);
431
432 BEGIN_BATCH(17);
433 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
434 OUT_BATCH(0x0);
435 OUT_BATCH(0x0);
436 OUT_BATCH(0x0);
437 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
438 OUT_BATCH(0x0);
439 OUT_BATCH(0x0);
440 OUT_BATCH(0x0);
441 OUT_BATCH(R300_RGBA_OUT);
442
443 OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
444 FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
445 OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
446 FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
447 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
448 FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
449 OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
450 FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
451 END_BATCH();
452 } else {
453 struct radeon_state_atom r500fp;
454 uint32_t _cmd[10];
455
456 R300_STATECHANGE(r300, fp);
457 R300_STATECHANGE(r300, r500fp);
458
459 BEGIN_BATCH(7);
460 OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
461 OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
462 OUT_BATCH(0x0);
463 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
464 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
465 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
466 OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
467 END_BATCH();
468
469 r500fp.check = check_r500fp;
470 r500fp.cmd = _cmd;
471 r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
472 r500fp.cmd[1] = R500_INST_TYPE_OUT |
473 R500_INST_TEX_SEM_WAIT |
474 R500_INST_LAST |
475 R500_INST_RGB_OMASK_R |
476 R500_INST_RGB_OMASK_G |
477 R500_INST_RGB_OMASK_B |
478 R500_INST_ALPHA_OMASK |
479 R500_INST_RGB_CLAMP |
480 R500_INST_ALPHA_CLAMP;
481 r500fp.cmd[2] = R500_RGB_ADDR0(0) |
482 R500_RGB_ADDR1(0) |
483 R500_RGB_ADDR1_CONST |
484 R500_RGB_ADDR2(0) |
485 R500_RGB_ADDR2_CONST;
486 r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
487 R500_ALPHA_ADDR1(0) |
488 R500_ALPHA_ADDR1_CONST |
489 R500_ALPHA_ADDR2(0) |
490 R500_ALPHA_ADDR2_CONST;
491 r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
492 R500_ALU_RGB_R_SWIZ_A_R |
493 R500_ALU_RGB_G_SWIZ_A_G |
494 R500_ALU_RGB_B_SWIZ_A_B |
495 R500_ALU_RGB_SEL_B_SRC0 |
496 R500_ALU_RGB_R_SWIZ_B_R |
497 R500_ALU_RGB_B_SWIZ_B_G |
498 R500_ALU_RGB_G_SWIZ_B_B;
499 r500fp.cmd[5] = R500_ALPHA_OP_CMP |
500 R500_ALPHA_SWIZ_A_A |
501 R500_ALPHA_SWIZ_B_A;
502 r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
503 R500_ALU_RGBA_R_SWIZ_0 |
504 R500_ALU_RGBA_G_SWIZ_0 |
505 R500_ALU_RGBA_B_SWIZ_0 |
506 R500_ALU_RGBA_A_SWIZ_0;
507
508 r500fp.cmd[7] = 0;
509 emit_r500fp(ctx, &r500fp);
510 }
511
512 BEGIN_BATCH(2);
513 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
514 END_BATCH();
515
516 if (has_tcl) {
517 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
518 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
519 (12 << R300_VF_MAX_VTX_NUM_SHIFT));
520 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
521 vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
522 } else {
523 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
524 (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
525 (5 << R300_VF_MAX_VTX_NUM_SHIFT));
526 }
527
528 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
529 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
530 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
531 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
532 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
533 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
534 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
535 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
536 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
537 else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
538 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
539 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
540 else
541 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
542
543 R300_STATECHANGE(r300, vap_cntl);
544
545 BEGIN_BATCH(2);
546 OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
547 END_BATCH();
548
549 if (has_tcl) {
550 struct radeon_state_atom vpu;
551 uint32_t _cmd[10];
552 R300_STATECHANGE(r300, pvs);
553 R300_STATECHANGE(r300, vpi);
554
555 BEGIN_BATCH(4);
556 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
557 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
558 (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
559 (1 << R300_PVS_LAST_INST_SHIFT));
560 OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
561 (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
562 OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
563 END_BATCH();
564
565 vpu.check = check_vpu;
566 vpu.cmd = _cmd;
567 vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
568
569 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
570 0, 0xf, PVS_DST_REG_OUT);
571 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
572 PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
573 PVS_SRC_REG_INPUT, NEGATE_NONE);
574 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
575 PVS_SRC_SELECT_FORCE_0,
576 PVS_SRC_SELECT_FORCE_0,
577 PVS_SRC_SELECT_FORCE_0,
578 PVS_SRC_REG_INPUT, NEGATE_NONE);
579 vpu.cmd[4] = 0x0;
580
581 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
582 PVS_DST_REG_OUT);
583 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
584 PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
585 PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
586 NEGATE_NONE);
587 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
588 PVS_SRC_SELECT_FORCE_0,
589 PVS_SRC_SELECT_FORCE_0,
590 PVS_SRC_SELECT_FORCE_0,
591 PVS_SRC_REG_INPUT, NEGATE_NONE);
592 vpu.cmd[8] = 0x0;
593
594 r300->vap_flush_needed = GL_TRUE;
595 emit_vpu(ctx, &vpu);
596 }
597 }
598
599 static int r300KernelClear(GLcontext *ctx, GLuint flags)
600 {
601 r300ContextPtr r300 = R300_CONTEXT(ctx);
602 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
603 struct radeon_framebuffer *rfb = dPriv->driverPrivate;
604 struct radeon_renderbuffer *rrb;
605 struct radeon_renderbuffer *rrbd;
606 int bits = 0, ret;
607
608 /* Make sure it fits there. */
609 radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
610
611 if (flags & BUFFER_BIT_COLOR0) {
612 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
613 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
614 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
615 }
616
617 if (flags & BUFFER_BIT_FRONT_LEFT) {
618 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
619 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
620 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
621 }
622
623 if (flags & BUFFER_BIT_BACK_LEFT) {
624 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
625 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
626 rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM);
627 }
628
629 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
630 if (rrbd) {
631 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
632 rrbd->bo, 0, RADEON_GEM_DOMAIN_VRAM);
633 }
634
635 ret = radeon_cs_space_check(r300->radeon.cmdbuf.cs);
636 if (ret)
637 return -1;
638
639 rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
640 if (flags || bits)
641 r300EmitClearState(ctx);
642
643 rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
644 if (rrbd && (flags & BUFFER_BIT_DEPTH))
645 bits |= CLEARBUFFER_DEPTH;
646
647 if (rrbd && (flags & BUFFER_BIT_STENCIL))
648 bits |= CLEARBUFFER_STENCIL;
649
650 if (flags & BUFFER_BIT_COLOR0) {
651 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
652 r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
653 bits = 0;
654 }
655
656 if (flags & BUFFER_BIT_FRONT_LEFT) {
657 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
658 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
659 bits = 0;
660 }
661
662 if (flags & BUFFER_BIT_BACK_LEFT) {
663 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
664 r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
665 bits = 0;
666 }
667
668 if (bits)
669 r300ClearBuffer(r300, bits, NULL, rrbd);
670
671 COMMIT_BATCH();
672 return 0;
673 }
674
675 /**
676 * Buffer clear
677 */
678 static void r300Clear(GLcontext * ctx, GLbitfield mask)
679 {
680 r300ContextPtr r300 = R300_CONTEXT(ctx);
681 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
682 const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
683 GLbitfield swrast_mask = 0, tri_mask = 0;
684 int i, ret;
685 struct gl_framebuffer *fb = ctx->DrawBuffer;
686
687 if (RADEON_DEBUG & DEBUG_IOCTL)
688 fprintf(stderr, "r300Clear\n");
689
690 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
691 LOCK_HARDWARE(&r300->radeon);
692 UNLOCK_HARDWARE(&r300->radeon);
693 if (dPriv->numClipRects == 0)
694 return;
695 }
696
697 /* Flush swtcl vertices if necessary, because we will change hardware
698 * state during clear. See also the state-related comment in
699 * r300EmitClearState.
700 */
701 R300_NEWPRIM(r300);
702
703 if (colorMask == ~0)
704 tri_mask |= (mask & BUFFER_BITS_COLOR);
705 else
706 tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
707
708
709 /* HW stencil */
710 if (mask & BUFFER_BIT_STENCIL) {
711 tri_mask |= BUFFER_BIT_STENCIL;
712 }
713
714 /* HW depth */
715 if (mask & BUFFER_BIT_DEPTH) {
716 tri_mask |= BUFFER_BIT_DEPTH;
717 }
718
719 /* If we're doing a tri pass for depth/stencil, include a likely color
720 * buffer with it.
721 */
722
723 for (i = 0; i < BUFFER_COUNT; i++) {
724 GLuint bufBit = 1 << i;
725 if ((tri_mask) & bufBit) {
726 if (!fb->Attachment[i].Renderbuffer->ClassID) {
727 tri_mask &= ~bufBit;
728 swrast_mask |= bufBit;
729 }
730 }
731 }
732
733 /* SW fallback clearing */
734 swrast_mask = mask & ~tri_mask;
735
736 ret = 0;
737 if (tri_mask) {
738 if (r300->radeon.radeonScreen->kernel_mm)
739 radeonUserClear(ctx, tri_mask);
740 else {
741 /* if kernel clear fails due to size restraints fallback */
742 ret = r300KernelClear(ctx, tri_mask);
743 if (ret < 0)
744 swrast_mask |= tri_mask;
745 }
746 }
747
748 if (swrast_mask) {
749 if (RADEON_DEBUG & DEBUG_FALLBACKS)
750 fprintf(stderr, "%s: swrast clear, mask: %x\n",
751 __FUNCTION__, swrast_mask);
752 _swrast_Clear(ctx, swrast_mask);
753 }
754 }
755
756
757 void r300InitIoctlFuncs(struct dd_function_table *functions)
758 {
759 functions->Clear = r300Clear;
760 functions->Finish = radeonFinish;
761 functions->Flush = radeonFlush;
762 }