src/mesa/drivers/dri/r600/r600_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R600_CONTEXT_H__
  38 #define __R600_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_common.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 #include "r700_chip.h"
  52 #include "r600_tex.h"
  53 #include "r700_oglprog.h"
  54 #include "r700_vertprog.h"
  55
  56 struct r600_context;
  57 typedef struct r600_context context_t;
  58
  59 #include "main/mm.h"
  60
  61 #define COLOR_IS_RGBA
  62 #define TAG(x) r600##x
  63 #include "tnl_dd/t_dd_vertex.h"
  64 #undef TAG
  65
  66 #define R600_FALLBACK_NONE 0
  67 #define R600_FALLBACK_TCL 1
  68 #define R600_FALLBACK_RAST 2
  69
  70 struct r600_hw_state {
  71         struct radeon_state_atom sq;
  72         struct radeon_state_atom db;
  73         struct radeon_state_atom stencil;
  74         struct radeon_state_atom db_target;
  75         struct radeon_state_atom sc;
  76         struct radeon_state_atom scissor;
  77         struct radeon_state_atom aa;
  78         struct radeon_state_atom cl;
  79         struct radeon_state_atom gb;
  80         struct radeon_state_atom ucp;
  81         struct radeon_state_atom su;
  82         struct radeon_state_atom poly;
  83         struct radeon_state_atom cb;
  84         struct radeon_state_atom clrcmp;
  85         struct radeon_state_atom blnd;
  86         struct radeon_state_atom blnd_clr;
  87         struct radeon_state_atom cb_target;
  88         struct radeon_state_atom sx;
  89         struct radeon_state_atom vgt;
  90         struct radeon_state_atom spi;
  91         struct radeon_state_atom vpt;
  92
  93         struct radeon_state_atom fs;
  94         struct radeon_state_atom vs;
  95         struct radeon_state_atom ps;
  96
  97         struct radeon_state_atom vs_consts;
  98         struct radeon_state_atom ps_consts;
  99
 100         struct radeon_state_atom vtx;
 101         struct radeon_state_atom tx;
 102         struct radeon_state_atom tx_smplr;
 103         struct radeon_state_atom tx_brdr_clr;
 104 };
 105
 106 typedef struct StreamDesc
 107 {
 108         GLint   size;   //number of data element
 109         GLenum  type;  //data element type
 110         GLsizei stride;
 111         GLenum  format; // GL_RGBA,GLBGRA
 112
 113         struct radeon_bo *bo;
 114         GLint  bo_offset;
 115
 116         GLuint    dwords;
 117         GLuint    dst_loc;
 118         GLuint    _signed;
 119         GLboolean normalize;
 120         GLboolean is_named_bo;
 121         GLubyte   element;
 122 } StreamDesc;
 123
 124 typedef struct r700_index_buffer
 125 {
 126         struct radeon_bo *bo;
 127         int    bo_offset;
 128
 129         GLboolean is_32bit;
 130         GLuint    count;
 131 } r700_index_buffer;
 132
 133 /**
 134  * \brief R600 context structure.
 135  */
 136 struct r600_context {
 137         struct radeon_context radeon;   /* parent class, must be first */
 138
 139         /* ------ */
 140         R700_CHIP_CONTEXT hw;
 141
 142         struct r600_hw_state atoms;
 143
 144         struct r700_vertex_program *selected_vp;
 145
 146         /* Vertex buffers
 147          */
 148         GLint      nNumActiveAos;
 149         StreamDesc stream_desc[VERT_ATTRIB_MAX];
 150     struct r700_index_buffer ind_buf;
 151         struct radeon_bo *blit_bo;
 152         GLboolean blit_bo_loaded;
 153 };
 154
 155 #define R700_CONTEXT(ctx)               ((context_t *)(ctx->DriverCtx))
 156 #define GL_CONTEXT(context)     ((GLcontext *)(context->radeon.glCtx))
 157
 158 extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 159                                    __DRIcontext * driContextPriv,
 160                                    void *sharedContextPrivate);
 161
 162 #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
 163
 164 #define R600_NEWPRIM( rmesa )                   \
 165 do {                                            \
 166         if ( rmesa->radeon.dma.flush )                  \
 167                 rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
 168 } while (0)
 169
 170 #define R600_STATECHANGE(r600, ATOM)                    \
 171 do {                                                    \
 172         R600_NEWPRIM(r600);                                     \
 173         r600->atoms.ATOM.dirty = GL_TRUE;                                       \
 174         r600->radeon.hw.is_dirty = GL_TRUE;                     \
 175 } while(0)
 176
 177 extern GLboolean r700SyncSurf(context_t *context,
 178                               struct radeon_bo *pbo,
 179                               uint32_t read_domain,
 180                               uint32_t write_domain,
 181                               uint32_t sync_type);
 182
 183 extern void r700WaitForIdleClean(context_t *context);
 184
 185 extern void r700Start3D(context_t *context);
 186 extern void r600InitAtoms(context_t *context);
 187 extern void r700InitDraw(GLcontext *ctx);
 188
 189 #define RADEON_D_CAPTURE 0
 190 #define RADEON_D_PLAYBACK 1
 191 #define RADEON_D_PLAYBACK_RAW 2
 192 #define RADEON_D_T 3
 193
 194 #endif                          /* __R600_CONTEXT_H__ */