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draw: corrections to allow for different cliptest cases
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r600_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
43 {
44 context_t *context = R700_CONTEXT(ctx);
45 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
46
47 struct r700_vertex_program *vp = context->selected_vp;
48
49 struct radeon_bo *bo = NULL;
50 unsigned int i;
51 BATCH_LOCALS(&context->radeon);
52
53 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
54
55 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
56 if (ctx->Texture.Unit[i]._ReallyEnabled) {
57 radeonTexObj *t = r700->textures[i];
58 if (t) {
59 if (!t->image_override) {
60 bo = t->mt->bo;
61 } else {
62 bo = t->bo;
63 }
64 if (bo) {
65
66 r700SyncSurf(context, bo,
67 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
68 0, TC_ACTION_ENA_bit);
69
70 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
71 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
72
73 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
74 { /* vs texture */
75 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
76 }
77 else
78 {
79 R600_OUT_BATCH(i * 7);
80 }
81
82 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
83 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
84 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
85 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
86 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
87 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
88 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
89 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
90 bo,
91 r700->textures[i]->SQ_TEX_RESOURCE2,
92 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
93 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
94 bo,
95 r700->textures[i]->SQ_TEX_RESOURCE3,
96 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
97 END_BATCH();
98 COMMIT_BATCH();
99 }
100 }
101 }
102 }
103 }
104
105 #define SAMPLER_STRIDE 3
106
107 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
108 {
109 context_t *context = R700_CONTEXT(ctx);
110 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
111 unsigned int i;
112
113 struct r700_vertex_program *vp = context->selected_vp;
114
115 BATCH_LOCALS(&context->radeon);
116 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
117
118 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
119 if (ctx->Texture.Unit[i]._ReallyEnabled) {
120 radeonTexObj *t = r700->textures[i];
121 if (t) {
122 BEGIN_BATCH_NO_AUTOSTATE(5);
123 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
124
125 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
126 { /* vs texture */
127 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
128 }
129 else
130 {
131 R600_OUT_BATCH(i * 3);
132 }
133
134 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
135 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
136 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
137 END_BATCH();
138 COMMIT_BATCH();
139 }
140 }
141 }
142 }
143
144 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
145 {
146 context_t *context = R700_CONTEXT(ctx);
147 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
148 unsigned int i;
149 BATCH_LOCALS(&context->radeon);
150 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
151
152 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
153 if (ctx->Texture.Unit[i]._ReallyEnabled) {
154 radeonTexObj *t = r700->textures[i];
155 if (t) {
156 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
157 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
158 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
159 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
160 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
161 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
162 END_BATCH();
163 COMMIT_BATCH();
164 }
165 }
166 }
167 }
168
169 extern int getTypeSize(GLenum type);
170 static void r700SetupVTXConstants(GLcontext * ctx,
171 void * pAos,
172 StreamDesc * pStreamDesc)
173 {
174 context_t *context = R700_CONTEXT(ctx);
175 struct radeon_aos * paos = (struct radeon_aos *)pAos;
176 BATCH_LOCALS(&context->radeon);
177
178 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
179 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
180 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
181 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
182 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
183
184 if (!paos->bo)
185 return;
186
187 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
188 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
189 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
190 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
191 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
192 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
193 else
194 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
195
196 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
197 uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
198
199 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
200 SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
201 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
202 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
203 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
204 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
205
206 if(GL_TRUE == pStreamDesc->normalize)
207 {
208 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
209 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
210 }
211 else
212 {
213 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
214 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
215 }
216
217 if(1 == pStreamDesc->_signed)
218 {
219 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
220 }
221
222 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
223 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
224 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
225
226 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
227
228 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
229 R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
230 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
231 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
232 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
233 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
234 R600_OUT_BATCH(0);
235 R600_OUT_BATCH(0);
236 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
237 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
238 paos->bo,
239 uSQ_VTX_CONSTANT_WORD0_0,
240 RADEON_GEM_DOMAIN_GTT, 0, 0);
241 END_BATCH();
242 COMMIT_BATCH();
243
244 }
245
246 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
247 {
248 context_t *context = R700_CONTEXT(ctx);
249 struct r700_vertex_program *vp = context->selected_vp;
250 unsigned int i, j = 0;
251 BATCH_LOCALS(&context->radeon);
252 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
253
254 if (context->radeon.tcl.aos_count == 0)
255 return;
256
257 for(i=0; i<VERT_ATTRIB_MAX; i++) {
258 if(vp->mesa_program->Base.InputsRead & (1 << i))
259 {
260 r700SetupVTXConstants(ctx,
261 (void*)(&context->radeon.tcl.aos[j]),
262 &(context->stream_desc[j]));
263 j++;
264 }
265 }
266 }
267
268 static void r700SetRenderTarget(context_t *context, int id)
269 {
270 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
271 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
272 struct radeon_renderbuffer *rrb;
273 unsigned int nPitchInPixel, height;
274
275 rrb = radeon_get_colorbuffer(&context->radeon);
276 if (!rrb || !rrb->bo) {
277 return;
278 }
279
280 R600_STATECHANGE(context, cb_target);
281
282 /* color buffer */
283 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
284
285 nPitchInPixel = rrb->pitch/rrb->cpp;
286
287 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
288 {
289 height = rrb->base.Height;
290 }
291 else
292 {
293 height = context->radeon.radeonScreen->driScreen->fbHeight;
294 }
295
296 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
297 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
298 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
299 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
300 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
301 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
302 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
303
304 switch (rrb->base.Format) {
305 case MESA_FORMAT_RGBA8888:
306 format = COLOR_8_8_8_8;
307 comp_swap = SWAP_STD_REV;
308 number_type = NUMBER_UNORM;
309 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
310 break;
311 case MESA_FORMAT_SIGNED_RGBA8888:
312 format = COLOR_8_8_8_8;
313 comp_swap = SWAP_STD_REV;
314 number_type = NUMBER_SNORM;
315 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
316 break;
317 case MESA_FORMAT_RGBA8888_REV:
318 format = COLOR_8_8_8_8;
319 comp_swap = SWAP_STD;
320 number_type = NUMBER_UNORM;
321 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
322 break;
323 case MESA_FORMAT_SIGNED_RGBA8888_REV:
324 format = COLOR_8_8_8_8;
325 comp_swap = SWAP_STD;
326 number_type = NUMBER_SNORM;
327 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
328 break;
329 case MESA_FORMAT_ARGB8888:
330 case MESA_FORMAT_XRGB8888:
331 format = COLOR_8_8_8_8;
332 comp_swap = SWAP_ALT;
333 number_type = NUMBER_UNORM;
334 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
335 break;
336 case MESA_FORMAT_ARGB8888_REV:
337 case MESA_FORMAT_XRGB8888_REV:
338 format = COLOR_8_8_8_8;
339 comp_swap = SWAP_ALT_REV;
340 number_type = NUMBER_UNORM;
341 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
342 break;
343 case MESA_FORMAT_RGB565:
344 format = COLOR_5_6_5;
345 comp_swap = SWAP_STD_REV;
346 number_type = NUMBER_UNORM;
347 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
348 break;
349 case MESA_FORMAT_RGB565_REV:
350 format = COLOR_5_6_5;
351 comp_swap = SWAP_STD;
352 number_type = NUMBER_UNORM;
353 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
354 break;
355 case MESA_FORMAT_ARGB4444:
356 format = COLOR_4_4_4_4;
357 comp_swap = SWAP_ALT;
358 number_type = NUMBER_UNORM;
359 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
360 break;
361 case MESA_FORMAT_ARGB4444_REV:
362 format = COLOR_4_4_4_4;
363 comp_swap = SWAP_ALT_REV;
364 number_type = NUMBER_UNORM;
365 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
366 break;
367 case MESA_FORMAT_ARGB1555:
368 format = COLOR_1_5_5_5;
369 comp_swap = SWAP_ALT;
370 number_type = NUMBER_UNORM;
371 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
372 break;
373 case MESA_FORMAT_ARGB1555_REV:
374 format = COLOR_1_5_5_5;
375 comp_swap = SWAP_ALT_REV;
376 number_type = NUMBER_UNORM;
377 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
378 break;
379 case MESA_FORMAT_AL88:
380 format = COLOR_8_8;
381 comp_swap = SWAP_STD;
382 number_type = NUMBER_UNORM;
383 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
384 break;
385 case MESA_FORMAT_AL88_REV:
386 format = COLOR_8_8;
387 comp_swap = SWAP_STD_REV;
388 number_type = NUMBER_UNORM;
389 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
390 break;
391 case MESA_FORMAT_RGB332:
392 format = COLOR_3_3_2;
393 comp_swap = SWAP_STD_REV;
394 number_type = NUMBER_UNORM;
395 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
396 break;
397 case MESA_FORMAT_A8:
398 format = COLOR_8;
399 comp_swap = SWAP_ALT_REV;
400 number_type = NUMBER_UNORM;
401 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
402 break;
403 case MESA_FORMAT_I8:
404 case MESA_FORMAT_CI8:
405 format = COLOR_8;
406 comp_swap = SWAP_STD;
407 number_type = NUMBER_UNORM;
408 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
409 break;
410 case MESA_FORMAT_L8:
411 format = COLOR_8;
412 comp_swap = SWAP_ALT;
413 number_type = NUMBER_UNORM;
414 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
415 break;
416 case MESA_FORMAT_RGBA_FLOAT32:
417 format = COLOR_32_32_32_32_FLOAT;
418 comp_swap = SWAP_STD_REV;
419 number_type = NUMBER_FLOAT;
420 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
421 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
422 break;
423 case MESA_FORMAT_RGBA_FLOAT16:
424 format = COLOR_16_16_16_16_FLOAT;
425 comp_swap = SWAP_STD_REV;
426 number_type = NUMBER_FLOAT;
427 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
428 break;
429 case MESA_FORMAT_ALPHA_FLOAT32:
430 format = COLOR_32_FLOAT;
431 comp_swap = SWAP_ALT_REV;
432 number_type = NUMBER_FLOAT;
433 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
434 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
435 break;
436 case MESA_FORMAT_ALPHA_FLOAT16:
437 format = COLOR_16_FLOAT;
438 comp_swap = SWAP_ALT_REV;
439 number_type = NUMBER_FLOAT;
440 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
441 break;
442 case MESA_FORMAT_LUMINANCE_FLOAT32:
443 format = COLOR_32_FLOAT;
444 comp_swap = SWAP_ALT;
445 number_type = NUMBER_FLOAT;
446 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
447 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
448 break;
449 case MESA_FORMAT_LUMINANCE_FLOAT16:
450 format = COLOR_16_FLOAT;
451 comp_swap = SWAP_ALT;
452 number_type = NUMBER_FLOAT;
453 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
454 break;
455 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
456 format = COLOR_32_32_FLOAT;
457 comp_swap = SWAP_ALT_REV;
458 number_type = NUMBER_FLOAT;
459 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
460 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
461 break;
462 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
463 format = COLOR_16_16_FLOAT;
464 comp_swap = SWAP_ALT_REV;
465 number_type = NUMBER_FLOAT;
466 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
467 break;
468 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
469 format = COLOR_32_FLOAT;
470 comp_swap = SWAP_STD;
471 number_type = NUMBER_FLOAT;
472 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
473 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
474 break;
475 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
476 format = COLOR_16_FLOAT;
477 comp_swap = SWAP_STD;
478 number_type = NUMBER_UNORM;
479 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
480 break;
481 case MESA_FORMAT_X8_Z24:
482 case MESA_FORMAT_S8_Z24:
483 format = COLOR_8_24;
484 comp_swap = SWAP_STD;
485 number_type = NUMBER_UNORM;
486 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
487 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
488 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
489 break;
490 case MESA_FORMAT_Z24_S8:
491 format = COLOR_24_8;
492 comp_swap = SWAP_STD;
493 number_type = NUMBER_UNORM;
494 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
495 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
496 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
497 break;
498 case MESA_FORMAT_Z16:
499 format = COLOR_16;
500 comp_swap = SWAP_STD;
501 number_type = NUMBER_UNORM;
502 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
503 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
504 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
505 break;
506 case MESA_FORMAT_Z32:
507 format = COLOR_32;
508 comp_swap = SWAP_STD;
509 number_type = NUMBER_UNORM;
510 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
511 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
512 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
513 break;
514 case MESA_FORMAT_SARGB8:
515 format = COLOR_8_8_8_8;
516 comp_swap = SWAP_ALT;
517 number_type = NUMBER_SRGB;
518 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
519 break;
520 case MESA_FORMAT_SLA8:
521 format = COLOR_8_8;
522 comp_swap = SWAP_ALT_REV;
523 number_type = NUMBER_SRGB;
524 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
525 break;
526 case MESA_FORMAT_SL8:
527 format = COLOR_8;
528 comp_swap = SWAP_ALT_REV;
529 number_type = NUMBER_SRGB;
530 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
531 break;
532 default:
533 _mesa_problem(context->radeon.glCtx, "unexpected format in r700SetRenderTarget()");
534 break;
535 }
536
537 /* must be 0 on r7xx */
538 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
539 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
540
541 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, format,
542 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
543 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, comp_swap,
544 COMP_SWAP_shift, COMP_SWAP_mask);
545 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, number_type,
546 NUMBER_TYPE_shift, NUMBER_TYPE_mask);
547 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
548
549 r700->render_target[id].enabled = GL_TRUE;
550 }
551
552 static void r700SetDepthTarget(context_t *context)
553 {
554 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
555
556 struct radeon_renderbuffer *rrb;
557 unsigned int nPitchInPixel, height;
558
559 rrb = radeon_get_depthbuffer(&context->radeon);
560 if (!rrb)
561 return;
562
563 R600_STATECHANGE(context, db_target);
564
565 /* depth buf */
566 r700->DB_DEPTH_SIZE.u32All = 0;
567 r700->DB_DEPTH_BASE.u32All = 0;
568 r700->DB_DEPTH_INFO.u32All = 0;
569 r700->DB_DEPTH_VIEW.u32All = 0;
570
571 nPitchInPixel = rrb->pitch/rrb->cpp;
572
573 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
574 {
575 height = rrb->base.Height;
576 }
577 else
578 {
579 height = context->radeon.radeonScreen->driScreen->fbHeight;
580 }
581
582 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
583 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
584 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
585 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
586
587 if(4 == rrb->cpp)
588 {
589 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
590 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
591 }
592 else
593 {
594 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
595 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
596 }
597 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
598 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
599 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
600 }
601
602 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
603 {
604 context_t *context = R700_CONTEXT(ctx);
605 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
606 struct radeon_renderbuffer *rrb;
607 BATCH_LOCALS(&context->radeon);
608 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
609
610 rrb = radeon_get_depthbuffer(&context->radeon);
611 if (!rrb || !rrb->bo) {
612 return;
613 }
614
615 r700SetDepthTarget(context);
616
617 BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
618 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
619 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
620 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
621 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
622 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
623 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
624 rrb->bo,
625 r700->DB_DEPTH_BASE.u32All,
626 0, RADEON_GEM_DOMAIN_VRAM, 0);
627 END_BATCH();
628 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
629 R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
630 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
631 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
632 rrb->bo,
633 r700->DB_DEPTH_INFO.u32All,
634 0, RADEON_GEM_DOMAIN_VRAM, 0);
635 END_BATCH();
636
637 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
638 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
639 BEGIN_BATCH_NO_AUTOSTATE(2);
640 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
641 R600_OUT_BATCH(1 << 0);
642 END_BATCH();
643 }
644
645 COMMIT_BATCH();
646
647 }
648
649 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
650 {
651 context_t *context = R700_CONTEXT(ctx);
652 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
653 struct radeon_renderbuffer *rrb;
654 BATCH_LOCALS(&context->radeon);
655 int id = 0;
656 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
657
658 rrb = radeon_get_colorbuffer(&context->radeon);
659 if (!rrb || !rrb->bo) {
660 return;
661 }
662
663 r700SetRenderTarget(context, 0);
664
665 if (id > R700_MAX_RENDER_TARGETS)
666 return;
667
668 if (!r700->render_target[id].enabled)
669 return;
670
671 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
672 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
673 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
674 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
675 rrb->bo,
676 r700->render_target[id].CB_COLOR0_BASE.u32All,
677 0, RADEON_GEM_DOMAIN_VRAM, 0);
678 END_BATCH();
679
680 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
681 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
682 BEGIN_BATCH_NO_AUTOSTATE(2);
683 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
684 R600_OUT_BATCH((2 << id));
685 END_BATCH();
686 }
687 /* Set CMASK & TILE buffer to the offset of color buffer as
688 * we don't use those this shouldn't cause any issue and we
689 * then have a valid cmd stream
690 */
691 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
692 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
693 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
694 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
695 rrb->bo,
696 r700->render_target[id].CB_COLOR0_TILE.u32All,
697 0, RADEON_GEM_DOMAIN_VRAM, 0);
698 END_BATCH();
699 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
700 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
701 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
702 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All,
703 rrb->bo,
704 r700->render_target[id].CB_COLOR0_FRAG.u32All,
705 0, RADEON_GEM_DOMAIN_VRAM, 0);
706 END_BATCH();
707
708 BEGIN_BATCH_NO_AUTOSTATE(9);
709 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
710 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
711 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
712 END_BATCH();
713
714 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
715 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
716 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All,
717 rrb->bo,
718 r700->render_target[id].CB_COLOR0_INFO.u32All,
719 0, RADEON_GEM_DOMAIN_VRAM, 0);
720
721 END_BATCH();
722
723 COMMIT_BATCH();
724
725 }
726
727 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
728 {
729 context_t *context = R700_CONTEXT(ctx);
730 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
731 struct radeon_bo * pbo;
732 struct radeon_bo * pbo_const;
733 BATCH_LOCALS(&context->radeon);
734 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
735
736 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
737
738 if (!pbo)
739 return;
740
741 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
742
743 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
744 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
745 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
746 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
747 pbo,
748 r700->ps.SQ_PGM_START_PS.u32All,
749 RADEON_GEM_DOMAIN_GTT, 0, 0);
750 END_BATCH();
751
752 BEGIN_BATCH_NO_AUTOSTATE(9);
753 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
754 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
755 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
756 END_BATCH();
757
758 BEGIN_BATCH_NO_AUTOSTATE(3);
759 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
760 END_BATCH();
761
762 pbo_const = (struct radeon_bo *)r700GetActiveFpShaderConstBo(GL_CONTEXT(context));
763 //TODO : set up shader const
764
765 COMMIT_BATCH();
766
767 }
768
769 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
770 {
771 context_t *context = R700_CONTEXT(ctx);
772 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
773 struct radeon_bo * pbo;
774 struct radeon_bo * pbo_const;
775 BATCH_LOCALS(&context->radeon);
776 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
777
778 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
779
780 if (!pbo)
781 return;
782
783 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
784
785 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
786 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
787 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
788 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
789 pbo,
790 r700->vs.SQ_PGM_START_VS.u32All,
791 RADEON_GEM_DOMAIN_GTT, 0, 0);
792 END_BATCH();
793
794 BEGIN_BATCH_NO_AUTOSTATE(6);
795 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
796 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
797 END_BATCH();
798
799 BEGIN_BATCH_NO_AUTOSTATE(3);
800 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
801 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
802 END_BATCH();
803
804 /* TODO : handle 4 bufs */
805 if(GL_TRUE == r700->bShaderUseMemConstant)
806 {
807 pbo_const = (struct radeon_bo *)r700GetActiveVpShaderConstBo(GL_CONTEXT(context));
808 if(NULL != pbo_const)
809 {
810 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); /* TODO : Check kc bit. */
811
812 BEGIN_BATCH_NO_AUTOSTATE(3);
813 R600_OUT_BATCH_REGVAL(SQ_ALU_CONST_BUFFER_SIZE_VS_0, (r700->vs.num_consts * 4)/16 );
814 END_BATCH();
815
816 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
817 R600_OUT_BATCH_REGSEQ(SQ_ALU_CONST_CACHE_VS_0, 1);
818 R600_OUT_BATCH(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All);
819 R600_OUT_BATCH_RELOC(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
820 pbo_const,
821 r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
822 RADEON_GEM_DOMAIN_GTT, 0, 0);
823 END_BATCH();
824 }
825 }
826
827 COMMIT_BATCH();
828 }
829
830 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
831 {
832 context_t *context = R700_CONTEXT(ctx);
833 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
834 struct radeon_bo * pbo;
835 BATCH_LOCALS(&context->radeon);
836 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
837
838 /* XXX fixme
839 * R6xx chips require a FS be emitted, even if it's not used.
840 * since we aren't using FS yet, just send the VS address to make
841 * the kernel command checker happy
842 */
843 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
844 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
845 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
846 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
847 /* XXX */
848
849 if (!pbo)
850 return;
851
852 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
853
854 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
855 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
856 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
857 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
858 pbo,
859 r700->fs.SQ_PGM_START_FS.u32All,
860 RADEON_GEM_DOMAIN_GTT, 0, 0);
861 END_BATCH();
862
863 BEGIN_BATCH_NO_AUTOSTATE(6);
864 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
865 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
866 END_BATCH();
867
868 COMMIT_BATCH();
869
870 }
871
872 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
873 {
874 context_t *context = R700_CONTEXT(ctx);
875 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
876 BATCH_LOCALS(&context->radeon);
877 int id = 0;
878 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
879
880 if (id > R700_MAX_VIEWPORTS)
881 return;
882
883 if (!r700->viewport[id].enabled)
884 return;
885
886 BEGIN_BATCH_NO_AUTOSTATE(16);
887 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
888 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
889 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
890 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
891 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
892 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
893 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
894 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
895 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
896 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
897 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
898 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
899 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
900 END_BATCH();
901
902 COMMIT_BATCH();
903
904 }
905
906 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
907 {
908 context_t *context = R700_CONTEXT(ctx);
909 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
910 BATCH_LOCALS(&context->radeon);
911 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
912
913 BEGIN_BATCH_NO_AUTOSTATE(34);
914 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
915 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
916 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
917 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
918 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
919 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
920 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
921
922 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
923 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
924 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
925 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
926 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
927
928 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
929 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
930 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
931 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
932 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
933 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
934 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
935 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
936 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
937 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
938 END_BATCH();
939
940 COMMIT_BATCH();
941 }
942
943 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
944 {
945 context_t *context = R700_CONTEXT(ctx);
946 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
947 BATCH_LOCALS(&context->radeon);
948 int i;
949 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
950
951 for (i = 0; i < R700_MAX_UCP; i++) {
952 if (r700->ucp[i].enabled) {
953 BEGIN_BATCH_NO_AUTOSTATE(6);
954 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
955 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
956 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
957 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
958 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
959 END_BATCH();
960 COMMIT_BATCH();
961 }
962 }
963 }
964
965 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
966 {
967 context_t *context = R700_CONTEXT(ctx);
968 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
969 BATCH_LOCALS(&context->radeon);
970 unsigned int ui;
971 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
972
973 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
974
975 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
976 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
977 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
978 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
979 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
980 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
981 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
982 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
983 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
984 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
985 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
986 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
987 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
988 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
989 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
990 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
991 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
992 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
993 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
994 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
995 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
996 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
997 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
998 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
999 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
1000 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
1001 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
1002 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
1003 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
1004 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
1005 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
1006 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
1007 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
1008
1009 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
1010 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
1011 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
1012 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
1013 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
1014 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
1015 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
1016 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
1017 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
1018 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
1019 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
1020
1021 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
1022 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
1023 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
1024 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
1025 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
1026 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
1027 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
1028 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
1029 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
1030 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
1031
1032 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
1033 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
1034 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
1035
1036 END_BATCH();
1037 COMMIT_BATCH();
1038 }
1039
1040 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
1041 {
1042 context_t *context = R700_CONTEXT(ctx);
1043 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1044 BATCH_LOCALS(&context->radeon);
1045 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1046
1047 BEGIN_BATCH_NO_AUTOSTATE(41);
1048
1049 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1050 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
1051 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
1052 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
1053 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
1054
1055 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1056 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
1057 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
1058 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
1059 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
1060 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
1061 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
1062 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
1063 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
1064 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
1065 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
1066 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
1067 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
1068 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
1069
1070 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
1071 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
1072 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
1073 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
1074
1075 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1076 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
1077 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
1078 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
1079
1080 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
1081
1082 END_BATCH();
1083 COMMIT_BATCH();
1084 }
1085
1086 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
1087 {
1088 context_t *context = R700_CONTEXT(ctx);
1089 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1090 BATCH_LOCALS(&context->radeon);
1091 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1092
1093 BEGIN_BATCH_NO_AUTOSTATE(9);
1094 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
1095 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
1096 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
1097 END_BATCH();
1098 COMMIT_BATCH();
1099 }
1100
1101 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
1102 {
1103 context_t *context = R700_CONTEXT(ctx);
1104 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1105 BATCH_LOCALS(&context->radeon);
1106 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1107
1108 BEGIN_BATCH_NO_AUTOSTATE(17);
1109
1110 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
1111 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
1112 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
1113
1114 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
1115 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
1116
1117 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
1118 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
1119 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
1120
1121 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
1122
1123 END_BATCH();
1124 COMMIT_BATCH();
1125 }
1126
1127 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
1128 {
1129 context_t *context = R700_CONTEXT(ctx);
1130 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1131 BATCH_LOCALS(&context->radeon);
1132
1133 BEGIN_BATCH_NO_AUTOSTATE(4);
1134 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1135 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
1136 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
1137 END_BATCH();
1138 COMMIT_BATCH();
1139 }
1140
1141 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
1142 {
1143 context_t *context = R700_CONTEXT(ctx);
1144 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1145 BATCH_LOCALS(&context->radeon);
1146 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1147
1148 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1149 BEGIN_BATCH_NO_AUTOSTATE(11);
1150 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
1151 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
1152 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
1153 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
1154 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
1155 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
1156 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
1157 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
1158 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
1159 END_BATCH();
1160 }
1161
1162 BEGIN_BATCH_NO_AUTOSTATE(7);
1163 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
1164 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
1165 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
1166 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
1167 END_BATCH();
1168 COMMIT_BATCH();
1169 }
1170
1171 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
1172 {
1173 context_t *context = R700_CONTEXT(ctx);
1174 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1175 BATCH_LOCALS(&context->radeon);
1176
1177 BEGIN_BATCH_NO_AUTOSTATE(6);
1178 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
1179 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
1180 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
1181 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
1182 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
1183 END_BATCH();
1184 COMMIT_BATCH();
1185 }
1186
1187 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
1188 {
1189 context_t *context = R700_CONTEXT(ctx);
1190 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1191 BATCH_LOCALS(&context->radeon);
1192 unsigned int ui;
1193 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1194
1195 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1196 BEGIN_BATCH_NO_AUTOSTATE(3);
1197 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
1198 END_BATCH();
1199 }
1200
1201 BEGIN_BATCH_NO_AUTOSTATE(3);
1202 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
1203 END_BATCH();
1204
1205 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1206 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
1207 if (r700->render_target[ui].enabled) {
1208 BEGIN_BATCH_NO_AUTOSTATE(3);
1209 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
1210 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
1211 END_BATCH();
1212 }
1213 }
1214 }
1215
1216 COMMIT_BATCH();
1217 }
1218
1219 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
1220 {
1221 context_t *context = R700_CONTEXT(ctx);
1222 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1223 BATCH_LOCALS(&context->radeon);
1224 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1225
1226 BEGIN_BATCH_NO_AUTOSTATE(6);
1227 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
1228 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
1229 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
1230 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
1231 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
1232 END_BATCH();
1233 COMMIT_BATCH();
1234 }
1235
1236 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
1237 {
1238 context_t *context = R700_CONTEXT(ctx);
1239 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1240 BATCH_LOCALS(&context->radeon);
1241
1242 BEGIN_BATCH_NO_AUTOSTATE(9);
1243 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
1244 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
1245 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
1246 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
1247 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
1248 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
1249 END_BATCH();
1250 COMMIT_BATCH();
1251
1252 }
1253
1254 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
1255 {
1256 context_t *context = R700_CONTEXT(ctx);
1257 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1258 BATCH_LOCALS(&context->radeon);
1259
1260 BEGIN_BATCH_NO_AUTOSTATE(10);
1261 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
1262 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
1263 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
1264 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1265 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
1266 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
1267 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
1268 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
1269 END_BATCH();
1270 COMMIT_BATCH();
1271
1272 }
1273
1274 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
1275 {
1276 context_t *context = R700_CONTEXT(ctx);
1277 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1278 BATCH_LOCALS(&context->radeon);
1279 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1280
1281 BEGIN_BATCH_NO_AUTOSTATE(12);
1282 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
1283 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
1284 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
1285 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
1286 END_BATCH();
1287 COMMIT_BATCH();
1288 }
1289
1290 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
1291 {
1292 context_t *context = R700_CONTEXT(ctx);
1293 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1294 BATCH_LOCALS(&context->radeon);
1295
1296 BEGIN_BATCH_NO_AUTOSTATE(6);
1297 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
1298 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
1299 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
1300 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
1301 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
1302 END_BATCH();
1303 COMMIT_BATCH();
1304 }
1305
1306 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
1307 {
1308 context_t *context = R700_CONTEXT(ctx);
1309 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1310 BATCH_LOCALS(&context->radeon);
1311 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1312
1313 BEGIN_BATCH_NO_AUTOSTATE(22);
1314 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1315 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1316 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1317
1318 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1319 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1320 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1321 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1322 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1323 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1324 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1325 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1326 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1327 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1328 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1329 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1330 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1331
1332 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1333 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1334 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1335 END_BATCH();
1336 COMMIT_BATCH();
1337 }
1338
1339 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
1340 {
1341 context_t *context = R700_CONTEXT(ctx);
1342 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1343 BATCH_LOCALS(&context->radeon);
1344 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1345
1346 BEGIN_BATCH_NO_AUTOSTATE(15);
1347 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1348 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1349 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1350 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1351 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1352 END_BATCH();
1353 COMMIT_BATCH();
1354 }
1355
1356 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
1357 {
1358 context_t *context = R700_CONTEXT(ctx);
1359 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1360 BATCH_LOCALS(&context->radeon);
1361
1362 BEGIN_BATCH_NO_AUTOSTATE(12);
1363 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1364 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1365 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1366 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1367 END_BATCH();
1368 COMMIT_BATCH();
1369 }
1370
1371 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1372 {
1373 context_t *context = R700_CONTEXT(ctx);
1374 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1375 int i;
1376 BATCH_LOCALS(&context->radeon);
1377
1378 if (r700->ps.num_consts == 0)
1379 return;
1380
1381 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1382 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1383 /* assembler map const from very beginning. */
1384 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1385 for (i = 0; i < r700->ps.num_consts; i++) {
1386 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1387 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1388 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1389 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1390 }
1391 END_BATCH();
1392 COMMIT_BATCH();
1393 }
1394
1395 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1396 {
1397 context_t *context = R700_CONTEXT(ctx);
1398 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1399 int i;
1400 BATCH_LOCALS(&context->radeon);
1401 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1402
1403 if (r700->vs.num_consts == 0)
1404 return;
1405
1406 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1407 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1408 /* assembler map const from very beginning. */
1409 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1410 for (i = 0; i < r700->vs.num_consts; i++) {
1411 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1412 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1413 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1414 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1415 }
1416 END_BATCH();
1417 COMMIT_BATCH();
1418 }
1419
1420 static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
1421 {
1422 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1423 struct radeon_query_object *query = radeon->query.current;
1424 BATCH_LOCALS(radeon);
1425 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1426
1427 /* clear the buffer */
1428 radeon_bo_map(query->bo, GL_FALSE);
1429 memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1430 radeon_bo_unmap(query->bo);
1431
1432 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1433 query->bo,
1434 0, RADEON_GEM_DOMAIN_GTT);
1435
1436 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1437 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1438 R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
1439 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1440 R600_OUT_BATCH(0x00000000);
1441 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1442 END_BATCH();
1443 query->emitted_begin = GL_TRUE;
1444 }
1445
1446 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1447 {
1448 return atom->cmd_size;
1449 }
1450
1451 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1452 {
1453 context_t *context = R700_CONTEXT(ctx);
1454 int count = 7;
1455
1456 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1457 count += 11;
1458 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1459
1460 return count;
1461 }
1462
1463 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1464 {
1465 context_t *context = R700_CONTEXT(ctx);
1466 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1467 unsigned int ui;
1468 int count = 3;
1469
1470 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1471 count += 3;
1472
1473 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1474 /* targets are enabled in r700SetRenderTarget but state
1475 size is calculated before that. Until MRT's are done
1476 hardcode target0 as enabled. */
1477 count += 3;
1478 for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
1479 if (r700->render_target[ui].enabled)
1480 count += 3;
1481 }
1482 }
1483 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1484
1485 return count;
1486 }
1487
1488 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1489 {
1490 context_t *context = R700_CONTEXT(ctx);
1491 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1492 int i;
1493 int count = 0;
1494
1495 for (i = 0; i < R700_MAX_UCP; i++) {
1496 if (r700->ucp[i].enabled)
1497 count += 6;
1498 }
1499 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1500 return count;
1501 }
1502
1503 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1504 {
1505 context_t *context = R700_CONTEXT(ctx);
1506 int count = context->radeon.tcl.aos_count * 18;
1507
1508 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1509 return count;
1510 }
1511
1512 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1513 {
1514 context_t *context = R700_CONTEXT(ctx);
1515 unsigned int i, count = 0;
1516 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1517
1518 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1519 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1520 radeonTexObj *t = r700->textures[i];
1521 if (t)
1522 count++;
1523 }
1524 }
1525 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1526 return count * 31;
1527 }
1528
1529 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1530 {
1531 context_t *context = R700_CONTEXT(ctx);
1532 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1533 int count = r700->ps.num_consts * 4;
1534
1535 if (count)
1536 count += 2;
1537 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1538
1539 return count;
1540 }
1541
1542 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1543 {
1544 context_t *context = R700_CONTEXT(ctx);
1545 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1546 int count = r700->vs.num_consts * 4;
1547
1548 if (count)
1549 count += 2;
1550 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1551
1552 return count;
1553 }
1554
1555 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
1556 {
1557 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1558 struct radeon_query_object *query = radeon->query.current;
1559 int count;
1560
1561 if (!query || query->emitted_begin)
1562 count = 0;
1563 else
1564 count = atom->cmd_size;
1565 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1566 return count;
1567 }
1568
1569 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1570 do { \
1571 context->atoms.ATOM.cmd_size = (SZ); \
1572 context->atoms.ATOM.cmd = NULL; \
1573 context->atoms.ATOM.name = #ATOM; \
1574 context->atoms.ATOM.idx = 0; \
1575 context->atoms.ATOM.check = check_##CHK; \
1576 context->atoms.ATOM.dirty = GL_FALSE; \
1577 context->atoms.ATOM.emit = (EMIT); \
1578 context->radeon.hw.max_state_size += (SZ); \
1579 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1580 } while (0)
1581
1582 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1583 {
1584 radeon->query.queryobj.cmd_size = (SZ);
1585 radeon->query.queryobj.cmd = NULL;
1586 radeon->query.queryobj.name = "queryobj";
1587 radeon->query.queryobj.idx = 0;
1588 radeon->query.queryobj.check = check_queryobj;
1589 radeon->query.queryobj.dirty = GL_FALSE;
1590 radeon->query.queryobj.emit = r700SendQueryBegin;
1591 radeon->hw.max_state_size += (SZ);
1592 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1593 }
1594
1595 void r600InitAtoms(context_t *context)
1596 {
1597 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1598 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1599 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1600
1601 /* Setup the atom linked list */
1602 make_empty_list(&context->radeon.hw.atomlist);
1603 context->radeon.hw.atomlist.name = "atom-list";
1604
1605 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1606 ALLOC_STATE(db, always, 17, r700SendDBState);
1607 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1608 ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
1609 ALLOC_STATE(sc, always, 15, r700SendSCState);
1610 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1611 ALLOC_STATE(aa, always, 12, r700SendAAState);
1612 ALLOC_STATE(cl, always, 12, r700SendCLState);
1613 ALLOC_STATE(gb, always, 6, r700SendGBState);
1614 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1615 ALLOC_STATE(su, always, 9, r700SendSUState);
1616 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1617 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1618 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1619 ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
1620 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1621 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1622 ALLOC_STATE(sx, always, 9, r700SendSXState);
1623 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1624 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1625 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1626 ALLOC_STATE(fs, always, 18, r700SendFSState);
1627 if(GL_TRUE == r700->bShaderUseMemConstant)
1628 {
1629 ALLOC_STATE(vs, always, 36, r700SendVSState);
1630 ALLOC_STATE(ps, always, 24, r700SendPSState); /* TODO : not imp yet, fix later. */
1631 }
1632 else
1633 {
1634 ALLOC_STATE(vs, always, 21, r700SendVSState);
1635 ALLOC_STATE(ps, always, 24, r700SendPSState);
1636 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1637 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1638 }
1639
1640 ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
1641 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1642 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1643 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1644 r600_init_query_stateobj(&context->radeon, 6 * 2);
1645
1646 context->radeon.hw.is_dirty = GL_TRUE;
1647 context->radeon.hw.all_dirty = GL_TRUE;
1648 }