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Merge branch 'gallium-no-rhw-position'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_render.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/glheader.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36 #include "main/api_arrayelt.h"
37 #include "swrast/swrast.h"
38 #include "swrast_setup/swrast_setup.h"
39 #include "vbo/vbo.h"
40
41 #include "tnl/tnl.h"
42 #include "tnl/t_vp_build.h"
43 #include "tnl/t_context.h"
44 #include "tnl/t_vertex.h"
45 #include "vbo/vbo_context.h"
46
47 #include "r600_context.h"
48 #include "r600_cmdbuf.h"
49
50 #include "r600_tex.h"
51
52 #include "r700_vertprog.h"
53 #include "r700_fragprog.h"
54 #include "r700_state.h"
55
56 #include "radeon_buffer_objects.h"
57 #include "radeon_common_context.h"
58
59 void r700WaitForIdle(context_t *context);
60 void r700WaitForIdleClean(context_t *context);
61 static unsigned int r700PrimitiveType(int prim);
62 GLboolean r700SyncSurf(context_t *context,
63 struct radeon_bo *pbo,
64 uint32_t read_domain,
65 uint32_t write_domain,
66 uint32_t sync_type);
67
68 void r700WaitForIdle(context_t *context)
69 {
70 BATCH_LOCALS(&context->radeon);
71 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
72 BEGIN_BATCH_NO_AUTOSTATE(3);
73
74 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
75 R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
76 R600_OUT_BATCH(WAIT_3D_IDLE_bit);
77
78 END_BATCH();
79 COMMIT_BATCH();
80 }
81
82 void r700WaitForIdleClean(context_t *context)
83 {
84 BATCH_LOCALS(&context->radeon);
85 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
86 BEGIN_BATCH_NO_AUTOSTATE(5);
87
88 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
89 R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
90
91 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
92 R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
93 R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
94
95 END_BATCH();
96 COMMIT_BATCH();
97 }
98
99 void r700Start3D(context_t *context)
100 {
101 BATCH_LOCALS(&context->radeon);
102 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
103 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
104 {
105 BEGIN_BATCH_NO_AUTOSTATE(2);
106 R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0));
107 R600_OUT_BATCH(0);
108 END_BATCH();
109 }
110
111 BEGIN_BATCH_NO_AUTOSTATE(3);
112 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
113 R600_OUT_BATCH(0x80000000);
114 R600_OUT_BATCH(0x80000000);
115 END_BATCH();
116
117 COMMIT_BATCH();
118 }
119
120 GLboolean r700SyncSurf(context_t *context,
121 struct radeon_bo *pbo,
122 uint32_t read_domain,
123 uint32_t write_domain,
124 uint32_t sync_type)
125 {
126 BATCH_LOCALS(&context->radeon);
127 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
128 uint32_t cp_coher_size;
129
130 if (!pbo)
131 return GL_FALSE;
132
133 if (pbo->size == 0xffffffff)
134 cp_coher_size = 0xffffffff;
135 else
136 cp_coher_size = ((pbo->size + 255) >> 8);
137
138 BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
139 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
140 R600_OUT_BATCH(sync_type);
141 R600_OUT_BATCH(cp_coher_size);
142 R600_OUT_BATCH(0);
143 R600_OUT_BATCH(10);
144 R600_OUT_BATCH_RELOC(0,
145 pbo,
146 0,
147 read_domain, write_domain, 0);
148 END_BATCH();
149 COMMIT_BATCH();
150
151 return GL_TRUE;
152 }
153
154 static unsigned int r700PrimitiveType(int prim)
155 {
156 switch (prim & PRIM_MODE_MASK)
157 {
158 case GL_POINTS:
159 return DI_PT_POINTLIST;
160 break;
161 case GL_LINES:
162 return DI_PT_LINELIST;
163 break;
164 case GL_LINE_STRIP:
165 return DI_PT_LINESTRIP;
166 break;
167 case GL_LINE_LOOP:
168 return DI_PT_LINELOOP;
169 break;
170 case GL_TRIANGLES:
171 return DI_PT_TRILIST;
172 break;
173 case GL_TRIANGLE_STRIP:
174 return DI_PT_TRISTRIP;
175 break;
176 case GL_TRIANGLE_FAN:
177 return DI_PT_TRIFAN;
178 break;
179 case GL_QUADS:
180 return DI_PT_QUADLIST;
181 break;
182 case GL_QUAD_STRIP:
183 return DI_PT_QUADSTRIP;
184 break;
185 case GL_POLYGON:
186 return DI_PT_POLYGON;
187 break;
188 default:
189 assert(0);
190 return -1;
191 break;
192 }
193 }
194
195 static int r700NumVerts(int num_verts, int prim)
196 {
197 int verts_off = 0;
198
199 switch (prim & PRIM_MODE_MASK) {
200 case GL_POINTS:
201 verts_off = 0;
202 break;
203 case GL_LINES:
204 verts_off = num_verts % 2;
205 break;
206 case GL_LINE_STRIP:
207 if (num_verts < 2)
208 verts_off = num_verts;
209 break;
210 case GL_LINE_LOOP:
211 if (num_verts < 2)
212 verts_off = num_verts;
213 break;
214 case GL_TRIANGLES:
215 verts_off = num_verts % 3;
216 break;
217 case GL_TRIANGLE_STRIP:
218 if (num_verts < 3)
219 verts_off = num_verts;
220 break;
221 case GL_TRIANGLE_FAN:
222 if (num_verts < 3)
223 verts_off = num_verts;
224 break;
225 case GL_QUADS:
226 verts_off = num_verts % 4;
227 break;
228 case GL_QUAD_STRIP:
229 if (num_verts < 4)
230 verts_off = num_verts;
231 else
232 verts_off = num_verts % 2;
233 break;
234 case GL_POLYGON:
235 if (num_verts < 3)
236 verts_off = num_verts;
237 break;
238 default:
239 assert(0);
240 return -1;
241 break;
242 }
243
244 return num_verts - verts_off;
245 }
246
247 static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
248 {
249 context_t *context = R700_CONTEXT(ctx);
250 BATCH_LOCALS(&context->radeon);
251 int type, total_emit;
252 int num_indices;
253 uint32_t vgt_draw_initiator = 0;
254 uint32_t vgt_index_type = 0;
255 uint32_t vgt_primitive_type = 0;
256 uint32_t vgt_num_indices = 0;
257
258 type = r700PrimitiveType(prim);
259 num_indices = r700NumVerts(end - start, prim);
260
261 radeon_print(RADEON_RENDER, RADEON_TRACE,
262 "%s type %x num_indices %d\n",
263 __func__, type, num_indices);
264
265 if (type < 0 || num_indices <= 0)
266 return;
267
268 SETfield(vgt_primitive_type, type,
269 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
270
271 SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
272
273 if(GL_TRUE != context->ind_buf.is_32bit)
274 {
275 SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
276 }
277
278 vgt_num_indices = num_indices;
279 SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
280 SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
281
282 total_emit = 3 /* VGT_PRIMITIVE_TYPE */
283 + 2 /* VGT_INDEX_TYPE */
284 + 2 /* NUM_INSTANCES */
285 + 5 + 2; /* DRAW_INDEX */
286
287 BEGIN_BATCH_NO_AUTOSTATE(total_emit);
288 // prim
289 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
290 R600_OUT_BATCH(vgt_primitive_type);
291 // index type
292 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
293 R600_OUT_BATCH(vgt_index_type);
294 // num instances
295 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
296 R600_OUT_BATCH(1);
297 // draw packet
298 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
299 R600_OUT_BATCH(context->ind_buf.bo_offset);
300 R600_OUT_BATCH(0);
301 R600_OUT_BATCH(vgt_num_indices);
302 R600_OUT_BATCH(vgt_draw_initiator);
303 R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
304 context->ind_buf.bo,
305 context->ind_buf.bo_offset,
306 RADEON_GEM_DOMAIN_GTT, 0, 0);
307 END_BATCH();
308 COMMIT_BATCH();
309 }
310
311 static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end, int prim)
312 {
313 context_t *context = R700_CONTEXT(ctx);
314 BATCH_LOCALS(&context->radeon);
315 int type, i;
316 uint32_t num_indices, total_emit = 0;
317 uint32_t vgt_draw_initiator = 0;
318 uint32_t vgt_index_type = 0;
319 uint32_t vgt_primitive_type = 0;
320 uint32_t vgt_num_indices = 0;
321
322 type = r700PrimitiveType(prim);
323 num_indices = r700NumVerts(end - start, prim);
324
325 radeon_print(RADEON_RENDER, RADEON_TRACE,
326 "%s type %x num_indices %d\n",
327 __func__, type, num_indices);
328
329 if (type < 0 || num_indices <= 0)
330 return;
331
332 SETfield(vgt_primitive_type, type,
333 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
334
335 if (num_indices > 0xffff)
336 {
337 SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
338 }
339 else
340 {
341 SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
342 }
343
344 vgt_num_indices = num_indices;
345 SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
346
347 if (start == 0)
348 {
349 SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
350 }
351 else
352 {
353 if (num_indices > 0xffff)
354 {
355 total_emit += num_indices;
356 }
357 else
358 {
359 total_emit += (num_indices + 1) / 2;
360 }
361 SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
362 }
363
364 total_emit += 3 /* VGT_PRIMITIVE_TYPE */
365 + 2 /* VGT_INDEX_TYPE */
366 + 2 /* NUM_INSTANCES */
367 + 3; /* DRAW */
368
369 BEGIN_BATCH_NO_AUTOSTATE(total_emit);
370 // prim
371 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
372 R600_OUT_BATCH(vgt_primitive_type);
373 // index type
374 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
375 R600_OUT_BATCH(vgt_index_type);
376 // num instances
377 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
378 R600_OUT_BATCH(1);
379 // draw packet
380 if(start == 0)
381 {
382 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
383 R600_OUT_BATCH(vgt_num_indices);
384 R600_OUT_BATCH(vgt_draw_initiator);
385 }
386 else
387 {
388 if (num_indices > 0xffff)
389 {
390 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
391 R600_OUT_BATCH(vgt_num_indices);
392 R600_OUT_BATCH(vgt_draw_initiator);
393 for (i = start; i < (start + num_indices); i++)
394 {
395 R600_OUT_BATCH(i);
396 }
397 }
398 else
399 {
400 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)));
401 R600_OUT_BATCH(vgt_num_indices);
402 R600_OUT_BATCH(vgt_draw_initiator);
403 for (i = start; i < (start + num_indices); i += 2)
404 {
405 if ((i + 1) == (start + num_indices))
406 {
407 R600_OUT_BATCH(i);
408 }
409 else
410 {
411 R600_OUT_BATCH(((i + 1) << 16) | (i));
412 }
413 }
414 }
415 }
416
417 END_BATCH();
418 COMMIT_BATCH();
419 }
420
421 /* start 3d, idle, cb/db flush */
422 #define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
423
424 static GLuint r700PredictRenderSize(GLcontext* ctx,
425 const struct _mesa_prim *prim,
426 const struct _mesa_index_buffer *ib,
427 GLuint nr_prims)
428 {
429 context_t *context = R700_CONTEXT(ctx);
430 GLboolean flushed;
431 GLuint dwords, i;
432 GLuint state_size;
433
434 dwords = PRE_EMIT_STATE_BUFSZ;
435 if (ib)
436 dwords += nr_prims * 14;
437 else {
438 for (i = 0; i < nr_prims; ++i)
439 {
440 if (prim[i].start == 0)
441 dwords += 10;
442 else if (prim[i].count > 0xffff)
443 dwords += prim[i].count + 10;
444 else
445 dwords += ((prim[i].count + 1) / 2) + 10;
446 }
447 }
448
449 state_size = radeonCountStateEmitSize(&context->radeon);
450 flushed = rcommonEnsureCmdBufSpace(&context->radeon,
451 dwords + state_size,
452 __FUNCTION__);
453 if (flushed)
454 dwords += radeonCountStateEmitSize(&context->radeon);
455 else
456 dwords += state_size;
457
458 radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
459 return dwords;
460
461 }
462
463 #define CONVERT( TYPE, MACRO ) do { \
464 GLuint i, j, sz; \
465 sz = input->Size; \
466 if (input->Normalized) { \
467 for (i = 0; i < count; i++) { \
468 const TYPE *in = (TYPE *)src_ptr; \
469 for (j = 0; j < sz; j++) { \
470 *dst_ptr++ = MACRO(*in); \
471 in++; \
472 } \
473 src_ptr += stride; \
474 } \
475 } else { \
476 for (i = 0; i < count; i++) { \
477 const TYPE *in = (TYPE *)src_ptr; \
478 for (j = 0; j < sz; j++) { \
479 *dst_ptr++ = (GLfloat)(*in); \
480 in++; \
481 } \
482 src_ptr += stride; \
483 } \
484 } \
485 } while (0)
486
487 /**
488 * Convert attribute data type to float
489 * If the attribute uses named buffer object replace the bo with newly allocated bo
490 */
491 static void r700ConvertAttrib(GLcontext *ctx, int count,
492 const struct gl_client_array *input,
493 struct StreamDesc *attr)
494 {
495 context_t *context = R700_CONTEXT(ctx);
496 const GLvoid *src_ptr;
497 GLboolean mapped_named_bo = GL_FALSE;
498 GLfloat *dst_ptr;
499 GLuint stride;
500
501 stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
502
503 /* Convert value for first element only */
504 if (input->StrideB == 0)
505 {
506 count = 1;
507 }
508
509 if (input->BufferObj->Name)
510 {
511 if (!input->BufferObj->Pointer)
512 {
513 ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj);
514 mapped_named_bo = GL_TRUE;
515 }
516
517 src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
518 }
519 else
520 {
521 src_ptr = input->Ptr;
522 }
523
524 radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset,
525 sizeof(GLfloat) * input->Size * count, 32);
526
527 radeon_bo_map(attr->bo, 1);
528
529 dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
530
531 assert(src_ptr != NULL);
532
533 switch (input->Type)
534 {
535 case GL_DOUBLE:
536 CONVERT(GLdouble, (GLfloat));
537 break;
538 case GL_UNSIGNED_INT:
539 CONVERT(GLuint, UINT_TO_FLOAT);
540 break;
541 case GL_INT:
542 CONVERT(GLint, INT_TO_FLOAT);
543 break;
544 case GL_UNSIGNED_SHORT:
545 CONVERT(GLushort, USHORT_TO_FLOAT);
546 break;
547 case GL_SHORT:
548 CONVERT(GLshort, SHORT_TO_FLOAT);
549 break;
550 case GL_UNSIGNED_BYTE:
551 assert(input->Format != GL_BGRA);
552 CONVERT(GLubyte, UBYTE_TO_FLOAT);
553 break;
554 case GL_BYTE:
555 CONVERT(GLbyte, BYTE_TO_FLOAT);
556 break;
557 default:
558 assert(0);
559 break;
560 }
561
562 radeon_bo_unmap(attr->bo);
563
564 if (mapped_named_bo)
565 {
566 ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj);
567 }
568 }
569
570 static void r700AlignDataToDword(GLcontext *ctx,
571 const struct gl_client_array *input,
572 int count,
573 struct StreamDesc *attr)
574 {
575 context_t *context = R700_CONTEXT(ctx);
576 const int dst_stride = (input->StrideB + 3) & ~3;
577 const int size = getTypeSize(input->Type) * input->Size * count;
578 GLboolean mapped_named_bo = GL_FALSE;
579
580 radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32);
581
582 radeon_bo_map(attr->bo, 1);
583
584 if (!input->BufferObj->Pointer)
585 {
586 ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj);
587 mapped_named_bo = GL_TRUE;
588 }
589
590 {
591 GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
592 GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
593 int i;
594
595 for (i = 0; i < count; ++i)
596 {
597 memcpy(dst_ptr, src_ptr, input->StrideB);
598 src_ptr += input->StrideB;
599 dst_ptr += dst_stride;
600 }
601 }
602
603 radeon_bo_unmap(attr->bo);
604 if (mapped_named_bo)
605 {
606 ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj);
607 }
608
609 attr->stride = dst_stride;
610 }
611
612 static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input[], int count)
613 {
614 context_t *context = R700_CONTEXT(ctx);
615 GLuint stride;
616 int ret;
617 int i, index;
618
619 R600_STATECHANGE(context, vtx);
620
621 for(index = 0; index < context->nNumActiveAos; index++)
622 {
623 struct radeon_aos *aos = &context->radeon.tcl.aos[index];
624 i = context->stream_desc[index].element;
625
626 stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
627
628 if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT ||
629 #if MESA_BIG_ENDIAN
630 getTypeSize(input[i]->Type) != 4 ||
631 #endif
632 stride < 4)
633 {
634 r700ConvertAttrib(ctx, count, input[i], &context->stream_desc[index]);
635 }
636 else
637 {
638 if (input[i]->BufferObj->Name)
639 {
640 if (stride % 4 != 0)
641 {
642 assert(((intptr_t) input[i]->Ptr) % input[i]->StrideB == 0);
643 r700AlignDataToDword(ctx, input[i], count, &context->stream_desc[index]);
644 context->stream_desc[index].is_named_bo = GL_FALSE;
645 }
646 else
647 {
648 context->stream_desc[index].stride = input[i]->StrideB;
649 context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr;
650 context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
651 context->stream_desc[index].is_named_bo = GL_TRUE;
652 }
653 }
654 else
655 {
656 int size;
657 int local_count = count;
658 uint32_t *dst;
659
660 if (input[i]->StrideB == 0)
661 {
662 size = getTypeSize(input[i]->Type) * input[i]->Size;
663 local_count = 1;
664 }
665 else
666 {
667 size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
668 }
669
670 radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo,
671 &context->stream_desc[index].bo_offset, size, 32);
672
673 radeon_bo_map(context->stream_desc[index].bo, 1);
674 assert(context->stream_desc[index].bo->ptr != NULL);
675
676
677 dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr,
678 context->stream_desc[index].bo_offset);
679
680 switch (context->stream_desc[index].dwords)
681 {
682 case 1:
683 radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
684 break;
685 case 2:
686 radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
687 break;
688 case 3:
689 radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
690 break;
691 case 4:
692 radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
693 break;
694 default:
695 assert(0);
696 break;
697 }
698 radeon_bo_unmap(context->stream_desc[index].bo);
699 }
700 }
701
702 aos->count = context->stream_desc[index].stride == 0 ? 1 : count;
703 aos->stride = context->stream_desc[index].stride / sizeof(float);
704 aos->components = context->stream_desc[index].dwords;
705 aos->bo = context->stream_desc[index].bo;
706 aos->offset = context->stream_desc[index].bo_offset;
707
708 if(context->stream_desc[index].is_named_bo)
709 {
710 radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs,
711 context->stream_desc[index].bo,
712 RADEON_GEM_DOMAIN_GTT, 0);
713 }
714 }
715
716 ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
717 first_elem(&context->radeon.dma.reserved)->bo,
718 RADEON_GEM_DOMAIN_GTT, 0);
719 }
720
721 static void r700FreeData(GLcontext *ctx)
722 {
723 /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
724 * to prevent double unref in radeonReleaseArrays
725 * called during context destroy
726 */
727 context_t *context = R700_CONTEXT(ctx);
728
729 int i;
730
731 for (i = 0; i < context->nNumActiveAos; i++)
732 {
733 if (!context->stream_desc[i].is_named_bo)
734 {
735 radeon_bo_unref(context->stream_desc[i].bo);
736 }
737 context->radeon.tcl.aos[i].bo = NULL;
738 }
739
740 if (context->ind_buf.bo != NULL)
741 {
742 radeon_bo_unref(context->ind_buf.bo);
743 }
744 }
745
746 static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
747 {
748 context_t *context = R700_CONTEXT(ctx);
749 GLvoid *src_ptr;
750 GLuint *out;
751 int i;
752 GLboolean mapped_named_bo = GL_FALSE;
753
754 if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
755 {
756 ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
757 mapped_named_bo = GL_TRUE;
758 assert(mesa_ind_buf->obj->Pointer != NULL);
759 }
760 src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
761
762 if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
763 {
764 GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
765 GLubyte *in = (GLubyte *)src_ptr;
766
767 radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
768 &context->ind_buf.bo_offset, size, 4);
769
770 radeon_bo_map(context->ind_buf.bo, 1);
771 assert(context->ind_buf.bo->ptr != NULL);
772 out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
773
774 for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
775 {
776 *out++ = in[i] | in[i + 1] << 16;
777 }
778
779 if (i < mesa_ind_buf->count)
780 {
781 *out++ = in[i];
782 }
783
784 radeon_bo_unmap(context->ind_buf.bo);
785 #if MESA_BIG_ENDIAN
786 }
787 else
788 { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
789 GLushort *in = (GLushort *)src_ptr;
790 GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
791
792 radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
793 &context->ind_buf.bo_offset, size, 4);
794
795 radeon_bo_map(context->ind_buf.bo, 1);
796 assert(context->ind_buf.bo->ptr != NULL);
797 out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
798
799 for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
800 {
801 *out++ = in[i] | in[i + 1] << 16;
802 }
803
804 if (i < mesa_ind_buf->count)
805 {
806 *out++ = in[i];
807 }
808 radeon_bo_unmap(context->ind_buf.bo);
809 #endif
810 }
811
812 context->ind_buf.is_32bit = GL_FALSE;
813 context->ind_buf.count = mesa_ind_buf->count;
814
815 if (mapped_named_bo)
816 {
817 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
818 }
819 }
820
821 static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
822 {
823 context_t *context = R700_CONTEXT(ctx);
824
825 if (!mesa_ind_buf) {
826 context->ind_buf.bo = NULL;
827 return;
828 }
829
830 #if MESA_BIG_ENDIAN
831 if (mesa_ind_buf->type == GL_UNSIGNED_INT)
832 #else
833 if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
834 #endif
835 {
836 const GLvoid *src_ptr;
837 GLvoid *dst_ptr;
838 GLboolean mapped_named_bo = GL_FALSE;
839
840 if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
841 {
842 ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
843 assert(mesa_ind_buf->obj->Pointer != NULL);
844 mapped_named_bo = GL_TRUE;
845 }
846
847 src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
848
849 const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
850
851 radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
852 &context->ind_buf.bo_offset, size, 4);
853 radeon_bo_map(context->ind_buf.bo, 1);
854 assert(context->ind_buf.bo->ptr != NULL);
855 dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
856
857 memcpy(dst_ptr, src_ptr, size);
858
859 radeon_bo_unmap(context->ind_buf.bo);
860 context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
861 context->ind_buf.count = mesa_ind_buf->count;
862
863 if (mapped_named_bo)
864 {
865 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
866 }
867 }
868 else
869 {
870 r700FixupIndexBuffer(ctx, mesa_ind_buf);
871 }
872 }
873
874 static GLboolean check_fallbacks(GLcontext *ctx)
875 {
876 if (ctx->RenderMode != GL_RENDER)
877 return GL_TRUE;
878
879 return GL_FALSE;
880 }
881
882 static GLboolean r700TryDrawPrims(GLcontext *ctx,
883 const struct gl_client_array *arrays[],
884 const struct _mesa_prim *prim,
885 GLuint nr_prims,
886 const struct _mesa_index_buffer *ib,
887 GLuint min_index,
888 GLuint max_index )
889 {
890 context_t *context = R700_CONTEXT(ctx);
891 radeonContextPtr radeon = &context->radeon;
892 GLuint i, id = 0;
893 struct radeon_renderbuffer *rrb;
894
895 if (ctx->NewState)
896 _mesa_update_state( ctx );
897
898 if (check_fallbacks(ctx))
899 return GL_FALSE;
900
901 _tnl_UpdateFixedFunctionProgram(ctx);
902 r700SetVertexFormat(ctx, arrays, max_index + 1);
903 /* shaders need to be updated before buffers are validated */
904 r700UpdateShaders(ctx);
905 if (!r600ValidateBuffers(ctx))
906 return GL_FALSE;
907
908 /* always emit CB base to prevent
909 * lock ups on some chips.
910 */
911 R600_STATECHANGE(context, cb_target);
912 /* mark vtx as dirty since it changes per-draw */
913 R600_STATECHANGE(context, vtx);
914
915 r700SetScissor(context);
916 r700SetupVertexProgram(ctx);
917 r700SetupFragmentProgram(ctx);
918 r700UpdateShaderStates(ctx);
919
920 GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims)
921 + context->radeon.cmdbuf.cs->cdw;
922
923 r700SetupIndexBuffer(ctx, ib);
924 r700SetupStreams(ctx, arrays, max_index + 1);
925
926 radeonEmitState(radeon);
927
928 radeon_debug_add_indent();
929 for (i = 0; i < nr_prims; ++i)
930 {
931 if (context->ind_buf.bo)
932 r700RunRenderPrimitive(ctx,
933 prim[i].start,
934 prim[i].start + prim[i].count,
935 prim[i].mode);
936 else
937 r700RunRenderPrimitiveImmediate(ctx,
938 prim[i].start,
939 prim[i].start + prim[i].count,
940 prim[i].mode);
941 }
942 radeon_debug_remove_indent();
943
944 /* Flush render op cached for last several quads. */
945 /* XXX drm should handle this in fence submit */
946 r700WaitForIdleClean(context);
947
948 rrb = radeon_get_colorbuffer(&context->radeon);
949 if (rrb && rrb->bo)
950 r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
951 CB_ACTION_ENA_bit | (1 << (id + 6)));
952
953 rrb = radeon_get_depthbuffer(&context->radeon);
954 if (rrb && rrb->bo)
955 r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
956 DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
957
958 r700FreeData(ctx);
959
960 if (emit_end < context->radeon.cmdbuf.cs->cdw)
961 {
962 WARN_ONCE("Rendering was %d commands larger than predicted size."
963 " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
964 }
965
966 return GL_TRUE;
967 }
968
969 static void r700DrawPrims(GLcontext *ctx,
970 const struct gl_client_array *arrays[],
971 const struct _mesa_prim *prim,
972 GLuint nr_prims,
973 const struct _mesa_index_buffer *ib,
974 GLboolean index_bounds_valid,
975 GLuint min_index,
976 GLuint max_index)
977 {
978 GLboolean retval = GL_FALSE;
979
980 /* This check should get folded into just the places that
981 * min/max index are really needed.
982 */
983 if (!index_bounds_valid) {
984 vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
985 }
986
987 if (min_index) {
988 vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrims );
989 return;
990 }
991
992 /* Make an attempt at drawing */
993 retval = r700TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
994
995 /* If failed run tnl pipeline - it should take care of fallbacks */
996 if (!retval) {
997 _swsetup_Wakeup(ctx);
998 _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
999 }
1000 }
1001
1002 void r700InitDraw(GLcontext *ctx)
1003 {
1004 struct vbo_context *vbo = vbo_context(ctx);
1005
1006 /* to be enabled */
1007 vbo->draw_prims = r700DrawPrims;
1008 }
1009
1010