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r600: add support for draw_elements_base_vertex
[mesa.git] / src / mesa / drivers / dri / r600 / r700_render.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/glheader.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36 #include "main/api_arrayelt.h"
37 #include "swrast/swrast.h"
38 #include "swrast_setup/swrast_setup.h"
39 #include "vbo/vbo.h"
40
41 #include "tnl/tnl.h"
42 #include "tnl/t_vp_build.h"
43 #include "tnl/t_context.h"
44 #include "tnl/t_vertex.h"
45 #include "vbo/vbo_context.h"
46
47 #include "r600_context.h"
48 #include "r600_cmdbuf.h"
49
50 #include "r600_tex.h"
51
52 #include "r700_vertprog.h"
53 #include "r700_fragprog.h"
54 #include "r700_state.h"
55
56 #include "radeon_buffer_objects.h"
57 #include "radeon_common_context.h"
58
59 void r700WaitForIdle(context_t *context);
60 void r700WaitForIdleClean(context_t *context);
61 static unsigned int r700PrimitiveType(int prim);
62 GLboolean r700SyncSurf(context_t *context,
63 struct radeon_bo *pbo,
64 uint32_t read_domain,
65 uint32_t write_domain,
66 uint32_t sync_type);
67
68 void r700WaitForIdle(context_t *context)
69 {
70 BATCH_LOCALS(&context->radeon);
71 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
72 BEGIN_BATCH_NO_AUTOSTATE(3);
73
74 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
75 R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
76 R600_OUT_BATCH(WAIT_3D_IDLE_bit);
77
78 END_BATCH();
79 COMMIT_BATCH();
80 }
81
82 void r700WaitForIdleClean(context_t *context)
83 {
84 BATCH_LOCALS(&context->radeon);
85 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
86 BEGIN_BATCH_NO_AUTOSTATE(5);
87
88 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
89 R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
90
91 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
92 R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
93 R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
94
95 END_BATCH();
96 COMMIT_BATCH();
97 }
98
99 void r700Start3D(context_t *context)
100 {
101 BATCH_LOCALS(&context->radeon);
102 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
103 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
104 {
105 BEGIN_BATCH_NO_AUTOSTATE(2);
106 R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0));
107 R600_OUT_BATCH(0);
108 END_BATCH();
109 }
110
111 BEGIN_BATCH_NO_AUTOSTATE(3);
112 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
113 R600_OUT_BATCH(0x80000000);
114 R600_OUT_BATCH(0x80000000);
115 END_BATCH();
116
117 COMMIT_BATCH();
118 }
119
120 GLboolean r700SyncSurf(context_t *context,
121 struct radeon_bo *pbo,
122 uint32_t read_domain,
123 uint32_t write_domain,
124 uint32_t sync_type)
125 {
126 BATCH_LOCALS(&context->radeon);
127 radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
128 uint32_t cp_coher_size;
129
130 if (!pbo)
131 return GL_FALSE;
132
133 if (pbo->size == 0xffffffff)
134 cp_coher_size = 0xffffffff;
135 else
136 cp_coher_size = ((pbo->size + 255) >> 8);
137
138 BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
139 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
140 R600_OUT_BATCH(sync_type);
141 R600_OUT_BATCH(cp_coher_size);
142 R600_OUT_BATCH(0);
143 R600_OUT_BATCH(10);
144 R600_OUT_BATCH_RELOC(0,
145 pbo,
146 0,
147 read_domain, write_domain, 0);
148 END_BATCH();
149 COMMIT_BATCH();
150
151 return GL_TRUE;
152 }
153
154 static unsigned int r700PrimitiveType(int prim)
155 {
156 switch (prim & PRIM_MODE_MASK)
157 {
158 case GL_POINTS:
159 return DI_PT_POINTLIST;
160 break;
161 case GL_LINES:
162 return DI_PT_LINELIST;
163 break;
164 case GL_LINE_STRIP:
165 return DI_PT_LINESTRIP;
166 break;
167 case GL_LINE_LOOP:
168 return DI_PT_LINELOOP;
169 break;
170 case GL_TRIANGLES:
171 return DI_PT_TRILIST;
172 break;
173 case GL_TRIANGLE_STRIP:
174 return DI_PT_TRISTRIP;
175 break;
176 case GL_TRIANGLE_FAN:
177 return DI_PT_TRIFAN;
178 break;
179 case GL_QUADS:
180 return DI_PT_QUADLIST;
181 break;
182 case GL_QUAD_STRIP:
183 return DI_PT_QUADSTRIP;
184 break;
185 case GL_POLYGON:
186 return DI_PT_POLYGON;
187 break;
188 default:
189 assert(0);
190 return -1;
191 break;
192 }
193 }
194
195 static int r700NumVerts(int num_verts, int prim)
196 {
197 int verts_off = 0;
198
199 switch (prim & PRIM_MODE_MASK) {
200 case GL_POINTS:
201 verts_off = 0;
202 break;
203 case GL_LINES:
204 verts_off = num_verts % 2;
205 break;
206 case GL_LINE_STRIP:
207 if (num_verts < 2)
208 verts_off = num_verts;
209 break;
210 case GL_LINE_LOOP:
211 if (num_verts < 2)
212 verts_off = num_verts;
213 break;
214 case GL_TRIANGLES:
215 verts_off = num_verts % 3;
216 break;
217 case GL_TRIANGLE_STRIP:
218 if (num_verts < 3)
219 verts_off = num_verts;
220 break;
221 case GL_TRIANGLE_FAN:
222 if (num_verts < 3)
223 verts_off = num_verts;
224 break;
225 case GL_QUADS:
226 verts_off = num_verts % 4;
227 break;
228 case GL_QUAD_STRIP:
229 if (num_verts < 4)
230 verts_off = num_verts;
231 else
232 verts_off = num_verts % 2;
233 break;
234 case GL_POLYGON:
235 if (num_verts < 3)
236 verts_off = num_verts;
237 break;
238 default:
239 assert(0);
240 return -1;
241 break;
242 }
243
244 return num_verts - verts_off;
245 }
246
247 static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end,
248 int prim, GLint basevertex)
249 {
250 context_t *context = R700_CONTEXT(ctx);
251 BATCH_LOCALS(&context->radeon);
252 int type, total_emit;
253 int num_indices;
254 uint32_t vgt_draw_initiator = 0;
255 uint32_t vgt_index_type = 0;
256 uint32_t vgt_primitive_type = 0;
257 uint32_t vgt_num_indices = 0;
258
259 type = r700PrimitiveType(prim);
260 num_indices = r700NumVerts(end - start, prim);
261
262 radeon_print(RADEON_RENDER, RADEON_TRACE,
263 "%s type %x num_indices %d\n",
264 __func__, type, num_indices);
265
266 if (type < 0 || num_indices <= 0)
267 return;
268
269 SETfield(vgt_primitive_type, type,
270 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
271
272 SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
273
274 if(GL_TRUE != context->ind_buf.is_32bit)
275 {
276 SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
277 }
278
279 vgt_num_indices = num_indices;
280 SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
281 SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
282
283 total_emit = 3 /* VGT_PRIMITIVE_TYPE */
284 + 2 /* VGT_INDEX_TYPE */
285 + 2 /* NUM_INSTANCES */
286 + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
287 + 5 + 2; /* DRAW_INDEX */
288
289 BEGIN_BATCH_NO_AUTOSTATE(total_emit);
290 // prim
291 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
292 R600_OUT_BATCH(vgt_primitive_type);
293 // index type
294 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
295 R600_OUT_BATCH(vgt_index_type);
296 // num instances
297 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
298 R600_OUT_BATCH(1);
299 /* offset */
300 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
301 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
302 R600_OUT_BATCH(basevertex); //VTX_BASE_VTX_LOC
303 R600_OUT_BATCH(0); //VTX_START_INST_LOC
304 // draw packet
305 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
306 R600_OUT_BATCH(context->ind_buf.bo_offset);
307 R600_OUT_BATCH(0);
308 R600_OUT_BATCH(vgt_num_indices);
309 R600_OUT_BATCH(vgt_draw_initiator);
310 R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
311 context->ind_buf.bo,
312 context->ind_buf.bo_offset,
313 RADEON_GEM_DOMAIN_GTT, 0, 0);
314 END_BATCH();
315 COMMIT_BATCH();
316 }
317
318 static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end, int prim)
319 {
320 context_t *context = R700_CONTEXT(ctx);
321 BATCH_LOCALS(&context->radeon);
322 int type, i;
323 uint32_t num_indices, total_emit = 0;
324 uint32_t vgt_draw_initiator = 0;
325 uint32_t vgt_index_type = 0;
326 uint32_t vgt_primitive_type = 0;
327 uint32_t vgt_num_indices = 0;
328
329 type = r700PrimitiveType(prim);
330 num_indices = r700NumVerts(end - start, prim);
331
332 radeon_print(RADEON_RENDER, RADEON_TRACE,
333 "%s type %x num_indices %d\n",
334 __func__, type, num_indices);
335
336 if (type < 0 || num_indices <= 0)
337 return;
338
339 SETfield(vgt_primitive_type, type,
340 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
341
342 if (num_indices > 0xffff)
343 {
344 SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
345 }
346 else
347 {
348 SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
349 }
350
351 vgt_num_indices = num_indices;
352 SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
353
354 if (start == 0)
355 {
356 SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
357 }
358 else
359 {
360 if (num_indices > 0xffff)
361 {
362 total_emit += num_indices;
363 }
364 else
365 {
366 total_emit += (num_indices + 1) / 2;
367 }
368 SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
369 }
370
371 total_emit += 3 /* VGT_PRIMITIVE_TYPE */
372 + 2 /* VGT_INDEX_TYPE */
373 + 2 /* NUM_INSTANCES */
374 + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
375 + 3; /* DRAW */
376
377 BEGIN_BATCH_NO_AUTOSTATE(total_emit);
378 // prim
379 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
380 R600_OUT_BATCH(vgt_primitive_type);
381 // index type
382 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
383 R600_OUT_BATCH(vgt_index_type);
384 // num instances
385 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
386 R600_OUT_BATCH(1);
387 /* offset */
388 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
389 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
390 R600_OUT_BATCH(0); //VTX_BASE_VTX_LOC
391 R600_OUT_BATCH(0); //VTX_START_INST_LOC
392 // draw packet
393 if(start == 0)
394 {
395 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
396 R600_OUT_BATCH(vgt_num_indices);
397 R600_OUT_BATCH(vgt_draw_initiator);
398 }
399 else
400 {
401 if (num_indices > 0xffff)
402 {
403 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
404 R600_OUT_BATCH(vgt_num_indices);
405 R600_OUT_BATCH(vgt_draw_initiator);
406 for (i = start; i < (start + num_indices); i++)
407 {
408 R600_OUT_BATCH(i);
409 }
410 }
411 else
412 {
413 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)));
414 R600_OUT_BATCH(vgt_num_indices);
415 R600_OUT_BATCH(vgt_draw_initiator);
416 for (i = start; i < (start + num_indices); i += 2)
417 {
418 if ((i + 1) == (start + num_indices))
419 {
420 R600_OUT_BATCH(i);
421 }
422 else
423 {
424 R600_OUT_BATCH(((i + 1) << 16) | (i));
425 }
426 }
427 }
428 }
429
430 END_BATCH();
431 COMMIT_BATCH();
432 }
433
434 /* start 3d, idle, cb/db flush */
435 #define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
436
437 static GLuint r700PredictRenderSize(GLcontext* ctx,
438 const struct _mesa_prim *prim,
439 const struct _mesa_index_buffer *ib,
440 GLuint nr_prims)
441 {
442 context_t *context = R700_CONTEXT(ctx);
443 GLboolean flushed;
444 GLuint dwords, i;
445 GLuint state_size;
446
447 dwords = PRE_EMIT_STATE_BUFSZ;
448 if (ib)
449 dwords += nr_prims * 18;
450 else {
451 for (i = 0; i < nr_prims; ++i)
452 {
453 if (prim[i].start == 0)
454 dwords += 14;
455 else if (prim[i].count > 0xffff)
456 dwords += prim[i].count + 14;
457 else
458 dwords += ((prim[i].count + 1) / 2) + 14;
459 }
460 }
461
462 state_size = radeonCountStateEmitSize(&context->radeon);
463 flushed = rcommonEnsureCmdBufSpace(&context->radeon,
464 dwords + state_size,
465 __FUNCTION__);
466 if (flushed)
467 dwords += radeonCountStateEmitSize(&context->radeon);
468 else
469 dwords += state_size;
470
471 radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
472 return dwords;
473
474 }
475
476 #define CONVERT( TYPE, MACRO ) do { \
477 GLuint i, j, sz; \
478 sz = input->Size; \
479 if (input->Normalized) { \
480 for (i = 0; i < count; i++) { \
481 const TYPE *in = (TYPE *)src_ptr; \
482 for (j = 0; j < sz; j++) { \
483 *dst_ptr++ = MACRO(*in); \
484 in++; \
485 } \
486 src_ptr += stride; \
487 } \
488 } else { \
489 for (i = 0; i < count; i++) { \
490 const TYPE *in = (TYPE *)src_ptr; \
491 for (j = 0; j < sz; j++) { \
492 *dst_ptr++ = (GLfloat)(*in); \
493 in++; \
494 } \
495 src_ptr += stride; \
496 } \
497 } \
498 } while (0)
499
500 /**
501 * Convert attribute data type to float
502 * If the attribute uses named buffer object replace the bo with newly allocated bo
503 */
504 static void r700ConvertAttrib(GLcontext *ctx, int count,
505 const struct gl_client_array *input,
506 struct StreamDesc *attr)
507 {
508 context_t *context = R700_CONTEXT(ctx);
509 const GLvoid *src_ptr;
510 GLboolean mapped_named_bo = GL_FALSE;
511 GLfloat *dst_ptr;
512 GLuint stride;
513
514 stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
515
516 /* Convert value for first element only */
517 if (input->StrideB == 0)
518 {
519 count = 1;
520 }
521
522 if (input->BufferObj->Name)
523 {
524 if (!input->BufferObj->Pointer)
525 {
526 ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj);
527 mapped_named_bo = GL_TRUE;
528 }
529
530 src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
531 }
532 else
533 {
534 src_ptr = input->Ptr;
535 }
536
537 radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset,
538 sizeof(GLfloat) * input->Size * count, 32);
539
540 radeon_bo_map(attr->bo, 1);
541
542 dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
543
544 assert(src_ptr != NULL);
545
546 switch (input->Type)
547 {
548 case GL_DOUBLE:
549 CONVERT(GLdouble, (GLfloat));
550 break;
551 case GL_UNSIGNED_INT:
552 CONVERT(GLuint, UINT_TO_FLOAT);
553 break;
554 case GL_INT:
555 CONVERT(GLint, INT_TO_FLOAT);
556 break;
557 case GL_UNSIGNED_SHORT:
558 CONVERT(GLushort, USHORT_TO_FLOAT);
559 break;
560 case GL_SHORT:
561 CONVERT(GLshort, SHORT_TO_FLOAT);
562 break;
563 case GL_UNSIGNED_BYTE:
564 assert(input->Format != GL_BGRA);
565 CONVERT(GLubyte, UBYTE_TO_FLOAT);
566 break;
567 case GL_BYTE:
568 CONVERT(GLbyte, BYTE_TO_FLOAT);
569 break;
570 default:
571 assert(0);
572 break;
573 }
574
575 radeon_bo_unmap(attr->bo);
576
577 if (mapped_named_bo)
578 {
579 ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj);
580 }
581 }
582
583 static void r700AlignDataToDword(GLcontext *ctx,
584 const struct gl_client_array *input,
585 int count,
586 struct StreamDesc *attr)
587 {
588 context_t *context = R700_CONTEXT(ctx);
589 const int dst_stride = (input->StrideB + 3) & ~3;
590 const int size = getTypeSize(input->Type) * input->Size * count;
591 GLboolean mapped_named_bo = GL_FALSE;
592
593 radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32);
594
595 radeon_bo_map(attr->bo, 1);
596
597 if (!input->BufferObj->Pointer)
598 {
599 ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj);
600 mapped_named_bo = GL_TRUE;
601 }
602
603 {
604 GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
605 GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
606 int i;
607
608 for (i = 0; i < count; ++i)
609 {
610 memcpy(dst_ptr, src_ptr, input->StrideB);
611 src_ptr += input->StrideB;
612 dst_ptr += dst_stride;
613 }
614 }
615
616 radeon_bo_unmap(attr->bo);
617 if (mapped_named_bo)
618 {
619 ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj);
620 }
621
622 attr->stride = dst_stride;
623 }
624
625 static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input[], int count)
626 {
627 context_t *context = R700_CONTEXT(ctx);
628 GLuint stride;
629 int ret;
630 int i, index;
631
632 R600_STATECHANGE(context, vtx);
633
634 for(index = 0; index < context->nNumActiveAos; index++)
635 {
636 struct radeon_aos *aos = &context->radeon.tcl.aos[index];
637 i = context->stream_desc[index].element;
638
639 stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
640
641 if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT
642 #if MESA_BIG_ENDIAN
643 || getTypeSize(input[i]->Type) != 4
644 #endif
645 )
646 {
647 r700ConvertAttrib(ctx, count, input[i], &context->stream_desc[index]);
648 }
649 else
650 {
651 if (input[i]->BufferObj->Name)
652 {
653 context->stream_desc[index].stride = input[i]->StrideB;
654 context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr;
655 context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
656 context->stream_desc[index].is_named_bo = GL_TRUE;
657 }
658 else
659 {
660 int size;
661 int local_count = count;
662 uint32_t *dst;
663
664 if (input[i]->StrideB == 0)
665 {
666 size = getTypeSize(input[i]->Type) * input[i]->Size;
667 local_count = 1;
668 }
669 else
670 {
671 size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
672 }
673
674 radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo,
675 &context->stream_desc[index].bo_offset, size, 32);
676
677 radeon_bo_map(context->stream_desc[index].bo, 1);
678 assert(context->stream_desc[index].bo->ptr != NULL);
679
680
681 dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr,
682 context->stream_desc[index].bo_offset);
683
684 switch (context->stream_desc[index].dwords)
685 {
686 case 1:
687 radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
688 break;
689 case 2:
690 radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
691 break;
692 case 3:
693 radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
694 break;
695 case 4:
696 radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
697 break;
698 default:
699 assert(0);
700 break;
701 }
702 radeon_bo_unmap(context->stream_desc[index].bo);
703 }
704 }
705
706 aos->count = context->stream_desc[index].stride == 0 ? 1 : count;
707 aos->stride = context->stream_desc[index].stride / sizeof(float);
708 aos->components = context->stream_desc[index].dwords;
709 aos->bo = context->stream_desc[index].bo;
710 aos->offset = context->stream_desc[index].bo_offset;
711
712 if(context->stream_desc[index].is_named_bo)
713 {
714 radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs,
715 context->stream_desc[index].bo,
716 RADEON_GEM_DOMAIN_GTT, 0);
717 }
718 }
719
720 ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
721 first_elem(&context->radeon.dma.reserved)->bo,
722 RADEON_GEM_DOMAIN_GTT, 0);
723 }
724
725 static void r700FreeData(GLcontext *ctx)
726 {
727 /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
728 * to prevent double unref in radeonReleaseArrays
729 * called during context destroy
730 */
731 context_t *context = R700_CONTEXT(ctx);
732
733 int i;
734
735 for (i = 0; i < context->nNumActiveAos; i++)
736 {
737 if (!context->stream_desc[i].is_named_bo)
738 {
739 radeon_bo_unref(context->stream_desc[i].bo);
740 }
741 context->radeon.tcl.aos[i].bo = NULL;
742 }
743
744 if (context->ind_buf.bo != NULL)
745 {
746 radeon_bo_unref(context->ind_buf.bo);
747 }
748 }
749
750 static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
751 {
752 context_t *context = R700_CONTEXT(ctx);
753 GLvoid *src_ptr;
754 GLuint *out;
755 int i;
756 GLboolean mapped_named_bo = GL_FALSE;
757
758 if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
759 {
760 ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
761 mapped_named_bo = GL_TRUE;
762 assert(mesa_ind_buf->obj->Pointer != NULL);
763 }
764 src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
765
766 if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
767 {
768 GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
769 GLubyte *in = (GLubyte *)src_ptr;
770
771 radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
772 &context->ind_buf.bo_offset, size, 4);
773
774 radeon_bo_map(context->ind_buf.bo, 1);
775 assert(context->ind_buf.bo->ptr != NULL);
776 out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
777
778 for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
779 {
780 *out++ = in[i] | in[i + 1] << 16;
781 }
782
783 if (i < mesa_ind_buf->count)
784 {
785 *out++ = in[i];
786 }
787
788 radeon_bo_unmap(context->ind_buf.bo);
789 #if MESA_BIG_ENDIAN
790 }
791 else
792 { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
793 GLushort *in = (GLushort *)src_ptr;
794 GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
795
796 radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
797 &context->ind_buf.bo_offset, size, 4);
798
799 radeon_bo_map(context->ind_buf.bo, 1);
800 assert(context->ind_buf.bo->ptr != NULL);
801 out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
802
803 for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
804 {
805 *out++ = in[i] | in[i + 1] << 16;
806 }
807
808 if (i < mesa_ind_buf->count)
809 {
810 *out++ = in[i];
811 }
812 radeon_bo_unmap(context->ind_buf.bo);
813 #endif
814 }
815
816 context->ind_buf.is_32bit = GL_FALSE;
817 context->ind_buf.count = mesa_ind_buf->count;
818
819 if (mapped_named_bo)
820 {
821 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
822 }
823 }
824
825 static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
826 {
827 context_t *context = R700_CONTEXT(ctx);
828
829 if (!mesa_ind_buf) {
830 context->ind_buf.bo = NULL;
831 return;
832 }
833
834 #if MESA_BIG_ENDIAN
835 if (mesa_ind_buf->type == GL_UNSIGNED_INT)
836 #else
837 if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
838 #endif
839 {
840 const GLvoid *src_ptr;
841 GLvoid *dst_ptr;
842 GLboolean mapped_named_bo = GL_FALSE;
843
844 if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
845 {
846 ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
847 assert(mesa_ind_buf->obj->Pointer != NULL);
848 mapped_named_bo = GL_TRUE;
849 }
850
851 src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
852
853 const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
854
855 radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
856 &context->ind_buf.bo_offset, size, 4);
857 radeon_bo_map(context->ind_buf.bo, 1);
858 assert(context->ind_buf.bo->ptr != NULL);
859 dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
860
861 memcpy(dst_ptr, src_ptr, size);
862
863 radeon_bo_unmap(context->ind_buf.bo);
864 context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
865 context->ind_buf.count = mesa_ind_buf->count;
866
867 if (mapped_named_bo)
868 {
869 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
870 }
871 }
872 else
873 {
874 r700FixupIndexBuffer(ctx, mesa_ind_buf);
875 }
876 }
877
878 static GLboolean check_fallbacks(GLcontext *ctx)
879 {
880 if (ctx->RenderMode != GL_RENDER)
881 return GL_TRUE;
882
883 return GL_FALSE;
884 }
885
886 static GLboolean r700TryDrawPrims(GLcontext *ctx,
887 const struct gl_client_array *arrays[],
888 const struct _mesa_prim *prim,
889 GLuint nr_prims,
890 const struct _mesa_index_buffer *ib,
891 GLuint min_index,
892 GLuint max_index )
893 {
894 context_t *context = R700_CONTEXT(ctx);
895 radeonContextPtr radeon = &context->radeon;
896 GLuint i, id = 0;
897 struct radeon_renderbuffer *rrb;
898
899 if (ctx->NewState)
900 _mesa_update_state( ctx );
901
902 if (check_fallbacks(ctx))
903 return GL_FALSE;
904
905 _tnl_UpdateFixedFunctionProgram(ctx);
906 r700SetVertexFormat(ctx, arrays, max_index + 1);
907 /* shaders need to be updated before buffers are validated */
908 r700UpdateShaders(ctx);
909 if (!r600ValidateBuffers(ctx))
910 return GL_FALSE;
911
912 /* always emit CB base to prevent
913 * lock ups on some chips.
914 */
915 R600_STATECHANGE(context, cb_target);
916 /* mark vtx as dirty since it changes per-draw */
917 R600_STATECHANGE(context, vtx);
918
919 r700SetScissor(context);
920 r700SetupVertexProgram(ctx);
921 r700SetupFragmentProgram(ctx);
922 r700UpdateShaderStates(ctx);
923
924 GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims)
925 + context->radeon.cmdbuf.cs->cdw;
926
927 r700SetupIndexBuffer(ctx, ib);
928 r700SetupStreams(ctx, arrays, max_index + 1);
929
930 radeonEmitState(radeon);
931
932 radeon_debug_add_indent();
933 for (i = 0; i < nr_prims; ++i)
934 {
935 if (context->ind_buf.bo)
936 r700RunRenderPrimitive(ctx,
937 prim[i].start,
938 prim[i].start + prim[i].count,
939 prim[i].mode,
940 prim[i].basevertex);
941 else
942 r700RunRenderPrimitiveImmediate(ctx,
943 prim[i].start,
944 prim[i].start + prim[i].count,
945 prim[i].mode);
946 }
947 radeon_debug_remove_indent();
948
949 /* Flush render op cached for last several quads. */
950 /* XXX drm should handle this in fence submit */
951 r700WaitForIdleClean(context);
952
953 rrb = radeon_get_colorbuffer(&context->radeon);
954 if (rrb && rrb->bo)
955 r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
956 CB_ACTION_ENA_bit | (1 << (id + 6)));
957
958 rrb = radeon_get_depthbuffer(&context->radeon);
959 if (rrb && rrb->bo)
960 r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
961 DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
962
963 r700FreeData(ctx);
964
965 if (emit_end < context->radeon.cmdbuf.cs->cdw)
966 {
967 WARN_ONCE("Rendering was %d commands larger than predicted size."
968 " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
969 }
970
971 return GL_TRUE;
972 }
973
974 static void r700DrawPrims(GLcontext *ctx,
975 const struct gl_client_array *arrays[],
976 const struct _mesa_prim *prim,
977 GLuint nr_prims,
978 const struct _mesa_index_buffer *ib,
979 GLboolean index_bounds_valid,
980 GLuint min_index,
981 GLuint max_index)
982 {
983 GLboolean retval = GL_FALSE;
984
985 context_t *context = R700_CONTEXT(ctx);
986 radeonContextPtr radeon = &context->radeon;
987 radeon_prepare_render(radeon);
988
989 /* This check should get folded into just the places that
990 * min/max index are really needed.
991 */
992
993 if (!vbo_all_varyings_in_vbos(arrays)) {
994 if (!index_bounds_valid)
995 vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
996 /* do we want to rebase, minimizes the
997 * amount of data to upload? */
998 if (min_index) {
999 vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrims );
1000 return;
1001 }
1002 }
1003 /* Make an attempt at drawing */
1004 retval = r700TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
1005
1006 /* If failed run tnl pipeline - it should take care of fallbacks */
1007 if (!retval) {
1008 _swsetup_Wakeup(ctx);
1009 _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
1010 }
1011 }
1012
1013 void r700InitDraw(GLcontext *ctx)
1014 {
1015 struct vbo_context *vbo = vbo_context(ctx);
1016
1017 /* to be enabled */
1018 vbo->draw_prims = r700DrawPrims;
1019 }
1020
1021