2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
63 void r700SetDefaultStates(context_t
*context
) //--------------------
68 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
70 context_t
*context
= R700_CONTEXT(ctx
);
72 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
73 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
75 struct r700_vertex_program
*vp
;
78 if (context
->radeon
.NewGLState
)
80 context
->radeon
.NewGLState
= 0;
82 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
84 /* mat states from state var not array for sw */
85 dummy_attrib
[i
].stride
= 0;
87 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
88 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
91 _tnl_UpdateFixedFunctionProgram(ctx
);
93 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
95 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
98 r700SelectVertexShader(ctx
);
99 vp
= (struct r700_vertex_program
*)ctx
->VertexProgram
._Current
;
101 if (vp
->translated
== GL_FALSE
)
104 //fprintf(stderr, "Failing back to sw-tcl\n");
105 //hw_tcl_on = future_hw_tcl_on = 0;
106 //r300ResetHwState(rmesa);
108 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
113 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
117 * To correctly position primitives:
119 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
121 context_t
*context
= R700_CONTEXT(ctx
);
122 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
123 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
124 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
125 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
126 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
129 GLfloat tx
= v
[MAT_TX
] + xoffset
;
130 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
132 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
133 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
135 radeonUpdateScissor(ctx
);
139 * Tell the card where to render (offset, pitch).
140 * Effected by glDrawBuffer, etc
142 void r700UpdateDrawBuffer(GLcontext
* ctx
) /* TODO */ //---------------------
144 #if 0 /* to be enabled */
145 context_t
*context
= R700_CONTEXT(ctx
);
147 switch (ctx
->DrawBuffer
->_ColorDrawBufferIndexes
[0])
149 case BUFFER_FRONT_LEFT
:
150 context
->target
.rt
= context
->screen
->frontBuffer
;
152 case BUFFER_BACK_LEFT
:
153 context
->target
.rt
= context
->screen
->backBuffer
;
156 memset (&context
->target
.rt
, sizeof(context
->target
.rt
), 0);
158 #endif /* to be enabled */
161 static void r700FetchStateParameter(GLcontext
* ctx
,
162 const gl_state_index state
[STATE_LENGTH
],
165 context_t
*context
= R700_CONTEXT(ctx
);
170 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
172 struct r700_fragment_program
*fp
;
173 struct gl_program_parameter_list
*paramList
;
176 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
)))
179 fp
= (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
185 paramList
= fp
->mesa_program
.Base
.Parameters
;
192 for (i
= 0; i
< paramList
->NumParameters
; i
++)
194 if (paramList
->Parameters
[i
].Type
== PROGRAM_STATE_VAR
)
196 r700FetchStateParameter(ctx
,
197 paramList
->Parameters
[i
].
199 paramList
->ParameterValues
[i
]);
205 * Called by Mesa after an internal state update.
207 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
209 context_t
*context
= R700_CONTEXT(ctx
);
211 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
213 _swrast_InvalidateState(ctx
, new_state
);
214 _swsetup_InvalidateState(ctx
, new_state
);
215 _vbo_InvalidateState(ctx
, new_state
);
216 _tnl_InvalidateState(ctx
, new_state
);
217 _ae_invalidate_state(ctx
, new_state
);
219 if (new_state
& (_NEW_BUFFERS
| _NEW_COLOR
| _NEW_PIXEL
))
221 _mesa_update_framebuffer(ctx
);
222 /* this updates the DrawBuffer's Width/Height if it's a FBO */
223 _mesa_update_draw_buffer_bounds(ctx
);
225 r700UpdateDrawBuffer(ctx
);
228 r700UpdateStateParameters(ctx
, new_state
);
230 if(GL_TRUE
== r700
->bEnablePerspective
)
232 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
233 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
234 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
236 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
238 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
239 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
243 /* For orthogonal case. */
244 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
245 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
247 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
249 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
250 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
253 context
->radeon
.NewGLState
|= new_state
;
256 static void r700SetDepthState(GLcontext
* ctx
)
258 context_t
*context
= R700_CONTEXT(ctx
);
260 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
264 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
267 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
271 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
274 switch (ctx
->Depth
.Func
)
277 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
278 ZFUNC_shift
, ZFUNC_mask
);
281 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
282 ZFUNC_shift
, ZFUNC_mask
);
285 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
286 ZFUNC_shift
, ZFUNC_mask
);
289 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
290 ZFUNC_shift
, ZFUNC_mask
);
293 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
294 ZFUNC_shift
, ZFUNC_mask
);
297 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
298 ZFUNC_shift
, ZFUNC_mask
);
301 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
302 ZFUNC_shift
, ZFUNC_mask
);
305 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
306 ZFUNC_shift
, ZFUNC_mask
);
309 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
310 ZFUNC_shift
, ZFUNC_mask
);
316 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
317 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
321 static void r700SetAlphaState(GLcontext
* ctx
)
323 context_t
*context
= R700_CONTEXT(ctx
);
324 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
325 uint32_t alpha_func
= REF_ALWAYS
;
326 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
328 switch (ctx
->Color
.AlphaFunc
) {
330 alpha_func
= REF_NEVER
;
333 alpha_func
= REF_LESS
;
336 alpha_func
= REF_EQUAL
;
339 alpha_func
= REF_LEQUAL
;
342 alpha_func
= REF_GREATER
;
345 alpha_func
= REF_NOTEQUAL
;
348 alpha_func
= REF_GEQUAL
;
351 /*alpha_func = REF_ALWAYS; */
352 really_enabled
= GL_FALSE
;
356 if (really_enabled
) {
357 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
358 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
359 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
360 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
362 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
367 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
371 r700SetAlphaState(ctx
);
375 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
377 context_t
*context
= R700_CONTEXT(ctx
);
378 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
380 r700
->CB_BLEND_RED
.f32All
= cf
[0];
381 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
382 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
383 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
386 static int blend_factor(GLenum factor
, GLboolean is_src
)
396 return BLEND_DST_COLOR
;
398 case GL_ONE_MINUS_DST_COLOR
:
399 return BLEND_ONE_MINUS_DST_COLOR
;
402 return BLEND_SRC_COLOR
;
404 case GL_ONE_MINUS_SRC_COLOR
:
405 return BLEND_ONE_MINUS_SRC_COLOR
;
408 return BLEND_SRC_ALPHA
;
410 case GL_ONE_MINUS_SRC_ALPHA
:
411 return BLEND_ONE_MINUS_SRC_ALPHA
;
414 return BLEND_DST_ALPHA
;
416 case GL_ONE_MINUS_DST_ALPHA
:
417 return BLEND_ONE_MINUS_DST_ALPHA
;
419 case GL_SRC_ALPHA_SATURATE
:
420 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
422 case GL_CONSTANT_COLOR
:
423 return BLEND_CONSTANT_COLOR
;
425 case GL_ONE_MINUS_CONSTANT_COLOR
:
426 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
428 case GL_CONSTANT_ALPHA
:
429 return BLEND_CONSTANT_ALPHA
;
431 case GL_ONE_MINUS_CONSTANT_ALPHA
:
432 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
435 fprintf(stderr
, "unknown blend factor %x\n", factor
);
436 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
441 static void r700SetBlendState(GLcontext
* ctx
)
443 context_t
*context
= R700_CONTEXT(ctx
);
444 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
446 uint32_t blend_reg
= 0, eqn
, eqnA
;
448 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
450 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
452 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
454 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
456 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
458 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
460 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
461 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
462 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
464 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
469 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
470 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
472 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
473 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
475 switch (ctx
->Color
.BlendEquationRGB
) {
477 eqn
= COMB_DST_PLUS_SRC
;
479 case GL_FUNC_SUBTRACT
:
480 eqn
= COMB_SRC_MINUS_DST
;
482 case GL_FUNC_REVERSE_SUBTRACT
:
483 eqn
= COMB_DST_MINUS_SRC
;
486 eqn
= COMB_MIN_DST_SRC
;
489 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
492 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
495 eqn
= COMB_MAX_DST_SRC
;
498 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
501 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
506 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
507 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
511 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
514 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
515 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
517 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
518 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
520 switch (ctx
->Color
.BlendEquationA
) {
522 eqnA
= COMB_DST_PLUS_SRC
;
524 case GL_FUNC_SUBTRACT
:
525 eqnA
= COMB_SRC_MINUS_DST
;
527 case GL_FUNC_REVERSE_SUBTRACT
:
528 eqnA
= COMB_DST_MINUS_SRC
;
531 eqnA
= COMB_MIN_DST_SRC
;
534 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
537 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
540 eqnA
= COMB_MAX_DST_SRC
;
543 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
546 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
550 "[%s:%u] Invalid A blend equation (0x%04x).\n",
551 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
556 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
558 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
560 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
561 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
563 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
564 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
566 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
567 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
571 static void r700BlendEquationSeparate(GLcontext
* ctx
,
572 GLenum modeRGB
, GLenum modeA
) //-----------------
574 r700SetBlendState(ctx
);
577 static void r700BlendFuncSeparate(GLcontext
* ctx
,
578 GLenum sfactorRGB
, GLenum dfactorRGB
,
579 GLenum sfactorA
, GLenum dfactorA
) //------------------------
581 r700SetBlendState(ctx
);
585 * Translate LogicOp enums into hardware representation.
586 * Both use a very logical bit-wise layout, but unfortunately the order
587 * of bits is reversed.
589 static GLuint
translate_logicop(GLenum logicop
)
591 GLuint bits
= logicop
- GL_CLEAR
;
592 bits
= ((bits
& 1) << 3) | ((bits
& 2) << 1) | ((bits
& 4) >> 1) | ((bits
& 8) >> 3);
597 * Used internally to update the r300->hw hardware state to match the
598 * current OpenGL state.
600 static void r700SetLogicOpState(GLcontext
*ctx
)
602 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
604 if (RGBA_LOGICOP_ENABLED(ctx
))
605 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
606 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
608 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
612 * Called by Mesa when an application program changes the LogicOp state
615 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
617 if (RGBA_LOGICOP_ENABLED(ctx
))
618 r700SetLogicOpState(ctx
);
621 static void r700UpdateCulling(GLcontext
* ctx
)
623 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
625 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
626 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
627 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
629 if (ctx
->Polygon
.CullFlag
)
631 switch (ctx
->Polygon
.CullFaceMode
)
634 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
635 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
638 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
639 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
641 case GL_FRONT_AND_BACK
:
642 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
643 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
646 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
647 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
652 switch (ctx
->Polygon
.FrontFace
)
655 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
658 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
661 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
666 static void r700UpdateLineStipple(GLcontext
* ctx
)
668 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
669 if (ctx
->Line
.StippleFlag
)
671 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
675 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
679 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
681 context_t
*context
= R700_CONTEXT(ctx
);
693 r700SetAlphaState(ctx
);
695 case GL_COLOR_LOGIC_OP
:
696 r700SetLogicOpState(ctx
);
697 /* fall-through, because logic op overrides blending */
699 r700SetBlendState(ctx
);
707 r700SetClipPlaneState(ctx
, cap
, state
);
710 r700SetDepthState(ctx
);
712 case GL_STENCIL_TEST
:
713 //r700SetStencilState(ctx, state);
716 r700UpdateCulling(ctx
);
718 case GL_POLYGON_OFFSET_POINT
:
719 case GL_POLYGON_OFFSET_LINE
:
720 case GL_POLYGON_OFFSET_FILL
:
721 r700SetPolygonOffsetState(ctx
, state
);
723 case GL_SCISSOR_TEST
:
724 radeon_firevertices(&context
->radeon
);
725 context
->radeon
.state
.scissor
.enabled
= state
;
726 radeonUpdateScissor(ctx
);
728 case GL_LINE_STIPPLE
:
729 r700UpdateLineStipple(ctx
);
738 * Handle glColorMask()
740 static void r700ColorMask(GLcontext
* ctx
,
741 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
743 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
744 unsigned int mask
= ((r
? 1 : 0) |
749 if (mask
!= r700
->CB_SHADER_MASK
.u32All
)
750 SETfield(r700
->CB_SHADER_MASK
.u32All
, mask
, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
754 * Change the depth testing function.
756 * \note Mesa already filters redundant calls to this function.
758 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
760 r700SetDepthState(ctx
);
764 * Enable/Disable depth writing.
766 * \note Mesa already filters redundant calls to this function.
768 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
770 r700SetDepthState(ctx
);
774 * Change the culling mode.
776 * \note Mesa already filters redundant calls to this function.
778 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
780 r700UpdateCulling(ctx
);
783 /* =============================================================
786 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
791 * Change the polygon orientation.
793 * \note Mesa already filters redundant calls to this function.
795 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
797 r700UpdateCulling(ctx
);
798 r700UpdatePolygonMode(ctx
);
801 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
803 context_t
*context
= R700_CONTEXT(ctx
);
804 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
806 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
809 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
812 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
819 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
823 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
824 GLenum func
, GLint ref
, GLuint mask
) //---------------------
829 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
833 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
834 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
838 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
841 context_t
*context
= R700_CONTEXT(ctx
);
842 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
843 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
844 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
845 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
846 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
847 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
848 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
849 GLfloat y_scale
, y_bias
;
859 GLfloat sx
= v
[MAT_SX
];
860 GLfloat tx
= v
[MAT_TX
] + xoffset
;
861 GLfloat sy
= v
[MAT_SY
] * y_scale
;
862 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
863 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
864 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
866 /* TODO : Need DMA flush as well. */
868 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
869 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
871 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
872 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
874 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
875 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
877 r700
->viewport
[id
].enabled
= GL_TRUE
;
879 r700SetScissor(context
);
883 static void r700Viewport(GLcontext
* ctx
,
887 GLsizei height
) //--------------------
889 r700UpdateWindow(ctx
, 0);
891 radeon_viewport(ctx
, x
, y
, width
, height
);
894 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
896 r700UpdateWindow(ctx
, 0);
899 static void r700PointSize(GLcontext
* ctx
, GLfloat size
) //-------------------
903 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
905 context_t
*context
= R700_CONTEXT(ctx
);
906 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
907 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
908 if (lineWidth
> 0xFFFF)
910 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
911 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
914 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
916 context_t
*context
= R700_CONTEXT(ctx
);
917 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
919 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
920 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
921 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
924 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
926 context_t
*context
= R700_CONTEXT(ctx
);
927 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
930 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
931 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
932 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
934 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
935 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
936 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
940 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
942 context_t
*context
= R700_CONTEXT(ctx
);
943 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
944 GLfloat constant
= units
;
946 switch (ctx
->Visual
.depthBits
) {
957 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
958 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
959 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
960 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
963 static void r700UpdatePolygonMode(GLcontext
* ctx
)
965 context_t
*context
= R700_CONTEXT(ctx
);
966 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
968 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
970 /* Only do something if a polygon mode is wanted, default is GL_FILL */
971 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
972 ctx
->Polygon
.BackMode
!= GL_FILL
) {
975 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
976 * correctly by selecting the correct front and back face
978 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
979 f
= ctx
->Polygon
.FrontMode
;
980 b
= ctx
->Polygon
.BackMode
;
982 f
= ctx
->Polygon
.BackMode
;
983 b
= ctx
->Polygon
.FrontMode
;
986 /* Enable polygon mode */
987 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
991 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
992 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
995 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
996 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
999 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1000 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1006 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1007 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1010 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1011 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1014 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1015 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1021 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1026 r700UpdatePolygonMode(ctx
);
1029 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1033 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1035 context_t
*context
= R700_CONTEXT(ctx
);
1036 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1040 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1041 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1043 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1044 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1045 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1046 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1049 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1051 context_t
*context
= R700_CONTEXT(ctx
);
1052 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1055 p
= cap
- GL_CLIP_PLANE0
;
1057 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1058 r700
->ucp
[p
].enabled
= GL_TRUE
;
1059 r700ClipPlane(ctx
, cap
, NULL
);
1061 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1062 r700
->ucp
[p
].enabled
= GL_FALSE
;
1066 void r700SetScissor(context_t
*context
) //---------------
1068 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1069 unsigned x1
, y1
, x2
, y2
;
1071 struct radeon_renderbuffer
*rrb
;
1073 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1074 if (!rrb
|| !rrb
->bo
) {
1077 if (context
->radeon
.state
.scissor
.enabled
) {
1078 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1079 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1080 x2
= context
->radeon
.state
.scissor
.rect
.x2
- 1;
1081 y2
= context
->radeon
.state
.scissor
.rect
.y2
- 1;
1085 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1086 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1090 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1091 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1092 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1093 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1094 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1096 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1097 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1098 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1099 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1102 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1103 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1104 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1105 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1106 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1107 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1108 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1109 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1111 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1112 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1113 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1114 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1115 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1116 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1118 /* more....2d clip */
1119 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1120 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1121 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1122 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1123 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1124 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1125 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1126 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1127 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1129 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1130 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1131 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1132 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1133 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1134 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1135 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1136 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1137 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1139 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1140 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1141 r700
->viewport
[id
].enabled
= GL_TRUE
;
1144 void r700SetRenderTarget(context_t
*context
, int id
)
1146 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1148 struct radeon_renderbuffer
*rrb
;
1149 unsigned int nPitchInPixel
;
1151 /* screen/window/view */
1152 SETfield(r700
->CB_TARGET_MASK
.u32All
, 0xF, (4 * id
), TARGET0_ENABLE_mask
);
1154 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1155 if (!rrb
|| !rrb
->bo
) {
1156 fprintf(stderr
, "no rrb\n");
1161 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= context
->radeon
.state
.color
.draw_offset
;
1163 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1164 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1165 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1166 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1167 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
1168 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= 0;
1169 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
1170 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ARRAY_LINEAR_GENERAL
,
1171 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
1174 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_8_8_8_8
,
1175 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1176 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT
, COMP_SWAP_shift
, COMP_SWAP_mask
);
1180 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_5_6_5
,
1181 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1182 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT_REV
,
1183 COMP_SWAP_shift
, COMP_SWAP_mask
);
1185 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SOURCE_FORMAT_bit
);
1186 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, BLEND_CLAMP_bit
);
1187 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
1189 r700
->render_target
[id
].enabled
= GL_TRUE
;
1192 void r700SetDepthTarget(context_t
*context
)
1194 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1196 struct radeon_renderbuffer
*rrb
;
1197 unsigned int nPitchInPixel
;
1200 r700
->DB_DEPTH_SIZE
.u32All
= 0;
1201 r700
->DB_DEPTH_BASE
.u32All
= 0;
1202 r700
->DB_DEPTH_INFO
.u32All
= 0;
1204 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1205 r700
->DB_DEPTH_VIEW
.u32All
= 0;
1206 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1207 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1208 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1209 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1210 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1211 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1212 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1213 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1214 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1216 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1217 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1218 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1219 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1220 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1222 rrb
= radeon_get_depthbuffer(&context
->radeon
);
1226 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1228 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1229 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1230 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1231 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
); /* size in pixel / 64 - 1 */
1235 switch (GL_CONTEXT(context
)->Visual
.depthBits
)
1239 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_8_24
,
1240 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1243 fprintf(stderr
, "Error: Unsupported depth %d... exiting\n",
1244 GL_CONTEXT(context
)->Visual
.depthBits
);
1250 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_16
,
1251 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1253 SETfield(r700
->DB_DEPTH_INFO
.u32All
, ARRAY_2D_TILED_THIN1
,
1254 DB_DEPTH_INFO__ARRAY_MODE_shift
, DB_DEPTH_INFO__ARRAY_MODE_mask
);
1255 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1258 static void r700InitSQConfig(GLcontext
* ctx
)
1260 context_t
*context
= R700_CONTEXT(ctx
);
1261 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1275 int num_ps_stack_entries
;
1276 int num_vs_stack_entries
;
1277 int num_gs_stack_entries
;
1278 int num_es_stack_entries
;
1285 switch (context
->radeon
.radeonScreen
->chip_family
) {
1286 case CHIP_FAMILY_R600
:
1292 num_ps_threads
= 136;
1293 num_vs_threads
= 48;
1296 num_ps_stack_entries
= 128;
1297 num_vs_stack_entries
= 128;
1298 num_gs_stack_entries
= 0;
1299 num_es_stack_entries
= 0;
1301 case CHIP_FAMILY_RV630
:
1302 case CHIP_FAMILY_RV635
:
1308 num_ps_threads
= 144;
1309 num_vs_threads
= 40;
1312 num_ps_stack_entries
= 40;
1313 num_vs_stack_entries
= 40;
1314 num_gs_stack_entries
= 32;
1315 num_es_stack_entries
= 16;
1317 case CHIP_FAMILY_RV610
:
1318 case CHIP_FAMILY_RV620
:
1319 case CHIP_FAMILY_RS780
:
1326 num_ps_threads
= 136;
1327 num_vs_threads
= 48;
1330 num_ps_stack_entries
= 40;
1331 num_vs_stack_entries
= 40;
1332 num_gs_stack_entries
= 32;
1333 num_es_stack_entries
= 16;
1335 case CHIP_FAMILY_RV670
:
1341 num_ps_threads
= 136;
1342 num_vs_threads
= 48;
1345 num_ps_stack_entries
= 40;
1346 num_vs_stack_entries
= 40;
1347 num_gs_stack_entries
= 32;
1348 num_es_stack_entries
= 16;
1350 case CHIP_FAMILY_RV770
:
1356 num_ps_threads
= 188;
1357 num_vs_threads
= 60;
1360 num_ps_stack_entries
= 256;
1361 num_vs_stack_entries
= 256;
1362 num_gs_stack_entries
= 0;
1363 num_es_stack_entries
= 0;
1365 case CHIP_FAMILY_RV730
:
1366 case CHIP_FAMILY_RV740
:
1372 num_ps_threads
= 188;
1373 num_vs_threads
= 60;
1376 num_ps_stack_entries
= 128;
1377 num_vs_stack_entries
= 128;
1378 num_gs_stack_entries
= 0;
1379 num_es_stack_entries
= 0;
1381 case CHIP_FAMILY_RV710
:
1387 num_ps_threads
= 144;
1388 num_vs_threads
= 48;
1391 num_ps_stack_entries
= 128;
1392 num_vs_stack_entries
= 128;
1393 num_gs_stack_entries
= 0;
1394 num_es_stack_entries
= 0;
1398 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1399 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1400 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1401 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1402 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1403 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1405 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1406 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1407 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1408 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1409 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1410 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1411 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1413 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1414 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1415 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1416 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1417 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1419 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1420 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1421 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1423 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1424 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1425 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1426 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1427 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1428 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1429 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1430 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1431 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1433 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1434 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1435 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1436 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1437 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1439 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1440 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1441 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1442 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1443 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1448 * Calculate initial hardware state and register state functions.
1449 * Assumes that the command buffer and state atoms have been
1450 * initialized already.
1452 void r700InitState(GLcontext
* ctx
) //-------------------
1454 context_t
*context
= R700_CONTEXT(ctx
);
1456 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1458 r700
->TA_CNTL_AUX
.u32All
= 0;
1459 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1460 r700
->VC_ENHANCE
.u32All
= 0;
1461 r700
->DB_WATERMARKS
.u32All
= 0;
1462 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1463 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1464 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1465 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1466 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1467 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1468 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1469 r700
->DB_DEBUG
.u32All
= 0x82000000;
1470 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1472 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1473 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1474 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1477 /* Turn off vgt reuse */
1478 r700
->VGT_REUSE_OFF
.u32All
= 0;
1479 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1481 /* Specify offsetting and clamp values for vertices */
1482 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1483 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1484 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1486 /* Specify the number of instances */
1487 r700
->VGT_DMA_NUM_INSTANCES
.u32All
= 1;
1489 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1491 /* default shader connections. */
1492 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1493 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1495 r700
->SPI_PS_INPUT_CNTL_0
.u32All
= 0x00000800;
1496 r700
->SPI_PS_INPUT_CNTL_1
.u32All
= 0x00000801;
1497 r700
->SPI_PS_INPUT_CNTL_2
.u32All
= 0x00000802;
1499 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1500 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1501 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1503 r700SetBlendState(ctx
);
1504 r700SetLogicOpState(ctx
);
1506 r700
->DB_SHADER_CONTROL
.u32All
= 0;
1507 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1510 r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
= 0x0;
1512 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
,
1513 ((RADEONDRIPtr
)(context
->radeon
.radeonScreen
->driScreen
->pDevPriv
))->width
,
1514 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1515 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
,
1516 ((RADEONDRIPtr
)(context
->radeon
.radeonScreen
->driScreen
->pDevPriv
))->height
,
1517 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1519 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1520 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1521 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1523 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1524 r700
->PA_SC_EDGERULE
.u32All
= 0;
1526 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1528 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1529 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1530 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1531 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1533 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1534 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1535 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1538 /* Do scale XY and Z by 1/W0. */
1539 r700
->bEnablePerspective
= GL_TRUE
;
1540 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1541 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1542 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1544 /* Enable viewport scaling for all three axis */
1545 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1546 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1547 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1548 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1549 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1550 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1552 /* Set up point sizes and min/max values */
1553 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, 0x8,
1554 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
1555 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, 0x8,
1556 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
1557 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1558 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1560 /* GL uses last vtx for flat shading components */
1561 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1563 /* Set up line control */
1564 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
, 0x8,
1565 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1567 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1568 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1569 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1571 /* Set up vertex control */
1572 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1573 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1574 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1575 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1576 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1578 /* to 1.0 = no guard band */
1579 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1580 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1581 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1582 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1585 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1586 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1587 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1588 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1589 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1590 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1591 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1593 /* Disable color compares */
1594 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1595 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1596 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1597 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1598 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1599 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1601 /* Zero out source */
1602 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1604 /* Put a compare color in for error checking */
1605 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1607 /* Set up color compare mask */
1608 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1610 /* default color mask */
1611 SETfield(r700
->CB_SHADER_MASK
.u32All
, 0xF, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
1613 /* Enable all samples for multi-sample anti-aliasing */
1614 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1616 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1618 r700
->SX_MISC
.u32All
= 0;
1620 r700InitSQConfig(ctx
);
1623 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1625 functions
->UpdateState
= r700InvalidateState
;
1626 functions
->AlphaFunc
= r700AlphaFunc
;
1627 functions
->BlendColor
= r700BlendColor
;
1628 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1629 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1630 functions
->Enable
= r700Enable
;
1631 functions
->ColorMask
= r700ColorMask
;
1632 functions
->DepthFunc
= r700DepthFunc
;
1633 functions
->DepthMask
= r700DepthMask
;
1634 functions
->CullFace
= r700CullFace
;
1635 functions
->Fogfv
= r700Fogfv
;
1636 functions
->FrontFace
= r700FrontFace
;
1637 functions
->ShadeModel
= r700ShadeModel
;
1638 functions
->LogicOpcode
= r700LogicOpcode
;
1640 /* ARB_point_parameters */
1641 functions
->PointParameterfv
= r700PointParameter
;
1643 /* Stencil related */
1644 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1645 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1646 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1648 /* Viewport related */
1649 functions
->Viewport
= r700Viewport
;
1650 functions
->DepthRange
= r700DepthRange
;
1651 functions
->PointSize
= r700PointSize
;
1652 functions
->LineWidth
= r700LineWidth
;
1653 functions
->LineStipple
= r700LineStipple
;
1655 functions
->PolygonOffset
= r700PolygonOffset
;
1656 functions
->PolygonMode
= r700PolygonMode
;
1658 functions
->RenderMode
= r700RenderMode
;
1660 functions
->ClipPlane
= r700ClipPlane
;
1662 functions
->Scissor
= radeonScissor
;
1664 functions
->DrawBuffer
= radeonDrawBuffer
;
1665 functions
->ReadBuffer
= radeonReadBuffer
;