2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
34 #include "main/simple_list.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast/swrast.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/api_arrayelt.h"
41 #include "main/framebuffer.h"
43 #include "shader/prog_parameter.h"
44 #include "shader/prog_statevars.h"
47 #include "r600_context.h"
49 #include "r700_state.h"
51 #include "r700_fragprog.h"
52 #include "r700_vertprog.h"
54 void r600UpdateTextureState(GLcontext
* ctx
);
55 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
56 static void r700UpdatePolygonMode(GLcontext
* ctx
);
57 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
58 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
59 static void r700UpdateWindow(GLcontext
* ctx
, int id
);
61 void r700UpdateShaders(GLcontext
* ctx
)
63 context_t
*context
= R700_CONTEXT(ctx
);
65 /* should only happenen once, just after context is created */
66 /* TODO: shouldn't we fallback to sw here? */
67 if (!ctx
->FragmentProgram
._Current
) {
68 fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
72 r700SelectFragmentShader(ctx
);
74 r700SelectVertexShader(ctx
);
75 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
76 context
->radeon
.NewGLState
= 0;
80 * To correctly position primitives:
82 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
84 context_t
*context
= R700_CONTEXT(ctx
);
85 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
86 __DRIdrawable
*dPriv
= radeon_get_drawable(&context
->radeon
);
87 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
88 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
89 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
92 GLfloat tx
= v
[MAT_TX
] + xoffset
;
93 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
95 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
96 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
97 /* Note: this should also modify whatever data the context reset
100 R600_STATECHANGE(context
, vpt
);
101 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
102 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
105 radeonUpdateScissor(ctx
);
108 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
110 struct r700_fragment_program
*fp
=
111 (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
112 struct gl_program_parameter_list
*paramList
;
114 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
117 if (!ctx
->FragmentProgram
._Current
|| !fp
)
120 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
125 _mesa_load_state_parameters(ctx
, paramList
);
130 * Called by Mesa after an internal state update.
132 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
134 context_t
*context
= R700_CONTEXT(ctx
);
136 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
138 _swrast_InvalidateState(ctx
, new_state
);
139 _swsetup_InvalidateState(ctx
, new_state
);
140 _vbo_InvalidateState(ctx
, new_state
);
141 _tnl_InvalidateState(ctx
, new_state
);
142 _ae_invalidate_state(ctx
, new_state
);
144 if (new_state
& _NEW_BUFFERS
) {
145 _mesa_update_framebuffer(ctx
);
146 /* this updates the DrawBuffer's Width/Height if it's a FBO */
147 _mesa_update_draw_buffer_bounds(ctx
);
149 R600_STATECHANGE(context
, cb_target
);
150 R600_STATECHANGE(context
, db_target
);
153 if (new_state
& (_NEW_LIGHT
)) {
154 R600_STATECHANGE(context
, su
);
155 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
)
156 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
158 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
161 r700UpdateStateParameters(ctx
, new_state
);
163 R600_STATECHANGE(context
, cl
);
164 R600_STATECHANGE(context
, spi
);
166 if(GL_TRUE
== r700
->bEnablePerspective
)
168 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
169 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
170 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
172 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
174 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
175 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
179 /* For orthogonal case. */
180 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
181 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
183 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
185 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
186 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
189 context
->radeon
.NewGLState
|= new_state
;
192 static void r700SetDBRenderState(GLcontext
* ctx
)
194 context_t
*context
= R700_CONTEXT(ctx
);
195 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
196 struct r700_fragment_program
*fp
= (struct r700_fragment_program
*)
197 (ctx
->FragmentProgram
._Current
);
199 R600_STATECHANGE(context
, db
);
201 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
202 SETfield(r700
->DB_SHADER_CONTROL
.u32All
, EARLY_Z_THEN_LATE_Z
, Z_ORDER_shift
, Z_ORDER_mask
);
203 /* XXX need to enable htile for hiz/s */
204 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
205 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
206 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
208 if (context
->radeon
.query
.current
)
210 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
211 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
213 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, PERFECT_ZPASS_COUNTS_bit
);
218 CLEARbit(r700
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
219 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
221 CLEARbit(r700
->DB_RENDER_CONTROL
.u32All
, PERFECT_ZPASS_COUNTS_bit
);
227 if (fp
->r700Shader
.killIsUsed
)
229 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, KILL_ENABLE_bit
);
233 CLEARbit(r700
->DB_SHADER_CONTROL
.u32All
, KILL_ENABLE_bit
);
236 if (fp
->r700Shader
.depthIsExported
)
238 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, Z_EXPORT_ENABLE_bit
);
242 CLEARbit(r700
->DB_SHADER_CONTROL
.u32All
, Z_EXPORT_ENABLE_bit
);
247 void r700UpdateShaderStates(GLcontext
* ctx
)
249 r700SetDBRenderState(ctx
);
250 r600UpdateTextureState(ctx
);
253 static void r700SetDepthState(GLcontext
* ctx
)
255 context_t
*context
= R700_CONTEXT(ctx
);
256 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
258 R600_STATECHANGE(context
, db
);
262 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
265 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
269 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
272 switch (ctx
->Depth
.Func
)
275 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
276 ZFUNC_shift
, ZFUNC_mask
);
279 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
280 ZFUNC_shift
, ZFUNC_mask
);
283 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
284 ZFUNC_shift
, ZFUNC_mask
);
287 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
288 ZFUNC_shift
, ZFUNC_mask
);
291 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
292 ZFUNC_shift
, ZFUNC_mask
);
295 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
296 ZFUNC_shift
, ZFUNC_mask
);
299 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
300 ZFUNC_shift
, ZFUNC_mask
);
303 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
304 ZFUNC_shift
, ZFUNC_mask
);
307 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
308 ZFUNC_shift
, ZFUNC_mask
);
314 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
315 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
319 static void r700SetAlphaState(GLcontext
* ctx
)
321 context_t
*context
= R700_CONTEXT(ctx
);
322 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
323 uint32_t alpha_func
= REF_ALWAYS
;
324 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
326 R600_STATECHANGE(context
, sx
);
328 switch (ctx
->Color
.AlphaFunc
) {
330 alpha_func
= REF_NEVER
;
333 alpha_func
= REF_LESS
;
336 alpha_func
= REF_EQUAL
;
339 alpha_func
= REF_LEQUAL
;
342 alpha_func
= REF_GREATER
;
345 alpha_func
= REF_NOTEQUAL
;
348 alpha_func
= REF_GEQUAL
;
351 /*alpha_func = REF_ALWAYS; */
352 really_enabled
= GL_FALSE
;
356 if (really_enabled
) {
357 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
358 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
359 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
360 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
362 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
367 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
371 r700SetAlphaState(ctx
);
375 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
377 context_t
*context
= R700_CONTEXT(ctx
);
378 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
380 R600_STATECHANGE(context
, blnd_clr
);
382 r700
->CB_BLEND_RED
.f32All
= cf
[0];
383 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
384 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
385 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
388 static int blend_factor(GLenum factor
, GLboolean is_src
)
398 return BLEND_DST_COLOR
;
400 case GL_ONE_MINUS_DST_COLOR
:
401 return BLEND_ONE_MINUS_DST_COLOR
;
404 return BLEND_SRC_COLOR
;
406 case GL_ONE_MINUS_SRC_COLOR
:
407 return BLEND_ONE_MINUS_SRC_COLOR
;
410 return BLEND_SRC_ALPHA
;
412 case GL_ONE_MINUS_SRC_ALPHA
:
413 return BLEND_ONE_MINUS_SRC_ALPHA
;
416 return BLEND_DST_ALPHA
;
418 case GL_ONE_MINUS_DST_ALPHA
:
419 return BLEND_ONE_MINUS_DST_ALPHA
;
421 case GL_SRC_ALPHA_SATURATE
:
422 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
424 case GL_CONSTANT_COLOR
:
425 return BLEND_CONSTANT_COLOR
;
427 case GL_ONE_MINUS_CONSTANT_COLOR
:
428 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
430 case GL_CONSTANT_ALPHA
:
431 return BLEND_CONSTANT_ALPHA
;
433 case GL_ONE_MINUS_CONSTANT_ALPHA
:
434 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
437 fprintf(stderr
, "unknown blend factor %x\n", factor
);
438 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
443 static void r700SetBlendState(GLcontext
* ctx
)
445 context_t
*context
= R700_CONTEXT(ctx
);
446 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
448 uint32_t blend_reg
= 0, eqn
, eqnA
;
450 R600_STATECHANGE(context
, blnd
);
452 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
454 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
456 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
458 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
460 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
462 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
464 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
465 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
466 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
468 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
473 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
474 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
476 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
477 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
479 switch (ctx
->Color
.BlendEquationRGB
) {
481 eqn
= COMB_DST_PLUS_SRC
;
483 case GL_FUNC_SUBTRACT
:
484 eqn
= COMB_SRC_MINUS_DST
;
486 case GL_FUNC_REVERSE_SUBTRACT
:
487 eqn
= COMB_DST_MINUS_SRC
;
490 eqn
= COMB_MIN_DST_SRC
;
493 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
496 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
499 eqn
= COMB_MAX_DST_SRC
;
502 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
505 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
510 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
511 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
515 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
518 blend_factor(ctx
->Color
.BlendSrcA
, GL_TRUE
),
519 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
521 blend_factor(ctx
->Color
.BlendDstA
, GL_FALSE
),
522 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
524 switch (ctx
->Color
.BlendEquationA
) {
526 eqnA
= COMB_DST_PLUS_SRC
;
528 case GL_FUNC_SUBTRACT
:
529 eqnA
= COMB_SRC_MINUS_DST
;
531 case GL_FUNC_REVERSE_SUBTRACT
:
532 eqnA
= COMB_DST_MINUS_SRC
;
535 eqnA
= COMB_MIN_DST_SRC
;
538 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
541 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
544 eqnA
= COMB_MAX_DST_SRC
;
547 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
550 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
554 "[%s:%u] Invalid A blend equation (0x%04x).\n",
555 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
560 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
562 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
564 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
565 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
567 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
568 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
570 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
571 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
575 static void r700BlendEquationSeparate(GLcontext
* ctx
,
576 GLenum modeRGB
, GLenum modeA
) //-----------------
578 r700SetBlendState(ctx
);
581 static void r700BlendFuncSeparate(GLcontext
* ctx
,
582 GLenum sfactorRGB
, GLenum dfactorRGB
,
583 GLenum sfactorA
, GLenum dfactorA
) //------------------------
585 r700SetBlendState(ctx
);
589 * Translate LogicOp enums into hardware representation.
591 static GLuint
translate_logicop(GLenum logicop
)
600 case GL_COPY_INVERTED
:
620 case GL_AND_INVERTED
:
627 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
633 * Used internally to update the r300->hw hardware state to match the
634 * current OpenGL state.
636 static void r700SetLogicOpState(GLcontext
*ctx
)
638 context_t
*context
= R700_CONTEXT(ctx
);
639 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
641 R600_STATECHANGE(context
, blnd
);
643 if (RGBA_LOGICOP_ENABLED(ctx
))
644 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
645 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
647 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
651 * Called by Mesa when an application program changes the LogicOp state
654 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
656 if (RGBA_LOGICOP_ENABLED(ctx
))
657 r700SetLogicOpState(ctx
);
660 static void r700UpdateCulling(GLcontext
* ctx
)
662 context_t
*context
= R700_CONTEXT(ctx
);
663 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
665 R600_STATECHANGE(context
, su
);
667 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
668 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
669 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
671 if (ctx
->Polygon
.CullFlag
)
673 switch (ctx
->Polygon
.CullFaceMode
)
676 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
677 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
680 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
681 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
683 case GL_FRONT_AND_BACK
:
684 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
685 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
688 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
689 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
694 switch (ctx
->Polygon
.FrontFace
)
697 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
700 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
703 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
707 /* Winding is inverted when rendering to FBO */
708 if (ctx
->DrawBuffer
&& ctx
->DrawBuffer
->Name
)
709 r700
->PA_SU_SC_MODE_CNTL
.u32All
^= FACE_bit
;
712 static void r700UpdateLineStipple(GLcontext
* ctx
)
714 context_t
*context
= R700_CONTEXT(ctx
);
715 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
717 R600_STATECHANGE(context
, sc
);
719 if (ctx
->Line
.StippleFlag
)
721 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
725 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
729 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
731 context_t
*context
= R700_CONTEXT(ctx
);
743 r700SetAlphaState(ctx
);
745 case GL_COLOR_LOGIC_OP
:
746 r700SetLogicOpState(ctx
);
747 /* fall-through, because logic op overrides blending */
749 r700SetBlendState(ctx
);
757 r700SetClipPlaneState(ctx
, cap
, state
);
760 r700SetDepthState(ctx
);
762 case GL_STENCIL_TEST
:
763 r700SetStencilState(ctx
, state
);
766 r700UpdateCulling(ctx
);
768 case GL_POLYGON_OFFSET_POINT
:
769 case GL_POLYGON_OFFSET_LINE
:
770 case GL_POLYGON_OFFSET_FILL
:
771 r700SetPolygonOffsetState(ctx
, state
);
773 case GL_SCISSOR_TEST
:
774 radeon_firevertices(&context
->radeon
);
775 context
->radeon
.state
.scissor
.enabled
= state
;
776 radeonUpdateScissor(ctx
);
778 case GL_LINE_STIPPLE
:
779 r700UpdateLineStipple(ctx
);
782 r700UpdateWindow(ctx
, 0);
791 * Handle glColorMask()
793 static void r700ColorMask(GLcontext
* ctx
,
794 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
796 context_t
*context
= R700_CONTEXT(ctx
);
797 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
798 unsigned int mask
= ((r
? 1 : 0) |
803 if (mask
!= r700
->CB_TARGET_MASK
.u32All
) {
804 R600_STATECHANGE(context
, cb
);
805 SETfield(r700
->CB_TARGET_MASK
.u32All
, mask
, TARGET0_ENABLE_shift
, TARGET0_ENABLE_mask
);
810 * Change the depth testing function.
812 * \note Mesa already filters redundant calls to this function.
814 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
816 r700SetDepthState(ctx
);
820 * Enable/Disable depth writing.
822 * \note Mesa already filters redundant calls to this function.
824 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
826 r700SetDepthState(ctx
);
830 * Change the culling mode.
832 * \note Mesa already filters redundant calls to this function.
834 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
836 r700UpdateCulling(ctx
);
839 /* =============================================================
842 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
847 * Change the polygon orientation.
849 * \note Mesa already filters redundant calls to this function.
851 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
853 r700UpdateCulling(ctx
);
854 r700UpdatePolygonMode(ctx
);
857 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
859 context_t
*context
= R700_CONTEXT(ctx
);
860 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
862 R600_STATECHANGE(context
, spi
);
864 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
867 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
870 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
877 /* =============================================================
880 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
882 context_t
*context
= R700_CONTEXT(ctx
);
883 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
885 R600_STATECHANGE(context
, su
);
887 /* We need to clamp to user defined range here, because
888 * the HW clamping happens only for per vertex point size. */
889 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
891 /* same size limits for AA, non-AA points */
892 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
894 /* format is 12.4 fixed point */
895 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
896 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
897 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
898 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
902 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
904 context_t
*context
= R700_CONTEXT(ctx
);
905 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
907 R600_STATECHANGE(context
, su
);
909 /* format is 12.4 fixed point */
911 case GL_POINT_SIZE_MIN
:
912 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 8.0),
913 MIN_SIZE_shift
, MIN_SIZE_mask
);
914 r700PointSize(ctx
, ctx
->Point
.Size
);
916 case GL_POINT_SIZE_MAX
:
917 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 8.0),
918 MAX_SIZE_shift
, MAX_SIZE_mask
);
919 r700PointSize(ctx
, ctx
->Point
.Size
);
921 case GL_POINT_DISTANCE_ATTENUATION
:
923 case GL_POINT_FADE_THRESHOLD_SIZE
:
930 static int translate_stencil_func(int func
)
953 static int translate_stencil_op(int op
)
961 return STENCIL_REPLACE
;
963 return STENCIL_INCR_CLAMP
;
965 return STENCIL_DECR_CLAMP
;
966 case GL_INCR_WRAP_EXT
:
967 return STENCIL_INCR_WRAP
;
968 case GL_DECR_WRAP_EXT
:
969 return STENCIL_DECR_WRAP
;
971 return STENCIL_INVERT
;
973 WARN_ONCE("Do not know how to translate stencil op");
979 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
981 context_t
*context
= R700_CONTEXT(ctx
);
982 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
983 GLboolean hw_stencil
= GL_FALSE
;
985 if (ctx
->DrawBuffer
) {
986 struct radeon_renderbuffer
*rrbStencil
987 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
988 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
992 R600_STATECHANGE(context
, db
);
994 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
995 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
997 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
1001 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
1002 GLenum func
, GLint ref
, GLuint mask
) //---------------------
1004 context_t
*context
= R700_CONTEXT(ctx
);
1005 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1006 const unsigned back
= ctx
->Stencil
._BackFace
;
1008 R600_STATECHANGE(context
, stencil
);
1009 R600_STATECHANGE(context
, db
);
1012 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
1013 STENCILREF_shift
, STENCILREF_mask
);
1014 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
1015 STENCILMASK_shift
, STENCILMASK_mask
);
1017 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
1018 STENCILFUNC_shift
, STENCILFUNC_mask
);
1021 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
1022 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
1023 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
1024 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
1026 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
1027 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
1031 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
1033 context_t
*context
= R700_CONTEXT(ctx
);
1034 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1035 const unsigned back
= ctx
->Stencil
._BackFace
;
1037 R600_STATECHANGE(context
, stencil
);
1040 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
1041 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
1044 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
1045 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1049 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
1050 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
1052 context_t
*context
= R700_CONTEXT(ctx
);
1053 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1054 const unsigned back
= ctx
->Stencil
._BackFace
;
1056 R600_STATECHANGE(context
, db
);
1058 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1059 STENCILFAIL_shift
, STENCILFAIL_mask
);
1060 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1061 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1062 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1063 STENCILZPASS_shift
, STENCILZPASS_mask
);
1065 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1066 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1067 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1068 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1069 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1070 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1073 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1075 context_t
*context
= R700_CONTEXT(ctx
);
1076 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1077 __DRIdrawable
*dPriv
= radeon_get_drawable(&context
->radeon
);
1078 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1079 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1080 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1081 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1082 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1083 GLfloat y_scale
, y_bias
;
1085 if (render_to_fbo
) {
1093 GLfloat sx
= v
[MAT_SX
];
1094 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1095 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1096 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1097 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1098 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1100 R600_STATECHANGE(context
, vpt
);
1101 R600_STATECHANGE(context
, cl
);
1103 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1104 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1106 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1107 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1109 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1110 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1112 if (ctx
->Transform
.DepthClamp
) {
1113 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= MIN2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
1114 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= MAX2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
1115 SETbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_NEAR_DISABLE_bit
);
1116 SETbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_FAR_DISABLE_bit
);
1118 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= 0.0;
1119 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= 1.0;
1120 CLEARbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_NEAR_DISABLE_bit
);
1121 CLEARbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_FAR_DISABLE_bit
);
1124 r700
->viewport
[id
].enabled
= GL_TRUE
;
1126 r700SetScissor(context
);
1130 static void r700Viewport(GLcontext
* ctx
,
1134 GLsizei height
) //--------------------
1136 r700UpdateWindow(ctx
, 0);
1138 radeon_viewport(ctx
, x
, y
, width
, height
);
1141 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1143 r700UpdateWindow(ctx
, 0);
1146 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1148 context_t
*context
= R700_CONTEXT(ctx
);
1149 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1150 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1152 R600_STATECHANGE(context
, su
);
1154 if (lineWidth
> 0xFFFF)
1156 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1157 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1160 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1162 context_t
*context
= R700_CONTEXT(ctx
);
1163 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1165 R600_STATECHANGE(context
, sc
);
1167 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1168 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1169 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1172 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1174 context_t
*context
= R700_CONTEXT(ctx
);
1175 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1177 R600_STATECHANGE(context
, su
);
1180 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1181 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1182 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1184 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1185 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1186 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1190 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1192 context_t
*context
= R700_CONTEXT(ctx
);
1193 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1194 GLfloat constant
= units
;
1197 R600_STATECHANGE(context
, poly
);
1199 switch (ctx
->Visual
.depthBits
) {
1211 SETfield(r700
->PA_SU_POLY_OFFSET_DB_FMT_CNTL
.u32All
, depth
,
1212 POLY_OFFSET_NEG_NUM_DB_BITS_shift
, POLY_OFFSET_NEG_NUM_DB_BITS_mask
);
1213 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1214 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1215 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1216 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1217 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1220 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1222 context_t
*context
= R700_CONTEXT(ctx
);
1223 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1225 R600_STATECHANGE(context
, su
);
1227 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1229 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1230 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1231 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1234 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1235 * correctly by selecting the correct front and back face
1237 f
= ctx
->Polygon
.FrontMode
;
1238 b
= ctx
->Polygon
.BackMode
;
1240 /* Enable polygon mode */
1241 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1245 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1246 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1249 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1250 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1253 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1254 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1260 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1261 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1264 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1265 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1268 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1269 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1275 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1280 r700UpdatePolygonMode(ctx
);
1283 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1287 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1289 context_t
*context
= R700_CONTEXT(ctx
);
1290 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1294 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1295 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1297 R600_STATECHANGE(context
, ucp
);
1299 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1300 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1301 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1302 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1305 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1307 context_t
*context
= R700_CONTEXT(ctx
);
1308 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1311 p
= cap
- GL_CLIP_PLANE0
;
1313 R600_STATECHANGE(context
, cl
);
1316 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1317 r700
->ucp
[p
].enabled
= GL_TRUE
;
1318 r700ClipPlane(ctx
, cap
, NULL
);
1320 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1321 r700
->ucp
[p
].enabled
= GL_FALSE
;
1325 void r700SetScissor(context_t
*context
) //---------------
1327 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1328 unsigned x1
, y1
, x2
, y2
;
1330 struct radeon_renderbuffer
*rrb
;
1332 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1333 if (!rrb
|| !rrb
->bo
) {
1336 if (context
->radeon
.state
.scissor
.enabled
) {
1337 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1338 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1339 x2
= context
->radeon
.state
.scissor
.rect
.x2
;
1340 y2
= context
->radeon
.state
.scissor
.rect
.y2
;
1341 /* r600 has exclusive BR scissors */
1342 if (context
->radeon
.radeonScreen
->kernel_mm
) {
1347 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1350 x2
= rrb
->base
.Width
;
1351 y2
= rrb
->base
.Height
;
1355 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1356 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1360 R600_STATECHANGE(context
, scissor
);
1363 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1364 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1365 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1366 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1367 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1369 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1370 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1371 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1372 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1375 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1376 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1377 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1378 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1379 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1381 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1382 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1383 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1384 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1387 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1388 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1389 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1390 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1391 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1392 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1393 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1394 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1396 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1397 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1398 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1399 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1400 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1401 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1403 /* more....2d clip */
1404 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1405 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1406 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1407 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1408 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1409 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1410 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1411 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1412 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1414 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1415 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1416 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1417 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1418 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1419 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1420 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1421 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1422 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1424 r700
->viewport
[id
].enabled
= GL_TRUE
;
1427 static void r700InitSQConfig(GLcontext
* ctx
)
1429 context_t
*context
= R700_CONTEXT(ctx
);
1430 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1444 int num_ps_stack_entries
;
1445 int num_vs_stack_entries
;
1446 int num_gs_stack_entries
;
1447 int num_es_stack_entries
;
1449 R600_STATECHANGE(context
, sq
);
1456 switch (context
->radeon
.radeonScreen
->chip_family
) {
1457 case CHIP_FAMILY_R600
:
1463 num_ps_threads
= 136;
1464 num_vs_threads
= 48;
1467 num_ps_stack_entries
= 128;
1468 num_vs_stack_entries
= 128;
1469 num_gs_stack_entries
= 0;
1470 num_es_stack_entries
= 0;
1472 case CHIP_FAMILY_RV630
:
1473 case CHIP_FAMILY_RV635
:
1479 num_ps_threads
= 144;
1480 num_vs_threads
= 40;
1483 num_ps_stack_entries
= 40;
1484 num_vs_stack_entries
= 40;
1485 num_gs_stack_entries
= 32;
1486 num_es_stack_entries
= 16;
1488 case CHIP_FAMILY_RV610
:
1489 case CHIP_FAMILY_RV620
:
1490 case CHIP_FAMILY_RS780
:
1491 case CHIP_FAMILY_RS880
:
1498 num_ps_threads
= 136;
1499 num_vs_threads
= 48;
1502 num_ps_stack_entries
= 40;
1503 num_vs_stack_entries
= 40;
1504 num_gs_stack_entries
= 32;
1505 num_es_stack_entries
= 16;
1507 case CHIP_FAMILY_RV670
:
1513 num_ps_threads
= 136;
1514 num_vs_threads
= 48;
1517 num_ps_stack_entries
= 40;
1518 num_vs_stack_entries
= 40;
1519 num_gs_stack_entries
= 32;
1520 num_es_stack_entries
= 16;
1522 case CHIP_FAMILY_RV770
:
1528 num_ps_threads
= 188;
1529 num_vs_threads
= 60;
1532 num_ps_stack_entries
= 256;
1533 num_vs_stack_entries
= 256;
1534 num_gs_stack_entries
= 0;
1535 num_es_stack_entries
= 0;
1537 case CHIP_FAMILY_RV730
:
1538 case CHIP_FAMILY_RV740
:
1544 num_ps_threads
= 188;
1545 num_vs_threads
= 60;
1548 num_ps_stack_entries
= 128;
1549 num_vs_stack_entries
= 128;
1550 num_gs_stack_entries
= 0;
1551 num_es_stack_entries
= 0;
1553 case CHIP_FAMILY_RV710
:
1559 num_ps_threads
= 144;
1560 num_vs_threads
= 48;
1563 num_ps_stack_entries
= 128;
1564 num_vs_stack_entries
= 128;
1565 num_gs_stack_entries
= 0;
1566 num_es_stack_entries
= 0;
1570 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1571 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1572 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1573 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1574 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1575 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1576 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1578 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1579 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1580 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1581 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1582 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, vs_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1583 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, gs_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1584 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, es_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1586 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1587 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1588 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1589 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1590 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1592 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1593 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1594 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1596 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1597 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1598 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1599 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1600 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1601 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1602 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1603 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1604 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1606 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1607 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1608 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1609 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1610 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1612 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1613 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1614 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1615 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1616 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1621 * Calculate initial hardware state and register state functions.
1622 * Assumes that the command buffer and state atoms have been
1623 * initialized already.
1625 void r700InitState(GLcontext
* ctx
) //-------------------
1627 context_t
*context
= R700_CONTEXT(ctx
);
1628 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1631 r700
->TA_CNTL_AUX
.u32All
= 0;
1632 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1633 r700
->VC_ENHANCE
.u32All
= 0;
1634 r700
->DB_WATERMARKS
.u32All
= 0;
1635 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1636 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1637 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1638 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1639 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1640 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1641 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1642 r700
->DB_DEBUG
.u32All
= 0x82000000;
1643 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1645 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1646 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1647 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1650 /* Turn off vgt reuse */
1651 r700
->VGT_REUSE_OFF
.u32All
= 0;
1652 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1654 /* Specify offsetting and clamp values for vertices */
1655 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1656 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1657 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1659 /* default shader connections. */
1660 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1661 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1662 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1663 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1665 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1666 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1667 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1669 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1670 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1671 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1673 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1674 r700
->PA_SC_EDGERULE
.u32All
= 0;
1676 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1678 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1679 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1680 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1681 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1683 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1684 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1685 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1688 /* Do scale XY and Z by 1/W0. */
1689 r700
->bEnablePerspective
= GL_TRUE
;
1690 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1691 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1692 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1694 /* Enable viewport scaling for all three axis */
1695 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1696 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1697 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1698 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1699 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1700 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1702 /* GL uses last vtx for flat shading components */
1703 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1705 /* Set up vertex control */
1706 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1707 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1708 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1709 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1710 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1712 /* to 1.0 = no guard band */
1713 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1714 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1715 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1716 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1718 /* Enable all samples for multi-sample anti-aliasing */
1719 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1721 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1723 r700
->SX_MISC
.u32All
= 0;
1725 r700InitSQConfig(ctx
);
1728 ctx
->Color
.ColorMask
[0][RCOMP
],
1729 ctx
->Color
.ColorMask
[0][GCOMP
],
1730 ctx
->Color
.ColorMask
[0][BCOMP
],
1731 ctx
->Color
.ColorMask
[0][ACOMP
]);
1733 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1734 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1735 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1736 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1737 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1738 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1739 r700SetDBRenderState(ctx
);
1741 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1742 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1743 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1744 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1745 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1748 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1749 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1750 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1751 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1752 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1753 ctx
->Stencil
.ZFailFunc
[0],
1754 ctx
->Stencil
.ZPassFunc
[0]);
1756 r700UpdateCulling(ctx
);
1758 r700SetBlendState(ctx
);
1759 r700SetLogicOpState(ctx
);
1761 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1762 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1764 r700PointSize(ctx
, 1.0);
1766 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1767 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1769 r700LineWidth(ctx
, 1.0);
1771 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1772 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1773 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1775 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1776 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1777 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1778 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1779 ctx
->Polygon
.OffsetUnits
);
1780 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1781 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1782 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1785 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1787 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1788 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1789 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1790 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1791 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1792 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1793 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1795 /* Disable color compares */
1796 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1797 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1798 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1799 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1800 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1801 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1803 /* Zero out source */
1804 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1806 /* Put a compare color in for error checking */
1807 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1809 /* Set up color compare mask */
1810 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1812 /* screen/window/view */
1813 SETfield(r700
->CB_SHADER_MASK
.u32All
, 0xF, (4 * id
), OUTPUT0_ENABLE_mask
);
1815 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1819 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1821 functions
->UpdateState
= r700InvalidateState
;
1822 functions
->AlphaFunc
= r700AlphaFunc
;
1823 functions
->BlendColor
= r700BlendColor
;
1824 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1825 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1826 functions
->Enable
= r700Enable
;
1827 functions
->ColorMask
= r700ColorMask
;
1828 functions
->DepthFunc
= r700DepthFunc
;
1829 functions
->DepthMask
= r700DepthMask
;
1830 functions
->CullFace
= r700CullFace
;
1831 functions
->Fogfv
= r700Fogfv
;
1832 functions
->FrontFace
= r700FrontFace
;
1833 functions
->ShadeModel
= r700ShadeModel
;
1834 functions
->LogicOpcode
= r700LogicOpcode
;
1836 /* ARB_point_parameters */
1837 functions
->PointParameterfv
= r700PointParameter
;
1839 /* Stencil related */
1840 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1841 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1842 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1844 /* Viewport related */
1845 functions
->Viewport
= r700Viewport
;
1846 functions
->DepthRange
= r700DepthRange
;
1847 functions
->PointSize
= r700PointSize
;
1848 functions
->LineWidth
= r700LineWidth
;
1849 functions
->LineStipple
= r700LineStipple
;
1851 functions
->PolygonOffset
= r700PolygonOffset
;
1852 functions
->PolygonMode
= r700PolygonMode
;
1854 functions
->RenderMode
= r700RenderMode
;
1856 functions
->ClipPlane
= r700ClipPlane
;
1858 functions
->Scissor
= radeonScissor
;
1860 functions
->DrawBuffer
= radeonDrawBuffer
;
1861 functions
->ReadBuffer
= radeonReadBuffer
;