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Merge branch 'gallium-vertexelementcso'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast/swrast.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/api_arrayelt.h"
41 #include "main/framebuffer.h"
42
43 #include "shader/prog_parameter.h"
44 #include "shader/prog_statevars.h"
45 #include "vbo/vbo.h"
46
47 #include "r600_context.h"
48
49 #include "r700_state.h"
50
51 #include "r700_fragprog.h"
52 #include "r700_vertprog.h"
53
54 void r600UpdateTextureState(GLcontext * ctx);
55 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
56 static void r700UpdatePolygonMode(GLcontext * ctx);
57 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
58 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
59 static void r700UpdateWindow(GLcontext * ctx, int id);
60
61 void r700UpdateShaders(GLcontext * ctx)
62 {
63 context_t *context = R700_CONTEXT(ctx);
64
65 /* should only happenen once, just after context is created */
66 /* TODO: shouldn't we fallback to sw here? */
67 if (!ctx->FragmentProgram._Current) {
68 fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
69 return;
70 }
71
72 r700SelectFragmentShader(ctx);
73
74 r700SelectVertexShader(ctx);
75 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
76 context->radeon.NewGLState = 0;
77 }
78
79 /*
80 * To correctly position primitives:
81 */
82 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
83 {
84 context_t *context = R700_CONTEXT(ctx);
85 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
86 __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
87 GLfloat xoffset = (GLfloat) dPriv->x;
88 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
89 const GLfloat *v = ctx->Viewport._WindowMap.m;
90 int id = 0;
91
92 GLfloat tx = v[MAT_TX] + xoffset;
93 GLfloat ty = (-v[MAT_TY]) + yoffset;
94
95 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
96 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
97 /* Note: this should also modify whatever data the context reset
98 * code uses...
99 */
100 R600_STATECHANGE(context, vpt);
101 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
102 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
103 }
104
105 radeonUpdateScissor(ctx);
106 }
107
108 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
109 {
110 struct r700_fragment_program *fp =
111 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
112 struct gl_program_parameter_list *paramList;
113
114 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
115 return;
116
117 if (!ctx->FragmentProgram._Current || !fp)
118 return;
119
120 paramList = ctx->FragmentProgram._Current->Base.Parameters;
121
122 if (!paramList)
123 return;
124
125 _mesa_load_state_parameters(ctx, paramList);
126
127 }
128
129 /**
130 * Called by Mesa after an internal state update.
131 */
132 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
133 {
134 context_t *context = R700_CONTEXT(ctx);
135
136 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
137
138 _swrast_InvalidateState(ctx, new_state);
139 _swsetup_InvalidateState(ctx, new_state);
140 _vbo_InvalidateState(ctx, new_state);
141 _tnl_InvalidateState(ctx, new_state);
142 _ae_invalidate_state(ctx, new_state);
143
144 if (new_state & _NEW_BUFFERS) {
145 _mesa_update_framebuffer(ctx);
146 /* this updates the DrawBuffer's Width/Height if it's a FBO */
147 _mesa_update_draw_buffer_bounds(ctx);
148
149 R600_STATECHANGE(context, cb_target);
150 R600_STATECHANGE(context, db_target);
151 }
152
153 if (new_state & (_NEW_LIGHT)) {
154 R600_STATECHANGE(context, su);
155 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
156 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
157 else
158 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
159 }
160
161 r700UpdateStateParameters(ctx, new_state);
162
163 R600_STATECHANGE(context, cl);
164 R600_STATECHANGE(context, spi);
165
166 if(GL_TRUE == r700->bEnablePerspective)
167 {
168 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
169 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
170 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
171
172 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
173
174 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
175 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
176 }
177 else
178 {
179 /* For orthogonal case. */
180 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
181 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
182
183 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
184
185 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
186 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
187 }
188
189 context->radeon.NewGLState |= new_state;
190 }
191
192 static void r700SetDBRenderState(GLcontext * ctx)
193 {
194 context_t *context = R700_CONTEXT(ctx);
195 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
196 struct r700_fragment_program *fp = (struct r700_fragment_program *)
197 (ctx->FragmentProgram._Current);
198
199 R600_STATECHANGE(context, db);
200
201 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
202 SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
203 /* XXX need to enable htile for hiz/s */
204 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
205 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
206 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
207
208 if (context->radeon.query.current)
209 {
210 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
211 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
212 {
213 SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
214 }
215 }
216 else
217 {
218 CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
219 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
220 {
221 CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
222 }
223 }
224
225 if (fp)
226 {
227 if (fp->r700Shader.killIsUsed)
228 {
229 SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
230 }
231 else
232 {
233 CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
234 }
235
236 if (fp->r700Shader.depthIsExported)
237 {
238 SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
239 }
240 else
241 {
242 CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
243 }
244 }
245 }
246
247 void r700UpdateShaderStates(GLcontext * ctx)
248 {
249 r700SetDBRenderState(ctx);
250 r600UpdateTextureState(ctx);
251 }
252
253 static void r700SetDepthState(GLcontext * ctx)
254 {
255 context_t *context = R700_CONTEXT(ctx);
256 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
257
258 R600_STATECHANGE(context, db);
259
260 if (ctx->Depth.Test)
261 {
262 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
263 if (ctx->Depth.Mask)
264 {
265 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
266 }
267 else
268 {
269 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
270 }
271
272 switch (ctx->Depth.Func)
273 {
274 case GL_NEVER:
275 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
276 ZFUNC_shift, ZFUNC_mask);
277 break;
278 case GL_LESS:
279 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
280 ZFUNC_shift, ZFUNC_mask);
281 break;
282 case GL_EQUAL:
283 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
284 ZFUNC_shift, ZFUNC_mask);
285 break;
286 case GL_LEQUAL:
287 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
288 ZFUNC_shift, ZFUNC_mask);
289 break;
290 case GL_GREATER:
291 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
292 ZFUNC_shift, ZFUNC_mask);
293 break;
294 case GL_NOTEQUAL:
295 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
296 ZFUNC_shift, ZFUNC_mask);
297 break;
298 case GL_GEQUAL:
299 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
300 ZFUNC_shift, ZFUNC_mask);
301 break;
302 case GL_ALWAYS:
303 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
304 ZFUNC_shift, ZFUNC_mask);
305 break;
306 default:
307 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
308 ZFUNC_shift, ZFUNC_mask);
309 break;
310 }
311 }
312 else
313 {
314 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
315 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
316 }
317 }
318
319 static void r700SetAlphaState(GLcontext * ctx)
320 {
321 context_t *context = R700_CONTEXT(ctx);
322 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
323 uint32_t alpha_func = REF_ALWAYS;
324 GLboolean really_enabled = ctx->Color.AlphaEnabled;
325
326 R600_STATECHANGE(context, sx);
327
328 switch (ctx->Color.AlphaFunc) {
329 case GL_NEVER:
330 alpha_func = REF_NEVER;
331 break;
332 case GL_LESS:
333 alpha_func = REF_LESS;
334 break;
335 case GL_EQUAL:
336 alpha_func = REF_EQUAL;
337 break;
338 case GL_LEQUAL:
339 alpha_func = REF_LEQUAL;
340 break;
341 case GL_GREATER:
342 alpha_func = REF_GREATER;
343 break;
344 case GL_NOTEQUAL:
345 alpha_func = REF_NOTEQUAL;
346 break;
347 case GL_GEQUAL:
348 alpha_func = REF_GEQUAL;
349 break;
350 case GL_ALWAYS:
351 /*alpha_func = REF_ALWAYS; */
352 really_enabled = GL_FALSE;
353 break;
354 }
355
356 if (really_enabled) {
357 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
358 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
359 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
360 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
361 } else {
362 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
363 }
364
365 }
366
367 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
368 {
369 (void)func;
370 (void)ref;
371 r700SetAlphaState(ctx);
372 }
373
374
375 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
376 {
377 context_t *context = R700_CONTEXT(ctx);
378 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
379
380 R600_STATECHANGE(context, blnd_clr);
381
382 r700->CB_BLEND_RED.f32All = cf[0];
383 r700->CB_BLEND_GREEN.f32All = cf[1];
384 r700->CB_BLEND_BLUE.f32All = cf[2];
385 r700->CB_BLEND_ALPHA.f32All = cf[3];
386 }
387
388 static int blend_factor(GLenum factor, GLboolean is_src)
389 {
390 switch (factor) {
391 case GL_ZERO:
392 return BLEND_ZERO;
393 break;
394 case GL_ONE:
395 return BLEND_ONE;
396 break;
397 case GL_DST_COLOR:
398 return BLEND_DST_COLOR;
399 break;
400 case GL_ONE_MINUS_DST_COLOR:
401 return BLEND_ONE_MINUS_DST_COLOR;
402 break;
403 case GL_SRC_COLOR:
404 return BLEND_SRC_COLOR;
405 break;
406 case GL_ONE_MINUS_SRC_COLOR:
407 return BLEND_ONE_MINUS_SRC_COLOR;
408 break;
409 case GL_SRC_ALPHA:
410 return BLEND_SRC_ALPHA;
411 break;
412 case GL_ONE_MINUS_SRC_ALPHA:
413 return BLEND_ONE_MINUS_SRC_ALPHA;
414 break;
415 case GL_DST_ALPHA:
416 return BLEND_DST_ALPHA;
417 break;
418 case GL_ONE_MINUS_DST_ALPHA:
419 return BLEND_ONE_MINUS_DST_ALPHA;
420 break;
421 case GL_SRC_ALPHA_SATURATE:
422 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
423 break;
424 case GL_CONSTANT_COLOR:
425 return BLEND_CONSTANT_COLOR;
426 break;
427 case GL_ONE_MINUS_CONSTANT_COLOR:
428 return BLEND_ONE_MINUS_CONSTANT_COLOR;
429 break;
430 case GL_CONSTANT_ALPHA:
431 return BLEND_CONSTANT_ALPHA;
432 break;
433 case GL_ONE_MINUS_CONSTANT_ALPHA:
434 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
435 break;
436 default:
437 fprintf(stderr, "unknown blend factor %x\n", factor);
438 return (is_src) ? BLEND_ONE : BLEND_ZERO;
439 break;
440 }
441 }
442
443 static void r700SetBlendState(GLcontext * ctx)
444 {
445 context_t *context = R700_CONTEXT(ctx);
446 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
447 int id = 0;
448 uint32_t blend_reg = 0, eqn, eqnA;
449
450 R600_STATECHANGE(context, blnd);
451
452 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
453 SETfield(blend_reg,
454 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
455 SETfield(blend_reg,
456 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
457 SETfield(blend_reg,
458 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
459 SETfield(blend_reg,
460 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
461 SETfield(blend_reg,
462 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
463 SETfield(blend_reg,
464 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
465 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
466 r700->CB_BLEND_CONTROL.u32All = blend_reg;
467 else
468 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
469 return;
470 }
471
472 SETfield(blend_reg,
473 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
474 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
475 SETfield(blend_reg,
476 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
477 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
478
479 switch (ctx->Color.BlendEquationRGB) {
480 case GL_FUNC_ADD:
481 eqn = COMB_DST_PLUS_SRC;
482 break;
483 case GL_FUNC_SUBTRACT:
484 eqn = COMB_SRC_MINUS_DST;
485 break;
486 case GL_FUNC_REVERSE_SUBTRACT:
487 eqn = COMB_DST_MINUS_SRC;
488 break;
489 case GL_MIN:
490 eqn = COMB_MIN_DST_SRC;
491 SETfield(blend_reg,
492 BLEND_ONE,
493 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
494 SETfield(blend_reg,
495 BLEND_ONE,
496 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
497 break;
498 case GL_MAX:
499 eqn = COMB_MAX_DST_SRC;
500 SETfield(blend_reg,
501 BLEND_ONE,
502 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
503 SETfield(blend_reg,
504 BLEND_ONE,
505 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
506 break;
507
508 default:
509 fprintf(stderr,
510 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
511 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
512 return;
513 }
514 SETfield(blend_reg,
515 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
516
517 SETfield(blend_reg,
518 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
519 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
520 SETfield(blend_reg,
521 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
522 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
523
524 switch (ctx->Color.BlendEquationA) {
525 case GL_FUNC_ADD:
526 eqnA = COMB_DST_PLUS_SRC;
527 break;
528 case GL_FUNC_SUBTRACT:
529 eqnA = COMB_SRC_MINUS_DST;
530 break;
531 case GL_FUNC_REVERSE_SUBTRACT:
532 eqnA = COMB_DST_MINUS_SRC;
533 break;
534 case GL_MIN:
535 eqnA = COMB_MIN_DST_SRC;
536 SETfield(blend_reg,
537 BLEND_ONE,
538 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
539 SETfield(blend_reg,
540 BLEND_ONE,
541 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
542 break;
543 case GL_MAX:
544 eqnA = COMB_MAX_DST_SRC;
545 SETfield(blend_reg,
546 BLEND_ONE,
547 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
548 SETfield(blend_reg,
549 BLEND_ONE,
550 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
551 break;
552 default:
553 fprintf(stderr,
554 "[%s:%u] Invalid A blend equation (0x%04x).\n",
555 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
556 return;
557 }
558
559 SETfield(blend_reg,
560 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
561
562 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
563
564 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
565 r700->CB_BLEND_CONTROL.u32All = blend_reg;
566 else {
567 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
568 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
569 }
570 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
571 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
572
573 }
574
575 static void r700BlendEquationSeparate(GLcontext * ctx,
576 GLenum modeRGB, GLenum modeA) //-----------------
577 {
578 r700SetBlendState(ctx);
579 }
580
581 static void r700BlendFuncSeparate(GLcontext * ctx,
582 GLenum sfactorRGB, GLenum dfactorRGB,
583 GLenum sfactorA, GLenum dfactorA) //------------------------
584 {
585 r700SetBlendState(ctx);
586 }
587
588 /**
589 * Translate LogicOp enums into hardware representation.
590 */
591 static GLuint translate_logicop(GLenum logicop)
592 {
593 switch (logicop) {
594 case GL_CLEAR:
595 return 0x00;
596 case GL_SET:
597 return 0xff;
598 case GL_COPY:
599 return 0xcc;
600 case GL_COPY_INVERTED:
601 return 0x33;
602 case GL_NOOP:
603 return 0xaa;
604 case GL_INVERT:
605 return 0x55;
606 case GL_AND:
607 return 0x88;
608 case GL_NAND:
609 return 0x77;
610 case GL_OR:
611 return 0xee;
612 case GL_NOR:
613 return 0x11;
614 case GL_XOR:
615 return 0x66;
616 case GL_EQUIV:
617 return 0xaa;
618 case GL_AND_REVERSE:
619 return 0x44;
620 case GL_AND_INVERTED:
621 return 0x22;
622 case GL_OR_REVERSE:
623 return 0xdd;
624 case GL_OR_INVERTED:
625 return 0xbb;
626 default:
627 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
628 return 0xcc;
629 }
630 }
631
632 /**
633 * Used internally to update the r300->hw hardware state to match the
634 * current OpenGL state.
635 */
636 static void r700SetLogicOpState(GLcontext *ctx)
637 {
638 context_t *context = R700_CONTEXT(ctx);
639 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
640
641 R600_STATECHANGE(context, blnd);
642
643 if (RGBA_LOGICOP_ENABLED(ctx))
644 SETfield(r700->CB_COLOR_CONTROL.u32All,
645 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
646 else
647 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
648 }
649
650 /**
651 * Called by Mesa when an application program changes the LogicOp state
652 * via glLogicOp.
653 */
654 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
655 {
656 if (RGBA_LOGICOP_ENABLED(ctx))
657 r700SetLogicOpState(ctx);
658 }
659
660 static void r700UpdateCulling(GLcontext * ctx)
661 {
662 context_t *context = R700_CONTEXT(ctx);
663 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
664
665 R600_STATECHANGE(context, su);
666
667 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
668 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
669 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
670
671 if (ctx->Polygon.CullFlag)
672 {
673 switch (ctx->Polygon.CullFaceMode)
674 {
675 case GL_FRONT:
676 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
677 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
678 break;
679 case GL_BACK:
680 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
681 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
682 break;
683 case GL_FRONT_AND_BACK:
684 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
685 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
686 break;
687 default:
688 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
689 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
690 break;
691 }
692 }
693
694 switch (ctx->Polygon.FrontFace)
695 {
696 case GL_CW:
697 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
698 break;
699 case GL_CCW:
700 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
701 break;
702 default:
703 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
704 break;
705 }
706
707 /* Winding is inverted when rendering to FBO */
708 if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
709 r700->PA_SU_SC_MODE_CNTL.u32All ^= FACE_bit;
710 }
711
712 static void r700UpdateLineStipple(GLcontext * ctx)
713 {
714 context_t *context = R700_CONTEXT(ctx);
715 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
716
717 R600_STATECHANGE(context, sc);
718
719 if (ctx->Line.StippleFlag)
720 {
721 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
722 }
723 else
724 {
725 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
726 }
727 }
728
729 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
730 {
731 context_t *context = R700_CONTEXT(ctx);
732
733 switch (cap) {
734 case GL_TEXTURE_1D:
735 case GL_TEXTURE_2D:
736 case GL_TEXTURE_3D:
737 /* empty */
738 break;
739 case GL_FOG:
740 /* empty */
741 break;
742 case GL_ALPHA_TEST:
743 r700SetAlphaState(ctx);
744 break;
745 case GL_COLOR_LOGIC_OP:
746 r700SetLogicOpState(ctx);
747 /* fall-through, because logic op overrides blending */
748 case GL_BLEND:
749 r700SetBlendState(ctx);
750 break;
751 case GL_CLIP_PLANE0:
752 case GL_CLIP_PLANE1:
753 case GL_CLIP_PLANE2:
754 case GL_CLIP_PLANE3:
755 case GL_CLIP_PLANE4:
756 case GL_CLIP_PLANE5:
757 r700SetClipPlaneState(ctx, cap, state);
758 break;
759 case GL_DEPTH_TEST:
760 r700SetDepthState(ctx);
761 break;
762 case GL_STENCIL_TEST:
763 r700SetStencilState(ctx, state);
764 break;
765 case GL_CULL_FACE:
766 r700UpdateCulling(ctx);
767 break;
768 case GL_POLYGON_OFFSET_POINT:
769 case GL_POLYGON_OFFSET_LINE:
770 case GL_POLYGON_OFFSET_FILL:
771 r700SetPolygonOffsetState(ctx, state);
772 break;
773 case GL_SCISSOR_TEST:
774 radeon_firevertices(&context->radeon);
775 context->radeon.state.scissor.enabled = state;
776 radeonUpdateScissor(ctx);
777 break;
778 case GL_LINE_STIPPLE:
779 r700UpdateLineStipple(ctx);
780 break;
781 case GL_DEPTH_CLAMP:
782 r700UpdateWindow(ctx, 0);
783 break;
784 default:
785 break;
786 }
787
788 }
789
790 /**
791 * Handle glColorMask()
792 */
793 static void r700ColorMask(GLcontext * ctx,
794 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
795 {
796 context_t *context = R700_CONTEXT(ctx);
797 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
798 unsigned int mask = ((r ? 1 : 0) |
799 (g ? 2 : 0) |
800 (b ? 4 : 0) |
801 (a ? 8 : 0));
802
803 if (mask != r700->CB_TARGET_MASK.u32All) {
804 R600_STATECHANGE(context, cb);
805 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
806 }
807 }
808
809 /**
810 * Change the depth testing function.
811 *
812 * \note Mesa already filters redundant calls to this function.
813 */
814 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
815 {
816 r700SetDepthState(ctx);
817 }
818
819 /**
820 * Enable/Disable depth writing.
821 *
822 * \note Mesa already filters redundant calls to this function.
823 */
824 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
825 {
826 r700SetDepthState(ctx);
827 }
828
829 /**
830 * Change the culling mode.
831 *
832 * \note Mesa already filters redundant calls to this function.
833 */
834 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
835 {
836 r700UpdateCulling(ctx);
837 }
838
839 /* =============================================================
840 * Fog
841 */
842 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
843 {
844 }
845
846 /**
847 * Change the polygon orientation.
848 *
849 * \note Mesa already filters redundant calls to this function.
850 */
851 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
852 {
853 r700UpdateCulling(ctx);
854 r700UpdatePolygonMode(ctx);
855 }
856
857 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
858 {
859 context_t *context = R700_CONTEXT(ctx);
860 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
861
862 R600_STATECHANGE(context, spi);
863
864 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
865 switch (mode) {
866 case GL_FLAT:
867 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
868 break;
869 case GL_SMOOTH:
870 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
871 break;
872 default:
873 return;
874 }
875 }
876
877 /* =============================================================
878 * Point state
879 */
880 static void r700PointSize(GLcontext * ctx, GLfloat size)
881 {
882 context_t *context = R700_CONTEXT(ctx);
883 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
884
885 R600_STATECHANGE(context, su);
886
887 /* We need to clamp to user defined range here, because
888 * the HW clamping happens only for per vertex point size. */
889 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
890
891 /* same size limits for AA, non-AA points */
892 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
893
894 /* format is 12.4 fixed point */
895 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
896 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
897 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
898 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
899
900 }
901
902 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
903 {
904 context_t *context = R700_CONTEXT(ctx);
905 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
906
907 R600_STATECHANGE(context, su);
908
909 /* format is 12.4 fixed point */
910 switch (pname) {
911 case GL_POINT_SIZE_MIN:
912 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
913 MIN_SIZE_shift, MIN_SIZE_mask);
914 r700PointSize(ctx, ctx->Point.Size);
915 break;
916 case GL_POINT_SIZE_MAX:
917 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
918 MAX_SIZE_shift, MAX_SIZE_mask);
919 r700PointSize(ctx, ctx->Point.Size);
920 break;
921 case GL_POINT_DISTANCE_ATTENUATION:
922 break;
923 case GL_POINT_FADE_THRESHOLD_SIZE:
924 break;
925 default:
926 break;
927 }
928 }
929
930 static int translate_stencil_func(int func)
931 {
932 switch (func) {
933 case GL_NEVER:
934 return REF_NEVER;
935 case GL_LESS:
936 return REF_LESS;
937 case GL_EQUAL:
938 return REF_EQUAL;
939 case GL_LEQUAL:
940 return REF_LEQUAL;
941 case GL_GREATER:
942 return REF_GREATER;
943 case GL_NOTEQUAL:
944 return REF_NOTEQUAL;
945 case GL_GEQUAL:
946 return REF_GEQUAL;
947 case GL_ALWAYS:
948 return REF_ALWAYS;
949 }
950 return 0;
951 }
952
953 static int translate_stencil_op(int op)
954 {
955 switch (op) {
956 case GL_KEEP:
957 return STENCIL_KEEP;
958 case GL_ZERO:
959 return STENCIL_ZERO;
960 case GL_REPLACE:
961 return STENCIL_REPLACE;
962 case GL_INCR:
963 return STENCIL_INCR_CLAMP;
964 case GL_DECR:
965 return STENCIL_DECR_CLAMP;
966 case GL_INCR_WRAP_EXT:
967 return STENCIL_INCR_WRAP;
968 case GL_DECR_WRAP_EXT:
969 return STENCIL_DECR_WRAP;
970 case GL_INVERT:
971 return STENCIL_INVERT;
972 default:
973 WARN_ONCE("Do not know how to translate stencil op");
974 return STENCIL_KEEP;
975 }
976 return 0;
977 }
978
979 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
980 {
981 context_t *context = R700_CONTEXT(ctx);
982 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
983 GLboolean hw_stencil = GL_FALSE;
984
985 if (ctx->DrawBuffer) {
986 struct radeon_renderbuffer *rrbStencil
987 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
988 hw_stencil = (rrbStencil && rrbStencil->bo);
989 }
990
991 if (hw_stencil) {
992 R600_STATECHANGE(context, db);
993 if (state) {
994 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
995 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
996 } else
997 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
998 }
999 }
1000
1001 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
1002 GLenum func, GLint ref, GLuint mask) //---------------------
1003 {
1004 context_t *context = R700_CONTEXT(ctx);
1005 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1006 const unsigned back = ctx->Stencil._BackFace;
1007
1008 R600_STATECHANGE(context, stencil);
1009 R600_STATECHANGE(context, db);
1010
1011 //front
1012 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1013 STENCILREF_shift, STENCILREF_mask);
1014 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1015 STENCILMASK_shift, STENCILMASK_mask);
1016
1017 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1018 STENCILFUNC_shift, STENCILFUNC_mask);
1019
1020 //back
1021 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1022 STENCILREF_BF_shift, STENCILREF_BF_mask);
1023 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1024 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1025
1026 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1027 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1028
1029 }
1030
1031 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1032 {
1033 context_t *context = R700_CONTEXT(ctx);
1034 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1035 const unsigned back = ctx->Stencil._BackFace;
1036
1037 R600_STATECHANGE(context, stencil);
1038
1039 // front
1040 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1041 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1042
1043 // back
1044 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1045 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1046
1047 }
1048
1049 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1050 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1051 {
1052 context_t *context = R700_CONTEXT(ctx);
1053 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1054 const unsigned back = ctx->Stencil._BackFace;
1055
1056 R600_STATECHANGE(context, db);
1057
1058 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1059 STENCILFAIL_shift, STENCILFAIL_mask);
1060 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1061 STENCILZFAIL_shift, STENCILZFAIL_mask);
1062 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1063 STENCILZPASS_shift, STENCILZPASS_mask);
1064
1065 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1066 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1067 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1068 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1069 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1070 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1071 }
1072
1073 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1074 {
1075 context_t *context = R700_CONTEXT(ctx);
1076 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1077 __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
1078 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1079 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1080 const GLfloat *v = ctx->Viewport._WindowMap.m;
1081 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1082 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1083 GLfloat y_scale, y_bias;
1084
1085 if (render_to_fbo) {
1086 y_scale = 1.0;
1087 y_bias = 0;
1088 } else {
1089 y_scale = -1.0;
1090 y_bias = yoffset;
1091 }
1092
1093 GLfloat sx = v[MAT_SX];
1094 GLfloat tx = v[MAT_TX] + xoffset;
1095 GLfloat sy = v[MAT_SY] * y_scale;
1096 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1097 GLfloat sz = v[MAT_SZ] * depthScale;
1098 GLfloat tz = v[MAT_TZ] * depthScale;
1099
1100 R600_STATECHANGE(context, vpt);
1101 R600_STATECHANGE(context, cl);
1102
1103 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1104 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1105
1106 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1107 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1108
1109 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1110 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1111
1112 if (ctx->Transform.DepthClamp) {
1113 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1114 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1115 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1116 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1117 } else {
1118 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1119 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1120 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1121 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1122 }
1123
1124 r700->viewport[id].enabled = GL_TRUE;
1125
1126 r700SetScissor(context);
1127 }
1128
1129
1130 static void r700Viewport(GLcontext * ctx,
1131 GLint x,
1132 GLint y,
1133 GLsizei width,
1134 GLsizei height) //--------------------
1135 {
1136 r700UpdateWindow(ctx, 0);
1137
1138 radeon_viewport(ctx, x, y, width, height);
1139 }
1140
1141 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1142 {
1143 r700UpdateWindow(ctx, 0);
1144 }
1145
1146 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1147 {
1148 context_t *context = R700_CONTEXT(ctx);
1149 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1150 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1151
1152 R600_STATECHANGE(context, su);
1153
1154 if (lineWidth > 0xFFFF)
1155 lineWidth = 0xFFFF;
1156 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1157 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1158 }
1159
1160 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1161 {
1162 context_t *context = R700_CONTEXT(ctx);
1163 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1164
1165 R600_STATECHANGE(context, sc);
1166
1167 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1168 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1169 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1170 }
1171
1172 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1173 {
1174 context_t *context = R700_CONTEXT(ctx);
1175 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1176
1177 R600_STATECHANGE(context, su);
1178
1179 if (state) {
1180 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1181 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1182 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1183 } else {
1184 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1185 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1186 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1187 }
1188 }
1189
1190 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1191 {
1192 context_t *context = R700_CONTEXT(ctx);
1193 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1194 GLfloat constant = units;
1195 GLchar depth = 0;
1196
1197 R600_STATECHANGE(context, poly);
1198
1199 switch (ctx->Visual.depthBits) {
1200 case 16:
1201 constant *= 4.0;
1202 depth = -16;
1203 break;
1204 case 24:
1205 constant *= 2.0;
1206 depth = -24;
1207 break;
1208 }
1209
1210 factor *= 12.0;
1211 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1212 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1213 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1214 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1215 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1216 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1217 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1218 }
1219
1220 static void r700UpdatePolygonMode(GLcontext * ctx)
1221 {
1222 context_t *context = R700_CONTEXT(ctx);
1223 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1224
1225 R600_STATECHANGE(context, su);
1226
1227 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1228
1229 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1230 if (ctx->Polygon.FrontMode != GL_FILL ||
1231 ctx->Polygon.BackMode != GL_FILL) {
1232 GLenum f, b;
1233
1234 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1235 * correctly by selecting the correct front and back face
1236 */
1237 f = ctx->Polygon.FrontMode;
1238 b = ctx->Polygon.BackMode;
1239
1240 /* Enable polygon mode */
1241 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1242
1243 switch (f) {
1244 case GL_LINE:
1245 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1246 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1247 break;
1248 case GL_POINT:
1249 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1250 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1251 break;
1252 case GL_FILL:
1253 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1254 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1255 break;
1256 }
1257
1258 switch (b) {
1259 case GL_LINE:
1260 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1261 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1262 break;
1263 case GL_POINT:
1264 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1265 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1266 break;
1267 case GL_FILL:
1268 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1269 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1270 break;
1271 }
1272 }
1273 }
1274
1275 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1276 {
1277 (void)face;
1278 (void)mode;
1279
1280 r700UpdatePolygonMode(ctx);
1281 }
1282
1283 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1284 {
1285 }
1286
1287 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1288 {
1289 context_t *context = R700_CONTEXT(ctx);
1290 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1291 GLint p;
1292 GLint *ip;
1293
1294 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1295 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1296
1297 R600_STATECHANGE(context, ucp);
1298
1299 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1300 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1301 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1302 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1303 }
1304
1305 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1306 {
1307 context_t *context = R700_CONTEXT(ctx);
1308 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1309 GLuint p;
1310
1311 p = cap - GL_CLIP_PLANE0;
1312
1313 R600_STATECHANGE(context, cl);
1314
1315 if (state) {
1316 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1317 r700->ucp[p].enabled = GL_TRUE;
1318 r700ClipPlane(ctx, cap, NULL);
1319 } else {
1320 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1321 r700->ucp[p].enabled = GL_FALSE;
1322 }
1323 }
1324
1325 void r700SetScissor(context_t *context) //---------------
1326 {
1327 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1328 unsigned x1, y1, x2, y2;
1329 int id = 0;
1330 struct radeon_renderbuffer *rrb;
1331
1332 rrb = radeon_get_colorbuffer(&context->radeon);
1333 if (!rrb || !rrb->bo) {
1334 return;
1335 }
1336 if (context->radeon.state.scissor.enabled) {
1337 x1 = context->radeon.state.scissor.rect.x1;
1338 y1 = context->radeon.state.scissor.rect.y1;
1339 x2 = context->radeon.state.scissor.rect.x2;
1340 y2 = context->radeon.state.scissor.rect.y2;
1341 /* r600 has exclusive BR scissors */
1342 if (context->radeon.radeonScreen->kernel_mm) {
1343 x2++;
1344 y2++;
1345 }
1346 } else {
1347 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1348 x1 = 0;
1349 y1 = 0;
1350 x2 = rrb->base.Width;
1351 y2 = rrb->base.Height;
1352 } else {
1353 x1 = rrb->dPriv->x;
1354 y1 = rrb->dPriv->y;
1355 x2 = rrb->dPriv->x + rrb->dPriv->w;
1356 y2 = rrb->dPriv->y + rrb->dPriv->h;
1357 }
1358 }
1359
1360 R600_STATECHANGE(context, scissor);
1361
1362 /* screen */
1363 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1364 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1365 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1366 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1367 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1368
1369 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1370 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1371 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1372 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1373
1374 /* window */
1375 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1376 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1377 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1378 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1379 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1380
1381 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1382 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1383 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1384 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1385
1386
1387 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1388 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1389 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1390 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1391 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1392 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1393 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1394 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1395
1396 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1397 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1398 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1399 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1400 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1401 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1402
1403 /* more....2d clip */
1404 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1405 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1406 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1407 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1408 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1409 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1410 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1411 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1412 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1413
1414 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1415 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1416 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1417 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1418 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1419 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1420 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1421 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1422 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1423
1424 r700->viewport[id].enabled = GL_TRUE;
1425 }
1426
1427 static void r700InitSQConfig(GLcontext * ctx)
1428 {
1429 context_t *context = R700_CONTEXT(ctx);
1430 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1431 int ps_prio;
1432 int vs_prio;
1433 int gs_prio;
1434 int es_prio;
1435 int num_ps_gprs;
1436 int num_vs_gprs;
1437 int num_gs_gprs;
1438 int num_es_gprs;
1439 int num_temp_gprs;
1440 int num_ps_threads;
1441 int num_vs_threads;
1442 int num_gs_threads;
1443 int num_es_threads;
1444 int num_ps_stack_entries;
1445 int num_vs_stack_entries;
1446 int num_gs_stack_entries;
1447 int num_es_stack_entries;
1448
1449 R600_STATECHANGE(context, sq);
1450
1451 // SQ
1452 ps_prio = 0;
1453 vs_prio = 1;
1454 gs_prio = 2;
1455 es_prio = 3;
1456 switch (context->radeon.radeonScreen->chip_family) {
1457 case CHIP_FAMILY_R600:
1458 num_ps_gprs = 192;
1459 num_vs_gprs = 56;
1460 num_temp_gprs = 4;
1461 num_gs_gprs = 0;
1462 num_es_gprs = 0;
1463 num_ps_threads = 136;
1464 num_vs_threads = 48;
1465 num_gs_threads = 4;
1466 num_es_threads = 4;
1467 num_ps_stack_entries = 128;
1468 num_vs_stack_entries = 128;
1469 num_gs_stack_entries = 0;
1470 num_es_stack_entries = 0;
1471 break;
1472 case CHIP_FAMILY_RV630:
1473 case CHIP_FAMILY_RV635:
1474 num_ps_gprs = 84;
1475 num_vs_gprs = 36;
1476 num_temp_gprs = 4;
1477 num_gs_gprs = 0;
1478 num_es_gprs = 0;
1479 num_ps_threads = 144;
1480 num_vs_threads = 40;
1481 num_gs_threads = 4;
1482 num_es_threads = 4;
1483 num_ps_stack_entries = 40;
1484 num_vs_stack_entries = 40;
1485 num_gs_stack_entries = 32;
1486 num_es_stack_entries = 16;
1487 break;
1488 case CHIP_FAMILY_RV610:
1489 case CHIP_FAMILY_RV620:
1490 case CHIP_FAMILY_RS780:
1491 case CHIP_FAMILY_RS880:
1492 default:
1493 num_ps_gprs = 84;
1494 num_vs_gprs = 36;
1495 num_temp_gprs = 4;
1496 num_gs_gprs = 0;
1497 num_es_gprs = 0;
1498 num_ps_threads = 136;
1499 num_vs_threads = 48;
1500 num_gs_threads = 4;
1501 num_es_threads = 4;
1502 num_ps_stack_entries = 40;
1503 num_vs_stack_entries = 40;
1504 num_gs_stack_entries = 32;
1505 num_es_stack_entries = 16;
1506 break;
1507 case CHIP_FAMILY_RV670:
1508 num_ps_gprs = 144;
1509 num_vs_gprs = 40;
1510 num_temp_gprs = 4;
1511 num_gs_gprs = 0;
1512 num_es_gprs = 0;
1513 num_ps_threads = 136;
1514 num_vs_threads = 48;
1515 num_gs_threads = 4;
1516 num_es_threads = 4;
1517 num_ps_stack_entries = 40;
1518 num_vs_stack_entries = 40;
1519 num_gs_stack_entries = 32;
1520 num_es_stack_entries = 16;
1521 break;
1522 case CHIP_FAMILY_RV770:
1523 num_ps_gprs = 192;
1524 num_vs_gprs = 56;
1525 num_temp_gprs = 4;
1526 num_gs_gprs = 0;
1527 num_es_gprs = 0;
1528 num_ps_threads = 188;
1529 num_vs_threads = 60;
1530 num_gs_threads = 0;
1531 num_es_threads = 0;
1532 num_ps_stack_entries = 256;
1533 num_vs_stack_entries = 256;
1534 num_gs_stack_entries = 0;
1535 num_es_stack_entries = 0;
1536 break;
1537 case CHIP_FAMILY_RV730:
1538 case CHIP_FAMILY_RV740:
1539 num_ps_gprs = 84;
1540 num_vs_gprs = 36;
1541 num_temp_gprs = 4;
1542 num_gs_gprs = 0;
1543 num_es_gprs = 0;
1544 num_ps_threads = 188;
1545 num_vs_threads = 60;
1546 num_gs_threads = 0;
1547 num_es_threads = 0;
1548 num_ps_stack_entries = 128;
1549 num_vs_stack_entries = 128;
1550 num_gs_stack_entries = 0;
1551 num_es_stack_entries = 0;
1552 break;
1553 case CHIP_FAMILY_RV710:
1554 num_ps_gprs = 192;
1555 num_vs_gprs = 56;
1556 num_temp_gprs = 4;
1557 num_gs_gprs = 0;
1558 num_es_gprs = 0;
1559 num_ps_threads = 144;
1560 num_vs_threads = 48;
1561 num_gs_threads = 0;
1562 num_es_threads = 0;
1563 num_ps_stack_entries = 128;
1564 num_vs_stack_entries = 128;
1565 num_gs_stack_entries = 0;
1566 num_es_stack_entries = 0;
1567 break;
1568 }
1569
1570 r700->sq_config.SQ_CONFIG.u32All = 0;
1571 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1572 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1573 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1574 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1575 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1576 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1577 else
1578 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1579 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1580 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1581 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1582 SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1583 SETfield(r700->sq_config.SQ_CONFIG.u32All, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1584 SETfield(r700->sq_config.SQ_CONFIG.u32All, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1585
1586 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1587 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1588 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1589 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1590 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1591
1592 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1593 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1594 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1595
1596 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1597 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1598 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1599 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1600 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1601 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1602 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1603 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1604 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1605
1606 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1607 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1608 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1609 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1610 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1611
1612 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1613 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1614 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1615 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1616 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1617
1618 }
1619
1620 /**
1621 * Calculate initial hardware state and register state functions.
1622 * Assumes that the command buffer and state atoms have been
1623 * initialized already.
1624 */
1625 void r700InitState(GLcontext * ctx) //-------------------
1626 {
1627 context_t *context = R700_CONTEXT(ctx);
1628 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1629 int id = 0;
1630
1631 r700->TA_CNTL_AUX.u32All = 0;
1632 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1633 r700->VC_ENHANCE.u32All = 0;
1634 r700->DB_WATERMARKS.u32All = 0;
1635 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1636 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1637 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1638 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1639 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1640 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1641 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1642 r700->DB_DEBUG.u32All = 0x82000000;
1643 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1644 } else {
1645 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1646 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1647 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1648 }
1649
1650 /* Turn off vgt reuse */
1651 r700->VGT_REUSE_OFF.u32All = 0;
1652 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1653
1654 /* Specify offsetting and clamp values for vertices */
1655 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1656 r700->VGT_MIN_VTX_INDX.u32All = 0;
1657 r700->VGT_INDX_OFFSET.u32All = 0;
1658
1659 /* default shader connections. */
1660 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1661 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1662 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1663 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1664
1665 r700->SPI_THREAD_GROUPING.u32All = 0;
1666 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1667 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1668
1669 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1670 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1671 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1672
1673 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1674 r700->PA_SC_EDGERULE.u32All = 0;
1675 else
1676 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1677
1678 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1679 r700->PA_SC_MODE_CNTL.u32All = 0;
1680 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1681 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1682 } else {
1683 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1684 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1685 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1686 }
1687
1688 /* Do scale XY and Z by 1/W0. */
1689 r700->bEnablePerspective = GL_TRUE;
1690 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1691 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1692 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1693
1694 /* Enable viewport scaling for all three axis */
1695 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1696 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1697 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1698 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1699 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1700 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1701
1702 /* GL uses last vtx for flat shading components */
1703 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1704
1705 /* Set up vertex control */
1706 r700->PA_SU_VTX_CNTL.u32All = 0;
1707 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1708 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1709 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1710 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1711
1712 /* to 1.0 = no guard band */
1713 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1714 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1715 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1716 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1717
1718 /* Enable all samples for multi-sample anti-aliasing */
1719 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1720 /* Turn off AA */
1721 r700->PA_SC_AA_CONFIG.u32All = 0;
1722
1723 r700->SX_MISC.u32All = 0;
1724
1725 r700InitSQConfig(ctx);
1726
1727 r700ColorMask(ctx,
1728 ctx->Color.ColorMask[0][RCOMP],
1729 ctx->Color.ColorMask[0][GCOMP],
1730 ctx->Color.ColorMask[0][BCOMP],
1731 ctx->Color.ColorMask[0][ACOMP]);
1732
1733 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1734 r700DepthMask(ctx, ctx->Depth.Mask);
1735 r700DepthFunc(ctx, ctx->Depth.Func);
1736 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1737 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1738 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1739 r700SetDBRenderState(ctx);
1740
1741 r700->DB_ALPHA_TO_MASK.u32All = 0;
1742 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1743 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1744 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1745 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1746
1747 /* stencil */
1748 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1749 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1750 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1751 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1752 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1753 ctx->Stencil.ZFailFunc[0],
1754 ctx->Stencil.ZPassFunc[0]);
1755
1756 r700UpdateCulling(ctx);
1757
1758 r700SetBlendState(ctx);
1759 r700SetLogicOpState(ctx);
1760
1761 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1762 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1763
1764 r700PointSize(ctx, 1.0);
1765
1766 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1767 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1768
1769 r700LineWidth(ctx, 1.0);
1770
1771 r700->PA_SC_LINE_CNTL.u32All = 0;
1772 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1773 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1774
1775 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1776 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1777 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1778 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1779 ctx->Polygon.OffsetUnits);
1780 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1781 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1782 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1783
1784 /* CB */
1785 r700BlendColor(ctx, ctx->Color.BlendColor);
1786
1787 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1788 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1789 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1790 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1791 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1792 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1793 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1794
1795 /* Disable color compares */
1796 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1797 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1798 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1799 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1800 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1801 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1802
1803 /* Zero out source */
1804 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1805
1806 /* Put a compare color in for error checking */
1807 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1808
1809 /* Set up color compare mask */
1810 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1811
1812 /* screen/window/view */
1813 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1814
1815 context->radeon.hw.all_dirty = GL_TRUE;
1816
1817 }
1818
1819 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1820 {
1821 functions->UpdateState = r700InvalidateState;
1822 functions->AlphaFunc = r700AlphaFunc;
1823 functions->BlendColor = r700BlendColor;
1824 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1825 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1826 functions->Enable = r700Enable;
1827 functions->ColorMask = r700ColorMask;
1828 functions->DepthFunc = r700DepthFunc;
1829 functions->DepthMask = r700DepthMask;
1830 functions->CullFace = r700CullFace;
1831 functions->Fogfv = r700Fogfv;
1832 functions->FrontFace = r700FrontFace;
1833 functions->ShadeModel = r700ShadeModel;
1834 functions->LogicOpcode = r700LogicOpcode;
1835
1836 /* ARB_point_parameters */
1837 functions->PointParameterfv = r700PointParameter;
1838
1839 /* Stencil related */
1840 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1841 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1842 functions->StencilOpSeparate = r700StencilOpSeparate;
1843
1844 /* Viewport related */
1845 functions->Viewport = r700Viewport;
1846 functions->DepthRange = r700DepthRange;
1847 functions->PointSize = r700PointSize;
1848 functions->LineWidth = r700LineWidth;
1849 functions->LineStipple = r700LineStipple;
1850
1851 functions->PolygonOffset = r700PolygonOffset;
1852 functions->PolygonMode = r700PolygonMode;
1853
1854 functions->RenderMode = r700RenderMode;
1855
1856 functions->ClipPlane = r700ClipPlane;
1857
1858 functions->Scissor = radeonScissor;
1859
1860 functions->DrawBuffer = radeonDrawBuffer;
1861 functions->ReadBuffer = radeonReadBuffer;
1862
1863 }
1864