2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
62 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
64 void r700SetDefaultStates(context_t
*context
) //--------------------
69 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
71 context_t
*context
= R700_CONTEXT(ctx
);
73 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
74 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
76 struct r700_vertex_program
*vp
;
79 if (context
->radeon
.NewGLState
)
81 context
->radeon
.NewGLState
= 0;
83 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
85 /* mat states from state var not array for sw */
86 dummy_attrib
[i
].stride
= 0;
88 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
89 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
92 _tnl_UpdateFixedFunctionProgram(ctx
);
94 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
96 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
99 r700SelectVertexShader(ctx
);
100 vp
= (struct r700_vertex_program
*)ctx
->VertexProgram
._Current
;
102 if (vp
->translated
== GL_FALSE
)
105 //fprintf(stderr, "Failing back to sw-tcl\n");
106 //hw_tcl_on = future_hw_tcl_on = 0;
107 //r300ResetHwState(rmesa);
109 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
114 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
118 * To correctly position primitives:
120 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
122 context_t
*context
= R700_CONTEXT(ctx
);
123 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
124 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
125 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
126 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
127 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
130 GLfloat tx
= v
[MAT_TX
] + xoffset
;
131 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
133 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
134 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
136 radeonUpdateScissor(ctx
);
140 * Tell the card where to render (offset, pitch).
141 * Effected by glDrawBuffer, etc
143 void r700UpdateDrawBuffer(GLcontext
* ctx
) /* TODO */ //---------------------
145 #if 0 /* to be enabled */
146 context_t
*context
= R700_CONTEXT(ctx
);
148 switch (ctx
->DrawBuffer
->_ColorDrawBufferIndexes
[0])
150 case BUFFER_FRONT_LEFT
:
151 context
->target
.rt
= context
->screen
->frontBuffer
;
153 case BUFFER_BACK_LEFT
:
154 context
->target
.rt
= context
->screen
->backBuffer
;
157 memset (&context
->target
.rt
, sizeof(context
->target
.rt
), 0);
159 #endif /* to be enabled */
162 static void r700FetchStateParameter(GLcontext
* ctx
,
163 const gl_state_index state
[STATE_LENGTH
],
166 context_t
*context
= R700_CONTEXT(ctx
);
171 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
173 struct r700_fragment_program
*fp
;
174 struct gl_program_parameter_list
*paramList
;
177 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
)))
180 fp
= (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
186 paramList
= fp
->mesa_program
.Base
.Parameters
;
193 for (i
= 0; i
< paramList
->NumParameters
; i
++)
195 if (paramList
->Parameters
[i
].Type
== PROGRAM_STATE_VAR
)
197 r700FetchStateParameter(ctx
,
198 paramList
->Parameters
[i
].
200 paramList
->ParameterValues
[i
]);
206 * Called by Mesa after an internal state update.
208 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
210 context_t
*context
= R700_CONTEXT(ctx
);
212 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
214 _swrast_InvalidateState(ctx
, new_state
);
215 _swsetup_InvalidateState(ctx
, new_state
);
216 _vbo_InvalidateState(ctx
, new_state
);
217 _tnl_InvalidateState(ctx
, new_state
);
218 _ae_invalidate_state(ctx
, new_state
);
220 if (new_state
& (_NEW_BUFFERS
| _NEW_COLOR
| _NEW_PIXEL
))
222 _mesa_update_framebuffer(ctx
);
223 /* this updates the DrawBuffer's Width/Height if it's a FBO */
224 _mesa_update_draw_buffer_bounds(ctx
);
226 r700UpdateDrawBuffer(ctx
);
229 r700UpdateStateParameters(ctx
, new_state
);
231 if(GL_TRUE
== r700
->bEnablePerspective
)
233 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
234 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
235 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
237 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
239 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
240 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
244 /* For orthogonal case. */
245 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
246 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
248 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
250 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
251 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
254 context
->radeon
.NewGLState
|= new_state
;
257 static void r700SetDepthState(GLcontext
* ctx
)
259 context_t
*context
= R700_CONTEXT(ctx
);
261 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
265 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
268 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
272 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
275 switch (ctx
->Depth
.Func
)
278 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
279 ZFUNC_shift
, ZFUNC_mask
);
282 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
283 ZFUNC_shift
, ZFUNC_mask
);
286 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
287 ZFUNC_shift
, ZFUNC_mask
);
290 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
291 ZFUNC_shift
, ZFUNC_mask
);
294 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
295 ZFUNC_shift
, ZFUNC_mask
);
298 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
299 ZFUNC_shift
, ZFUNC_mask
);
302 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
303 ZFUNC_shift
, ZFUNC_mask
);
306 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
307 ZFUNC_shift
, ZFUNC_mask
);
310 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
311 ZFUNC_shift
, ZFUNC_mask
);
317 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
318 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
322 static void r700SetAlphaState(GLcontext
* ctx
)
324 context_t
*context
= R700_CONTEXT(ctx
);
325 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
326 uint32_t alpha_func
= REF_ALWAYS
;
327 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
329 switch (ctx
->Color
.AlphaFunc
) {
331 alpha_func
= REF_NEVER
;
334 alpha_func
= REF_LESS
;
337 alpha_func
= REF_EQUAL
;
340 alpha_func
= REF_LEQUAL
;
343 alpha_func
= REF_GREATER
;
346 alpha_func
= REF_NOTEQUAL
;
349 alpha_func
= REF_GEQUAL
;
352 /*alpha_func = REF_ALWAYS; */
353 really_enabled
= GL_FALSE
;
357 if (really_enabled
) {
358 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
359 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
360 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
361 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
363 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
368 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
372 r700SetAlphaState(ctx
);
376 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
378 context_t
*context
= R700_CONTEXT(ctx
);
379 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
381 r700
->CB_BLEND_RED
.f32All
= cf
[0];
382 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
383 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
384 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
387 static int blend_factor(GLenum factor
, GLboolean is_src
)
397 return BLEND_DST_COLOR
;
399 case GL_ONE_MINUS_DST_COLOR
:
400 return BLEND_ONE_MINUS_DST_COLOR
;
403 return BLEND_SRC_COLOR
;
405 case GL_ONE_MINUS_SRC_COLOR
:
406 return BLEND_ONE_MINUS_SRC_COLOR
;
409 return BLEND_SRC_ALPHA
;
411 case GL_ONE_MINUS_SRC_ALPHA
:
412 return BLEND_ONE_MINUS_SRC_ALPHA
;
415 return BLEND_DST_ALPHA
;
417 case GL_ONE_MINUS_DST_ALPHA
:
418 return BLEND_ONE_MINUS_DST_ALPHA
;
420 case GL_SRC_ALPHA_SATURATE
:
421 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
423 case GL_CONSTANT_COLOR
:
424 return BLEND_CONSTANT_COLOR
;
426 case GL_ONE_MINUS_CONSTANT_COLOR
:
427 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
429 case GL_CONSTANT_ALPHA
:
430 return BLEND_CONSTANT_ALPHA
;
432 case GL_ONE_MINUS_CONSTANT_ALPHA
:
433 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
436 fprintf(stderr
, "unknown blend factor %x\n", factor
);
437 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
442 static void r700SetBlendState(GLcontext
* ctx
)
444 context_t
*context
= R700_CONTEXT(ctx
);
445 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
447 uint32_t blend_reg
= 0, eqn
, eqnA
;
449 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
451 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
453 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
455 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
457 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
459 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
461 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
462 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
463 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
465 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
470 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
471 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
473 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
474 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
476 switch (ctx
->Color
.BlendEquationRGB
) {
478 eqn
= COMB_DST_PLUS_SRC
;
480 case GL_FUNC_SUBTRACT
:
481 eqn
= COMB_SRC_MINUS_DST
;
483 case GL_FUNC_REVERSE_SUBTRACT
:
484 eqn
= COMB_DST_MINUS_SRC
;
487 eqn
= COMB_MIN_DST_SRC
;
490 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
493 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
496 eqn
= COMB_MAX_DST_SRC
;
499 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
502 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
507 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
508 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
512 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
515 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
516 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
518 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
519 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
521 switch (ctx
->Color
.BlendEquationA
) {
523 eqnA
= COMB_DST_PLUS_SRC
;
525 case GL_FUNC_SUBTRACT
:
526 eqnA
= COMB_SRC_MINUS_DST
;
528 case GL_FUNC_REVERSE_SUBTRACT
:
529 eqnA
= COMB_DST_MINUS_SRC
;
532 eqnA
= COMB_MIN_DST_SRC
;
535 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
538 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
541 eqnA
= COMB_MAX_DST_SRC
;
544 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
547 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
551 "[%s:%u] Invalid A blend equation (0x%04x).\n",
552 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
557 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
559 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
561 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
562 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
564 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
565 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
567 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
568 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
572 static void r700BlendEquationSeparate(GLcontext
* ctx
,
573 GLenum modeRGB
, GLenum modeA
) //-----------------
575 r700SetBlendState(ctx
);
578 static void r700BlendFuncSeparate(GLcontext
* ctx
,
579 GLenum sfactorRGB
, GLenum dfactorRGB
,
580 GLenum sfactorA
, GLenum dfactorA
) //------------------------
582 r700SetBlendState(ctx
);
586 * Translate LogicOp enums into hardware representation.
587 * Both use a very logical bit-wise layout, but unfortunately the order
588 * of bits is reversed.
590 static GLuint
translate_logicop(GLenum logicop
)
592 GLuint bits
= logicop
- GL_CLEAR
;
593 bits
= ((bits
& 1) << 3) | ((bits
& 2) << 1) | ((bits
& 4) >> 1) | ((bits
& 8) >> 3);
598 * Used internally to update the r300->hw hardware state to match the
599 * current OpenGL state.
601 static void r700SetLogicOpState(GLcontext
*ctx
)
603 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
605 if (RGBA_LOGICOP_ENABLED(ctx
))
606 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
607 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
609 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
613 * Called by Mesa when an application program changes the LogicOp state
616 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
618 if (RGBA_LOGICOP_ENABLED(ctx
))
619 r700SetLogicOpState(ctx
);
622 static void r700UpdateCulling(GLcontext
* ctx
)
624 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
626 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
627 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
628 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
630 if (ctx
->Polygon
.CullFlag
)
632 switch (ctx
->Polygon
.CullFaceMode
)
635 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
636 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
639 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
640 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
642 case GL_FRONT_AND_BACK
:
643 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
644 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
647 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
648 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
653 switch (ctx
->Polygon
.FrontFace
)
656 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
659 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
662 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
667 static void r700UpdateLineStipple(GLcontext
* ctx
)
669 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
670 if (ctx
->Line
.StippleFlag
)
672 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
676 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
680 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
682 context_t
*context
= R700_CONTEXT(ctx
);
694 r700SetAlphaState(ctx
);
696 case GL_COLOR_LOGIC_OP
:
697 r700SetLogicOpState(ctx
);
698 /* fall-through, because logic op overrides blending */
700 r700SetBlendState(ctx
);
708 r700SetClipPlaneState(ctx
, cap
, state
);
711 r700SetDepthState(ctx
);
713 case GL_STENCIL_TEST
:
714 r700SetStencilState(ctx
, state
);
717 r700UpdateCulling(ctx
);
719 case GL_POLYGON_OFFSET_POINT
:
720 case GL_POLYGON_OFFSET_LINE
:
721 case GL_POLYGON_OFFSET_FILL
:
722 r700SetPolygonOffsetState(ctx
, state
);
724 case GL_SCISSOR_TEST
:
725 radeon_firevertices(&context
->radeon
);
726 context
->radeon
.state
.scissor
.enabled
= state
;
727 radeonUpdateScissor(ctx
);
729 case GL_LINE_STIPPLE
:
730 r700UpdateLineStipple(ctx
);
739 * Handle glColorMask()
741 static void r700ColorMask(GLcontext
* ctx
,
742 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
744 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
745 unsigned int mask
= ((r
? 1 : 0) |
750 if (mask
!= r700
->CB_SHADER_MASK
.u32All
)
751 SETfield(r700
->CB_SHADER_MASK
.u32All
, mask
, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
755 * Change the depth testing function.
757 * \note Mesa already filters redundant calls to this function.
759 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
761 r700SetDepthState(ctx
);
765 * Enable/Disable depth writing.
767 * \note Mesa already filters redundant calls to this function.
769 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
771 r700SetDepthState(ctx
);
775 * Change the culling mode.
777 * \note Mesa already filters redundant calls to this function.
779 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
781 r700UpdateCulling(ctx
);
784 /* =============================================================
787 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
792 * Change the polygon orientation.
794 * \note Mesa already filters redundant calls to this function.
796 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
798 r700UpdateCulling(ctx
);
799 r700UpdatePolygonMode(ctx
);
802 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
804 context_t
*context
= R700_CONTEXT(ctx
);
805 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
807 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
810 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
813 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
820 /* =============================================================
823 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
825 context_t
*context
= R700_CONTEXT(ctx
);
826 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
828 /* We need to clamp to user defined range here, because
829 * the HW clamping happens only for per vertex point size. */
830 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
832 /* same size limits for AA, non-AA points */
833 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
835 /* format is 12.4 fixed point */
836 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
837 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
838 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
839 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
843 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
845 context_t
*context
= R700_CONTEXT(ctx
);
846 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
848 /* format is 12.4 fixed point */
850 case GL_POINT_SIZE_MIN
:
851 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 16.0),
852 MIN_SIZE_shift
, MIN_SIZE_mask
);
854 case GL_POINT_SIZE_MAX
:
855 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 16.0),
856 MAX_SIZE_shift
, MAX_SIZE_mask
);
858 case GL_POINT_DISTANCE_ATTENUATION
:
860 case GL_POINT_FADE_THRESHOLD_SIZE
:
867 static int translate_stencil_func(int func
)
890 static int translate_stencil_op(int op
)
898 return STENCIL_REPLACE
;
900 return STENCIL_INCR_CLAMP
;
902 return STENCIL_DECR_CLAMP
;
903 case GL_INCR_WRAP_EXT
:
904 return STENCIL_INCR_WRAP
;
905 case GL_DECR_WRAP_EXT
:
906 return STENCIL_DECR_WRAP
;
908 return STENCIL_INVERT
;
910 WARN_ONCE("Do not know how to translate stencil op");
916 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
918 context_t
*context
= R700_CONTEXT(ctx
);
919 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
920 GLboolean hw_stencil
= GL_FALSE
;
923 //r300CatchStencilFallback(ctx);
925 if (ctx
->DrawBuffer
) {
926 struct radeon_renderbuffer
*rrbStencil
927 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
928 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
933 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
935 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
939 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
940 GLenum func
, GLint ref
, GLuint mask
) //---------------------
942 context_t
*context
= R700_CONTEXT(ctx
);
943 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
944 const unsigned back
= ctx
->Stencil
._BackFace
;
947 //r300CatchStencilFallback(ctx);
950 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
951 STENCILREF_shift
, STENCILREF_mask
);
952 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
953 STENCILMASK_shift
, STENCILMASK_mask
);
955 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
956 STENCILFUNC_shift
, STENCILFUNC_mask
);
959 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
960 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
961 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
962 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
964 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
965 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
969 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
971 context_t
*context
= R700_CONTEXT(ctx
);
972 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
973 const unsigned back
= ctx
->Stencil
._BackFace
;
976 //r300CatchStencilFallback(ctx);
979 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
980 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
983 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
984 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
988 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
989 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
991 context_t
*context
= R700_CONTEXT(ctx
);
992 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
993 const unsigned back
= ctx
->Stencil
._BackFace
;
996 //r300CatchStencilFallback(ctx);
998 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
999 STENCILFAIL_shift
, STENCILFAIL_mask
);
1000 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1001 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1002 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1003 STENCILZPASS_shift
, STENCILZPASS_mask
);
1005 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1006 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1007 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1008 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1009 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1010 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1013 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1015 context_t
*context
= R700_CONTEXT(ctx
);
1016 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1017 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
1018 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1019 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1020 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1021 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1022 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1023 GLfloat y_scale
, y_bias
;
1025 if (render_to_fbo
) {
1033 GLfloat sx
= v
[MAT_SX
];
1034 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1035 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1036 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1037 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1038 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1040 /* TODO : Need DMA flush as well. */
1042 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1043 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1045 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1046 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1048 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1049 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1051 r700
->viewport
[id
].enabled
= GL_TRUE
;
1053 r700SetScissor(context
);
1057 static void r700Viewport(GLcontext
* ctx
,
1061 GLsizei height
) //--------------------
1063 r700UpdateWindow(ctx
, 0);
1065 radeon_viewport(ctx
, x
, y
, width
, height
);
1068 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1070 r700UpdateWindow(ctx
, 0);
1073 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1075 context_t
*context
= R700_CONTEXT(ctx
);
1076 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1077 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1078 if (lineWidth
> 0xFFFF)
1080 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1081 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1084 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1086 context_t
*context
= R700_CONTEXT(ctx
);
1087 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1089 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1090 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1091 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1094 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1096 context_t
*context
= R700_CONTEXT(ctx
);
1097 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1100 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1101 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1102 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1104 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1105 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1106 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1110 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1112 context_t
*context
= R700_CONTEXT(ctx
);
1113 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1114 GLfloat constant
= units
;
1116 switch (ctx
->Visual
.depthBits
) {
1127 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1128 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1129 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1130 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1133 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1135 context_t
*context
= R700_CONTEXT(ctx
);
1136 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1138 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1140 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1141 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1142 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1145 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1146 * correctly by selecting the correct front and back face
1148 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
1149 f
= ctx
->Polygon
.FrontMode
;
1150 b
= ctx
->Polygon
.BackMode
;
1152 f
= ctx
->Polygon
.BackMode
;
1153 b
= ctx
->Polygon
.FrontMode
;
1156 /* Enable polygon mode */
1157 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1161 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1162 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1165 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1166 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1169 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1170 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1176 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1177 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1180 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1181 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1184 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1185 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1191 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1196 r700UpdatePolygonMode(ctx
);
1199 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1203 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1205 context_t
*context
= R700_CONTEXT(ctx
);
1206 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1210 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1211 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1213 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1214 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1215 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1216 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1219 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1221 context_t
*context
= R700_CONTEXT(ctx
);
1222 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1225 p
= cap
- GL_CLIP_PLANE0
;
1227 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1228 r700
->ucp
[p
].enabled
= GL_TRUE
;
1229 r700ClipPlane(ctx
, cap
, NULL
);
1231 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1232 r700
->ucp
[p
].enabled
= GL_FALSE
;
1236 void r700SetScissor(context_t
*context
) //---------------
1238 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1239 unsigned x1
, y1
, x2
, y2
;
1241 struct radeon_renderbuffer
*rrb
;
1243 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1244 if (!rrb
|| !rrb
->bo
) {
1247 if (context
->radeon
.state
.scissor
.enabled
) {
1248 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1249 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1250 x2
= context
->radeon
.state
.scissor
.rect
.x2
- 1;
1251 y2
= context
->radeon
.state
.scissor
.rect
.y2
- 1;
1255 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1256 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1260 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1261 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1262 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1263 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1264 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1266 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1267 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1268 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1269 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1272 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1273 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1274 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1275 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1276 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1277 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1278 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1279 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1281 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1282 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1283 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1284 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1285 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1286 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1288 /* more....2d clip */
1289 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1290 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1291 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1292 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1293 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1294 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1295 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1296 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1297 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1299 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1300 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1301 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1302 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1303 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1304 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1305 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1306 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1307 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1309 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1310 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1311 r700
->viewport
[id
].enabled
= GL_TRUE
;
1314 void r700SetRenderTarget(context_t
*context
, int id
)
1316 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1318 struct radeon_renderbuffer
*rrb
;
1319 unsigned int nPitchInPixel
;
1321 /* screen/window/view */
1322 SETfield(r700
->CB_TARGET_MASK
.u32All
, 0xF, (4 * id
), TARGET0_ENABLE_mask
);
1324 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1325 if (!rrb
|| !rrb
->bo
) {
1326 fprintf(stderr
, "no rrb\n");
1331 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= context
->radeon
.state
.color
.draw_offset
;
1333 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1334 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1335 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1336 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1337 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
1338 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= 0;
1339 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
1340 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ARRAY_LINEAR_GENERAL
,
1341 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
1344 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_8_8_8_8
,
1345 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1346 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT
, COMP_SWAP_shift
, COMP_SWAP_mask
);
1350 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_5_6_5
,
1351 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1352 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT_REV
,
1353 COMP_SWAP_shift
, COMP_SWAP_mask
);
1355 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SOURCE_FORMAT_bit
);
1356 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, BLEND_CLAMP_bit
);
1357 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
1359 r700
->render_target
[id
].enabled
= GL_TRUE
;
1362 void r700SetDepthTarget(context_t
*context
)
1364 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1366 struct radeon_renderbuffer
*rrb
;
1367 unsigned int nPitchInPixel
;
1370 r700
->DB_DEPTH_SIZE
.u32All
= 0;
1371 r700
->DB_DEPTH_BASE
.u32All
= 0;
1372 r700
->DB_DEPTH_INFO
.u32All
= 0;
1374 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1375 r700
->DB_DEPTH_VIEW
.u32All
= 0;
1376 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1377 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1378 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1379 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1380 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1381 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1382 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1383 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1384 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1386 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1387 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1388 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1389 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1390 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1392 rrb
= radeon_get_depthbuffer(&context
->radeon
);
1396 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1398 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1399 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1400 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1401 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
); /* size in pixel / 64 - 1 */
1405 switch (GL_CONTEXT(context
)->Visual
.depthBits
)
1409 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_8_24
,
1410 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1413 fprintf(stderr
, "Error: Unsupported depth %d... exiting\n",
1414 GL_CONTEXT(context
)->Visual
.depthBits
);
1420 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_16
,
1421 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1423 SETfield(r700
->DB_DEPTH_INFO
.u32All
, ARRAY_2D_TILED_THIN1
,
1424 DB_DEPTH_INFO__ARRAY_MODE_shift
, DB_DEPTH_INFO__ARRAY_MODE_mask
);
1425 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1428 static void r700InitSQConfig(GLcontext
* ctx
)
1430 context_t
*context
= R700_CONTEXT(ctx
);
1431 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1445 int num_ps_stack_entries
;
1446 int num_vs_stack_entries
;
1447 int num_gs_stack_entries
;
1448 int num_es_stack_entries
;
1455 switch (context
->radeon
.radeonScreen
->chip_family
) {
1456 case CHIP_FAMILY_R600
:
1462 num_ps_threads
= 136;
1463 num_vs_threads
= 48;
1466 num_ps_stack_entries
= 128;
1467 num_vs_stack_entries
= 128;
1468 num_gs_stack_entries
= 0;
1469 num_es_stack_entries
= 0;
1471 case CHIP_FAMILY_RV630
:
1472 case CHIP_FAMILY_RV635
:
1478 num_ps_threads
= 144;
1479 num_vs_threads
= 40;
1482 num_ps_stack_entries
= 40;
1483 num_vs_stack_entries
= 40;
1484 num_gs_stack_entries
= 32;
1485 num_es_stack_entries
= 16;
1487 case CHIP_FAMILY_RV610
:
1488 case CHIP_FAMILY_RV620
:
1489 case CHIP_FAMILY_RS780
:
1496 num_ps_threads
= 136;
1497 num_vs_threads
= 48;
1500 num_ps_stack_entries
= 40;
1501 num_vs_stack_entries
= 40;
1502 num_gs_stack_entries
= 32;
1503 num_es_stack_entries
= 16;
1505 case CHIP_FAMILY_RV670
:
1511 num_ps_threads
= 136;
1512 num_vs_threads
= 48;
1515 num_ps_stack_entries
= 40;
1516 num_vs_stack_entries
= 40;
1517 num_gs_stack_entries
= 32;
1518 num_es_stack_entries
= 16;
1520 case CHIP_FAMILY_RV770
:
1526 num_ps_threads
= 188;
1527 num_vs_threads
= 60;
1530 num_ps_stack_entries
= 256;
1531 num_vs_stack_entries
= 256;
1532 num_gs_stack_entries
= 0;
1533 num_es_stack_entries
= 0;
1535 case CHIP_FAMILY_RV730
:
1536 case CHIP_FAMILY_RV740
:
1542 num_ps_threads
= 188;
1543 num_vs_threads
= 60;
1546 num_ps_stack_entries
= 128;
1547 num_vs_stack_entries
= 128;
1548 num_gs_stack_entries
= 0;
1549 num_es_stack_entries
= 0;
1551 case CHIP_FAMILY_RV710
:
1557 num_ps_threads
= 144;
1558 num_vs_threads
= 48;
1561 num_ps_stack_entries
= 128;
1562 num_vs_stack_entries
= 128;
1563 num_gs_stack_entries
= 0;
1564 num_es_stack_entries
= 0;
1568 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1569 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1570 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1571 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1572 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1573 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1575 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1576 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1577 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1578 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1579 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1580 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1581 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1583 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1584 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1585 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1586 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1587 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1589 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1590 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1591 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1593 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1594 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1595 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1596 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1597 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1598 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1599 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1600 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1601 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1603 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1604 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1605 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1606 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1607 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1609 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1610 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1611 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1612 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1613 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1618 * Calculate initial hardware state and register state functions.
1619 * Assumes that the command buffer and state atoms have been
1620 * initialized already.
1622 void r700InitState(GLcontext
* ctx
) //-------------------
1624 context_t
*context
= R700_CONTEXT(ctx
);
1626 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1628 r700
->TA_CNTL_AUX
.u32All
= 0;
1629 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1630 r700
->VC_ENHANCE
.u32All
= 0;
1631 r700
->DB_WATERMARKS
.u32All
= 0;
1632 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1633 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1634 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1635 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1636 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1637 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1638 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1639 r700
->DB_DEBUG
.u32All
= 0x82000000;
1640 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1642 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1643 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1644 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1647 /* Turn off vgt reuse */
1648 r700
->VGT_REUSE_OFF
.u32All
= 0;
1649 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1651 /* Specify offsetting and clamp values for vertices */
1652 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1653 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1654 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1656 /* Specify the number of instances */
1657 r700
->VGT_DMA_NUM_INSTANCES
.u32All
= 1;
1659 /* default shader connections. */
1660 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1661 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1663 r700
->SPI_PS_INPUT_CNTL_0
.u32All
= 0x00000800;
1664 r700
->SPI_PS_INPUT_CNTL_1
.u32All
= 0x00000801;
1665 r700
->SPI_PS_INPUT_CNTL_2
.u32All
= 0x00000802;
1667 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1668 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1669 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1672 r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
= 0x0;
1674 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
,
1675 ((RADEONDRIPtr
)(context
->radeon
.radeonScreen
->driScreen
->pDevPriv
))->width
,
1676 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1677 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
,
1678 ((RADEONDRIPtr
)(context
->radeon
.radeonScreen
->driScreen
->pDevPriv
))->height
,
1679 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1681 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1682 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1683 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1685 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1686 r700
->PA_SC_EDGERULE
.u32All
= 0;
1688 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1690 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1691 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1692 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1693 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1695 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1696 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1697 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1700 /* Do scale XY and Z by 1/W0. */
1701 r700
->bEnablePerspective
= GL_TRUE
;
1702 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1703 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1704 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1706 /* Enable viewport scaling for all three axis */
1707 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1708 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1709 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1710 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1711 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1712 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1714 /* GL uses last vtx for flat shading components */
1715 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1717 /* Set up vertex control */
1718 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1719 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1720 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1721 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1722 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1724 /* to 1.0 = no guard band */
1725 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1726 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1727 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1728 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1730 /* Enable all samples for multi-sample anti-aliasing */
1731 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1733 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1735 r700
->SX_MISC
.u32All
= 0;
1737 r700InitSQConfig(ctx
);
1740 ctx
->Color
.ColorMask
[RCOMP
],
1741 ctx
->Color
.ColorMask
[GCOMP
],
1742 ctx
->Color
.ColorMask
[BCOMP
],
1743 ctx
->Color
.ColorMask
[ACOMP
]);
1745 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1746 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1747 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1748 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1751 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1752 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1753 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1754 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1755 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1756 ctx
->Stencil
.ZFailFunc
[0],
1757 ctx
->Stencil
.ZPassFunc
[0]);
1759 r700UpdateCulling(ctx
);
1761 r700SetBlendState(ctx
);
1762 r700SetLogicOpState(ctx
);
1764 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1765 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1767 r700PointSize(ctx
, 1.0);
1769 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1770 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1772 r700LineWidth(ctx
, 1.0);
1774 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1775 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1776 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1778 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1779 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1780 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1781 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1782 ctx
->Polygon
.OffsetUnits
);
1783 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1784 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1785 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1788 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1790 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1791 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1792 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1793 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1794 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1795 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1796 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1798 /* Disable color compares */
1799 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1800 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1801 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1802 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1803 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1804 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1806 /* Zero out source */
1807 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1809 /* Put a compare color in for error checking */
1810 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1812 /* Set up color compare mask */
1813 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1817 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1819 functions
->UpdateState
= r700InvalidateState
;
1820 functions
->AlphaFunc
= r700AlphaFunc
;
1821 functions
->BlendColor
= r700BlendColor
;
1822 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1823 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1824 functions
->Enable
= r700Enable
;
1825 functions
->ColorMask
= r700ColorMask
;
1826 functions
->DepthFunc
= r700DepthFunc
;
1827 functions
->DepthMask
= r700DepthMask
;
1828 functions
->CullFace
= r700CullFace
;
1829 functions
->Fogfv
= r700Fogfv
;
1830 functions
->FrontFace
= r700FrontFace
;
1831 functions
->ShadeModel
= r700ShadeModel
;
1832 functions
->LogicOpcode
= r700LogicOpcode
;
1834 /* ARB_point_parameters */
1835 functions
->PointParameterfv
= r700PointParameter
;
1837 /* Stencil related */
1838 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1839 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1840 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1842 /* Viewport related */
1843 functions
->Viewport
= r700Viewport
;
1844 functions
->DepthRange
= r700DepthRange
;
1845 functions
->PointSize
= r700PointSize
;
1846 functions
->LineWidth
= r700LineWidth
;
1847 functions
->LineStipple
= r700LineStipple
;
1849 functions
->PolygonOffset
= r700PolygonOffset
;
1850 functions
->PolygonMode
= r700PolygonMode
;
1852 functions
->RenderMode
= r700RenderMode
;
1854 functions
->ClipPlane
= r700ClipPlane
;
1856 functions
->Scissor
= radeonScissor
;
1858 functions
->DrawBuffer
= radeonDrawBuffer
;
1859 functions
->ReadBuffer
= radeonReadBuffer
;