2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
62 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
64 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
66 context_t
*context
= R700_CONTEXT(ctx
);
67 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
68 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
71 /* should only happenen once, just after context is created */
72 /* TODO: shouldn't we fallback to sw here? */
73 if (!ctx
->FragmentProgram
._Current
) {
74 _mesa_fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
78 r700SelectFragmentShader(ctx
);
80 if (context
->radeon
.NewGLState
) {
81 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++) {
82 /* mat states from state var not array for sw */
83 dummy_attrib
[i
].stride
= 0;
84 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
85 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
88 _tnl_UpdateFixedFunctionProgram(ctx
);
90 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++) {
91 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
95 r700SelectVertexShader(ctx
);
96 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
97 context
->radeon
.NewGLState
= 0;
101 * To correctly position primitives:
103 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
105 context_t
*context
= R700_CONTEXT(ctx
);
106 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
107 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
108 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
109 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
110 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
113 GLfloat tx
= v
[MAT_TX
] + xoffset
;
114 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
116 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
117 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
118 /* Note: this should also modify whatever data the context reset
121 R600_STATECHANGE(context
, vpt
);
122 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
123 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
126 radeonUpdateScissor(ctx
);
129 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
131 struct r700_fragment_program
*fp
=
132 (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
133 struct gl_program_parameter_list
*paramList
;
135 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
138 if (!ctx
->FragmentProgram
._Current
|| !fp
)
141 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
146 _mesa_load_state_parameters(ctx
, paramList
);
151 * Called by Mesa after an internal state update.
153 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
155 context_t
*context
= R700_CONTEXT(ctx
);
157 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
159 _swrast_InvalidateState(ctx
, new_state
);
160 _swsetup_InvalidateState(ctx
, new_state
);
161 _vbo_InvalidateState(ctx
, new_state
);
162 _tnl_InvalidateState(ctx
, new_state
);
163 _ae_invalidate_state(ctx
, new_state
);
165 if (new_state
& _NEW_BUFFERS
) {
166 _mesa_update_framebuffer(ctx
);
167 /* this updates the DrawBuffer's Width/Height if it's a FBO */
168 _mesa_update_draw_buffer_bounds(ctx
);
170 R600_STATECHANGE(context
, cb_target
);
171 R600_STATECHANGE(context
, db_target
);
174 if (new_state
& (_NEW_LIGHT
)) {
175 R600_STATECHANGE(context
, su
);
176 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
)
177 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
179 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
182 r700UpdateStateParameters(ctx
, new_state
);
184 R600_STATECHANGE(context
, cl
);
185 R600_STATECHANGE(context
, spi
);
187 if(GL_TRUE
== r700
->bEnablePerspective
)
189 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
190 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
191 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
193 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
195 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
196 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
200 /* For orthogonal case. */
201 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
202 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
204 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
206 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
207 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
210 context
->radeon
.NewGLState
|= new_state
;
213 static void r700SetDepthState(GLcontext
* ctx
)
215 context_t
*context
= R700_CONTEXT(ctx
);
216 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
218 R600_STATECHANGE(context
, db
);
222 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
225 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
229 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
232 switch (ctx
->Depth
.Func
)
235 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
236 ZFUNC_shift
, ZFUNC_mask
);
239 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
240 ZFUNC_shift
, ZFUNC_mask
);
243 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
244 ZFUNC_shift
, ZFUNC_mask
);
247 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
248 ZFUNC_shift
, ZFUNC_mask
);
251 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
252 ZFUNC_shift
, ZFUNC_mask
);
255 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
256 ZFUNC_shift
, ZFUNC_mask
);
259 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
260 ZFUNC_shift
, ZFUNC_mask
);
263 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
264 ZFUNC_shift
, ZFUNC_mask
);
267 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
268 ZFUNC_shift
, ZFUNC_mask
);
274 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
275 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
279 static void r700SetAlphaState(GLcontext
* ctx
)
281 context_t
*context
= R700_CONTEXT(ctx
);
282 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
283 uint32_t alpha_func
= REF_ALWAYS
;
284 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
286 R600_STATECHANGE(context
, sx
);
288 switch (ctx
->Color
.AlphaFunc
) {
290 alpha_func
= REF_NEVER
;
293 alpha_func
= REF_LESS
;
296 alpha_func
= REF_EQUAL
;
299 alpha_func
= REF_LEQUAL
;
302 alpha_func
= REF_GREATER
;
305 alpha_func
= REF_NOTEQUAL
;
308 alpha_func
= REF_GEQUAL
;
311 /*alpha_func = REF_ALWAYS; */
312 really_enabled
= GL_FALSE
;
316 if (really_enabled
) {
317 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
318 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
319 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
320 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
322 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
327 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
331 r700SetAlphaState(ctx
);
335 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
337 context_t
*context
= R700_CONTEXT(ctx
);
338 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
340 R600_STATECHANGE(context
, blnd_clr
);
342 r700
->CB_BLEND_RED
.f32All
= cf
[0];
343 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
344 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
345 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
348 static int blend_factor(GLenum factor
, GLboolean is_src
)
358 return BLEND_DST_COLOR
;
360 case GL_ONE_MINUS_DST_COLOR
:
361 return BLEND_ONE_MINUS_DST_COLOR
;
364 return BLEND_SRC_COLOR
;
366 case GL_ONE_MINUS_SRC_COLOR
:
367 return BLEND_ONE_MINUS_SRC_COLOR
;
370 return BLEND_SRC_ALPHA
;
372 case GL_ONE_MINUS_SRC_ALPHA
:
373 return BLEND_ONE_MINUS_SRC_ALPHA
;
376 return BLEND_DST_ALPHA
;
378 case GL_ONE_MINUS_DST_ALPHA
:
379 return BLEND_ONE_MINUS_DST_ALPHA
;
381 case GL_SRC_ALPHA_SATURATE
:
382 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
384 case GL_CONSTANT_COLOR
:
385 return BLEND_CONSTANT_COLOR
;
387 case GL_ONE_MINUS_CONSTANT_COLOR
:
388 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
390 case GL_CONSTANT_ALPHA
:
391 return BLEND_CONSTANT_ALPHA
;
393 case GL_ONE_MINUS_CONSTANT_ALPHA
:
394 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
397 fprintf(stderr
, "unknown blend factor %x\n", factor
);
398 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
403 static void r700SetBlendState(GLcontext
* ctx
)
405 context_t
*context
= R700_CONTEXT(ctx
);
406 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
408 uint32_t blend_reg
= 0, eqn
, eqnA
;
410 R600_STATECHANGE(context
, blnd
);
412 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
414 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
416 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
418 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
420 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
422 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
424 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
425 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
426 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
428 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
433 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
434 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
436 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
437 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
439 switch (ctx
->Color
.BlendEquationRGB
) {
441 eqn
= COMB_DST_PLUS_SRC
;
443 case GL_FUNC_SUBTRACT
:
444 eqn
= COMB_SRC_MINUS_DST
;
446 case GL_FUNC_REVERSE_SUBTRACT
:
447 eqn
= COMB_DST_MINUS_SRC
;
450 eqn
= COMB_MIN_DST_SRC
;
453 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
456 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
459 eqn
= COMB_MAX_DST_SRC
;
462 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
465 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
470 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
471 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
475 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
478 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
479 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
481 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
482 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
484 switch (ctx
->Color
.BlendEquationA
) {
486 eqnA
= COMB_DST_PLUS_SRC
;
488 case GL_FUNC_SUBTRACT
:
489 eqnA
= COMB_SRC_MINUS_DST
;
491 case GL_FUNC_REVERSE_SUBTRACT
:
492 eqnA
= COMB_DST_MINUS_SRC
;
495 eqnA
= COMB_MIN_DST_SRC
;
498 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
501 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
504 eqnA
= COMB_MAX_DST_SRC
;
507 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
510 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
514 "[%s:%u] Invalid A blend equation (0x%04x).\n",
515 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
520 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
522 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
524 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
525 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
527 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
528 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
530 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
531 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
535 static void r700BlendEquationSeparate(GLcontext
* ctx
,
536 GLenum modeRGB
, GLenum modeA
) //-----------------
538 r700SetBlendState(ctx
);
541 static void r700BlendFuncSeparate(GLcontext
* ctx
,
542 GLenum sfactorRGB
, GLenum dfactorRGB
,
543 GLenum sfactorA
, GLenum dfactorA
) //------------------------
545 r700SetBlendState(ctx
);
549 * Translate LogicOp enums into hardware representation.
551 static GLuint
translate_logicop(GLenum logicop
)
560 case GL_COPY_INVERTED
:
580 case GL_AND_INVERTED
:
587 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
593 * Used internally to update the r300->hw hardware state to match the
594 * current OpenGL state.
596 static void r700SetLogicOpState(GLcontext
*ctx
)
598 context_t
*context
= R700_CONTEXT(ctx
);
599 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
601 R600_STATECHANGE(context
, blnd
);
603 if (RGBA_LOGICOP_ENABLED(ctx
))
604 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
605 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
607 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
611 * Called by Mesa when an application program changes the LogicOp state
614 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
616 if (RGBA_LOGICOP_ENABLED(ctx
))
617 r700SetLogicOpState(ctx
);
620 static void r700UpdateCulling(GLcontext
* ctx
)
622 context_t
*context
= R700_CONTEXT(ctx
);
623 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
625 R600_STATECHANGE(context
, su
);
627 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
628 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
629 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
631 if (ctx
->Polygon
.CullFlag
)
633 switch (ctx
->Polygon
.CullFaceMode
)
636 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
637 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
640 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
641 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
643 case GL_FRONT_AND_BACK
:
644 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
645 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
648 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
649 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
654 switch (ctx
->Polygon
.FrontFace
)
657 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
660 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
663 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
668 static void r700UpdateLineStipple(GLcontext
* ctx
)
670 context_t
*context
= R700_CONTEXT(ctx
);
671 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
673 R600_STATECHANGE(context
, sc
);
675 if (ctx
->Line
.StippleFlag
)
677 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
681 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
685 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
687 context_t
*context
= R700_CONTEXT(ctx
);
699 r700SetAlphaState(ctx
);
701 case GL_COLOR_LOGIC_OP
:
702 r700SetLogicOpState(ctx
);
703 /* fall-through, because logic op overrides blending */
705 r700SetBlendState(ctx
);
713 r700SetClipPlaneState(ctx
, cap
, state
);
716 r700SetDepthState(ctx
);
718 case GL_STENCIL_TEST
:
719 r700SetStencilState(ctx
, state
);
722 r700UpdateCulling(ctx
);
724 case GL_POLYGON_OFFSET_POINT
:
725 case GL_POLYGON_OFFSET_LINE
:
726 case GL_POLYGON_OFFSET_FILL
:
727 r700SetPolygonOffsetState(ctx
, state
);
729 case GL_SCISSOR_TEST
:
730 radeon_firevertices(&context
->radeon
);
731 context
->radeon
.state
.scissor
.enabled
= state
;
732 radeonUpdateScissor(ctx
);
734 case GL_LINE_STIPPLE
:
735 r700UpdateLineStipple(ctx
);
744 * Handle glColorMask()
746 static void r700ColorMask(GLcontext
* ctx
,
747 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
749 context_t
*context
= R700_CONTEXT(ctx
);
750 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
751 unsigned int mask
= ((r
? 1 : 0) |
756 if (mask
!= r700
->CB_SHADER_MASK
.u32All
) {
757 R600_STATECHANGE(context
, cb
);
758 SETfield(r700
->CB_SHADER_MASK
.u32All
, mask
, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
763 * Change the depth testing function.
765 * \note Mesa already filters redundant calls to this function.
767 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
769 r700SetDepthState(ctx
);
773 * Enable/Disable depth writing.
775 * \note Mesa already filters redundant calls to this function.
777 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
779 r700SetDepthState(ctx
);
783 * Change the culling mode.
785 * \note Mesa already filters redundant calls to this function.
787 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
789 r700UpdateCulling(ctx
);
792 /* =============================================================
795 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
800 * Change the polygon orientation.
802 * \note Mesa already filters redundant calls to this function.
804 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
806 r700UpdateCulling(ctx
);
807 r700UpdatePolygonMode(ctx
);
810 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
812 context_t
*context
= R700_CONTEXT(ctx
);
813 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
815 R600_STATECHANGE(context
, spi
);
817 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
820 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
823 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
830 /* =============================================================
833 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
835 context_t
*context
= R700_CONTEXT(ctx
);
836 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
838 R600_STATECHANGE(context
, su
);
840 /* We need to clamp to user defined range here, because
841 * the HW clamping happens only for per vertex point size. */
842 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
844 /* same size limits for AA, non-AA points */
845 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
847 /* format is 12.4 fixed point */
848 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
849 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
850 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
851 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
855 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
857 context_t
*context
= R700_CONTEXT(ctx
);
858 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
860 R600_STATECHANGE(context
, su
);
862 /* format is 12.4 fixed point */
864 case GL_POINT_SIZE_MIN
:
865 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 16.0),
866 MIN_SIZE_shift
, MIN_SIZE_mask
);
868 case GL_POINT_SIZE_MAX
:
869 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 16.0),
870 MAX_SIZE_shift
, MAX_SIZE_mask
);
872 case GL_POINT_DISTANCE_ATTENUATION
:
874 case GL_POINT_FADE_THRESHOLD_SIZE
:
881 static int translate_stencil_func(int func
)
904 static int translate_stencil_op(int op
)
912 return STENCIL_REPLACE
;
914 return STENCIL_INCR_CLAMP
;
916 return STENCIL_DECR_CLAMP
;
917 case GL_INCR_WRAP_EXT
:
918 return STENCIL_INCR_WRAP
;
919 case GL_DECR_WRAP_EXT
:
920 return STENCIL_DECR_WRAP
;
922 return STENCIL_INVERT
;
924 WARN_ONCE("Do not know how to translate stencil op");
930 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
932 context_t
*context
= R700_CONTEXT(ctx
);
933 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
934 GLboolean hw_stencil
= GL_FALSE
;
936 if (ctx
->DrawBuffer
) {
937 struct radeon_renderbuffer
*rrbStencil
938 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
939 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
943 R600_STATECHANGE(context
, db
);
945 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
946 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
948 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
952 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
953 GLenum func
, GLint ref
, GLuint mask
) //---------------------
955 context_t
*context
= R700_CONTEXT(ctx
);
956 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
957 const unsigned back
= ctx
->Stencil
._BackFace
;
959 R600_STATECHANGE(context
, stencil
);
960 R600_STATECHANGE(context
, db
);
963 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
964 STENCILREF_shift
, STENCILREF_mask
);
965 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
966 STENCILMASK_shift
, STENCILMASK_mask
);
968 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
969 STENCILFUNC_shift
, STENCILFUNC_mask
);
972 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
973 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
974 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
975 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
977 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
978 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
982 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
984 context_t
*context
= R700_CONTEXT(ctx
);
985 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
986 const unsigned back
= ctx
->Stencil
._BackFace
;
988 R600_STATECHANGE(context
, stencil
);
991 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
992 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
995 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
996 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1000 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
1001 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
1003 context_t
*context
= R700_CONTEXT(ctx
);
1004 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1005 const unsigned back
= ctx
->Stencil
._BackFace
;
1007 R600_STATECHANGE(context
, db
);
1009 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1010 STENCILFAIL_shift
, STENCILFAIL_mask
);
1011 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1012 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1013 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1014 STENCILZPASS_shift
, STENCILZPASS_mask
);
1016 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1017 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1018 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1019 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1020 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1021 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1024 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1026 context_t
*context
= R700_CONTEXT(ctx
);
1027 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1028 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
1029 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1030 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1031 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1032 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1033 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1034 GLfloat y_scale
, y_bias
;
1036 if (render_to_fbo
) {
1044 GLfloat sx
= v
[MAT_SX
];
1045 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1046 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1047 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1048 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1049 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1051 R600_STATECHANGE(context
, vpt
);
1053 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1054 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1056 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1057 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1059 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1060 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1062 r700
->viewport
[id
].enabled
= GL_TRUE
;
1064 r700SetScissor(context
);
1068 static void r700Viewport(GLcontext
* ctx
,
1072 GLsizei height
) //--------------------
1074 r700UpdateWindow(ctx
, 0);
1076 radeon_viewport(ctx
, x
, y
, width
, height
);
1079 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1081 r700UpdateWindow(ctx
, 0);
1084 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1086 context_t
*context
= R700_CONTEXT(ctx
);
1087 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1088 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1090 R600_STATECHANGE(context
, su
);
1092 if (lineWidth
> 0xFFFF)
1094 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1095 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1098 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1100 context_t
*context
= R700_CONTEXT(ctx
);
1101 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1103 R600_STATECHANGE(context
, sc
);
1105 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1106 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1107 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1110 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1112 context_t
*context
= R700_CONTEXT(ctx
);
1113 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1115 R600_STATECHANGE(context
, su
);
1118 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1119 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1120 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1122 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1123 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1124 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1128 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1130 context_t
*context
= R700_CONTEXT(ctx
);
1131 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1132 GLfloat constant
= units
;
1134 switch (ctx
->Visual
.depthBits
) {
1145 R600_STATECHANGE(context
, poly
);
1147 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1148 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1149 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1150 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1153 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1155 context_t
*context
= R700_CONTEXT(ctx
);
1156 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1158 R600_STATECHANGE(context
, su
);
1160 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1162 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1163 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1164 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1167 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1168 * correctly by selecting the correct front and back face
1170 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
1171 f
= ctx
->Polygon
.FrontMode
;
1172 b
= ctx
->Polygon
.BackMode
;
1174 f
= ctx
->Polygon
.BackMode
;
1175 b
= ctx
->Polygon
.FrontMode
;
1178 /* Enable polygon mode */
1179 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1183 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1184 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1187 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1188 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1191 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1192 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1198 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1199 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1202 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1203 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1206 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1207 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1213 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1218 r700UpdatePolygonMode(ctx
);
1221 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1225 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1227 context_t
*context
= R700_CONTEXT(ctx
);
1228 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1232 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1233 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1235 R600_STATECHANGE(context
, ucp
);
1237 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1238 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1239 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1240 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1243 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1245 context_t
*context
= R700_CONTEXT(ctx
);
1246 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1249 p
= cap
- GL_CLIP_PLANE0
;
1251 R600_STATECHANGE(context
, cl
);
1254 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1255 r700
->ucp
[p
].enabled
= GL_TRUE
;
1256 r700ClipPlane(ctx
, cap
, NULL
);
1258 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1259 r700
->ucp
[p
].enabled
= GL_FALSE
;
1263 void r700SetScissor(context_t
*context
) //---------------
1265 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1266 unsigned x1
, y1
, x2
, y2
;
1268 struct radeon_renderbuffer
*rrb
;
1270 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1271 if (!rrb
|| !rrb
->bo
) {
1274 if (context
->radeon
.state
.scissor
.enabled
) {
1275 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1276 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1277 x2
= context
->radeon
.state
.scissor
.rect
.x2
;
1278 y2
= context
->radeon
.state
.scissor
.rect
.y2
;
1280 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1283 x2
= rrb
->base
.Width
;
1284 y2
= rrb
->base
.Height
;
1288 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1289 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1293 R600_STATECHANGE(context
, scissor
);
1296 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1297 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1298 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1299 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1300 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1302 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1303 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1304 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1305 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1308 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1309 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1310 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1311 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1312 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1314 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1315 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1316 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1317 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1320 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1321 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1322 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1323 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1324 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1325 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1326 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1327 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1329 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1330 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1331 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1332 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1333 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1334 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1336 /* more....2d clip */
1337 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1338 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1339 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1340 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1341 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1342 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1343 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1344 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1345 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1347 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1348 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1349 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1350 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1351 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1352 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1353 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1354 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1355 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1357 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1358 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1359 r700
->viewport
[id
].enabled
= GL_TRUE
;
1362 static void r700InitSQConfig(GLcontext
* ctx
)
1364 context_t
*context
= R700_CONTEXT(ctx
);
1365 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1379 int num_ps_stack_entries
;
1380 int num_vs_stack_entries
;
1381 int num_gs_stack_entries
;
1382 int num_es_stack_entries
;
1384 R600_STATECHANGE(context
, sq
);
1391 switch (context
->radeon
.radeonScreen
->chip_family
) {
1392 case CHIP_FAMILY_R600
:
1398 num_ps_threads
= 136;
1399 num_vs_threads
= 48;
1402 num_ps_stack_entries
= 128;
1403 num_vs_stack_entries
= 128;
1404 num_gs_stack_entries
= 0;
1405 num_es_stack_entries
= 0;
1407 case CHIP_FAMILY_RV630
:
1408 case CHIP_FAMILY_RV635
:
1414 num_ps_threads
= 144;
1415 num_vs_threads
= 40;
1418 num_ps_stack_entries
= 40;
1419 num_vs_stack_entries
= 40;
1420 num_gs_stack_entries
= 32;
1421 num_es_stack_entries
= 16;
1423 case CHIP_FAMILY_RV610
:
1424 case CHIP_FAMILY_RV620
:
1425 case CHIP_FAMILY_RS780
:
1426 case CHIP_FAMILY_RS880
:
1433 num_ps_threads
= 136;
1434 num_vs_threads
= 48;
1437 num_ps_stack_entries
= 40;
1438 num_vs_stack_entries
= 40;
1439 num_gs_stack_entries
= 32;
1440 num_es_stack_entries
= 16;
1442 case CHIP_FAMILY_RV670
:
1448 num_ps_threads
= 136;
1449 num_vs_threads
= 48;
1452 num_ps_stack_entries
= 40;
1453 num_vs_stack_entries
= 40;
1454 num_gs_stack_entries
= 32;
1455 num_es_stack_entries
= 16;
1457 case CHIP_FAMILY_RV770
:
1463 num_ps_threads
= 188;
1464 num_vs_threads
= 60;
1467 num_ps_stack_entries
= 256;
1468 num_vs_stack_entries
= 256;
1469 num_gs_stack_entries
= 0;
1470 num_es_stack_entries
= 0;
1472 case CHIP_FAMILY_RV730
:
1473 case CHIP_FAMILY_RV740
:
1479 num_ps_threads
= 188;
1480 num_vs_threads
= 60;
1483 num_ps_stack_entries
= 128;
1484 num_vs_stack_entries
= 128;
1485 num_gs_stack_entries
= 0;
1486 num_es_stack_entries
= 0;
1488 case CHIP_FAMILY_RV710
:
1494 num_ps_threads
= 144;
1495 num_vs_threads
= 48;
1498 num_ps_stack_entries
= 128;
1499 num_vs_stack_entries
= 128;
1500 num_gs_stack_entries
= 0;
1501 num_es_stack_entries
= 0;
1505 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1506 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1507 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1508 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1509 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1510 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1511 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1513 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1514 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1515 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1516 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1517 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1518 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1519 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1521 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1522 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1523 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1524 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1525 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1527 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1528 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1529 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1531 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1532 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1533 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1534 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1535 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1536 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1537 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1538 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1539 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1541 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1542 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1543 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1544 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1545 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1547 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1548 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1549 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1550 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1551 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1556 * Calculate initial hardware state and register state functions.
1557 * Assumes that the command buffer and state atoms have been
1558 * initialized already.
1560 void r700InitState(GLcontext
* ctx
) //-------------------
1562 context_t
*context
= R700_CONTEXT(ctx
);
1563 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1566 radeon_firevertices(&context
->radeon
);
1568 r700
->TA_CNTL_AUX
.u32All
= 0;
1569 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1570 r700
->VC_ENHANCE
.u32All
= 0;
1571 r700
->DB_WATERMARKS
.u32All
= 0;
1572 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1573 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1574 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1575 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1576 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1577 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1578 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1579 r700
->DB_DEBUG
.u32All
= 0x82000000;
1580 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1582 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1583 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1584 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1587 /* Turn off vgt reuse */
1588 r700
->VGT_REUSE_OFF
.u32All
= 0;
1589 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1591 /* Specify offsetting and clamp values for vertices */
1592 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1593 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1594 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1596 /* default shader connections. */
1597 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1598 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1599 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1600 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1602 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1603 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1604 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1606 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1607 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1608 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1610 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1611 r700
->PA_SC_EDGERULE
.u32All
= 0;
1613 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1615 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1616 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1617 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1618 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1620 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1621 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1622 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1625 /* Do scale XY and Z by 1/W0. */
1626 r700
->bEnablePerspective
= GL_TRUE
;
1627 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1628 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1629 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1631 /* Enable viewport scaling for all three axis */
1632 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1633 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1634 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1635 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1636 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1637 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1639 /* GL uses last vtx for flat shading components */
1640 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1642 /* Set up vertex control */
1643 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1644 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1645 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1646 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1647 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1649 /* to 1.0 = no guard band */
1650 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1651 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1652 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1653 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1655 /* Enable all samples for multi-sample anti-aliasing */
1656 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1658 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1660 r700
->SX_MISC
.u32All
= 0;
1662 r700InitSQConfig(ctx
);
1665 ctx
->Color
.ColorMask
[RCOMP
],
1666 ctx
->Color
.ColorMask
[GCOMP
],
1667 ctx
->Color
.ColorMask
[BCOMP
],
1668 ctx
->Color
.ColorMask
[ACOMP
]);
1670 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1671 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1672 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1673 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1675 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1677 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1678 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1679 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1680 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1681 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1682 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1683 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1684 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1685 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1687 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1688 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1689 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1690 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1691 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1694 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1695 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1696 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1697 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1698 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1699 ctx
->Stencil
.ZFailFunc
[0],
1700 ctx
->Stencil
.ZPassFunc
[0]);
1702 r700UpdateCulling(ctx
);
1704 r700SetBlendState(ctx
);
1705 r700SetLogicOpState(ctx
);
1707 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1708 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1710 r700PointSize(ctx
, 1.0);
1712 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1713 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1715 r700LineWidth(ctx
, 1.0);
1717 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1718 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1719 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1721 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1722 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1723 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1724 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1725 ctx
->Polygon
.OffsetUnits
);
1726 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1727 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1728 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1731 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1733 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1734 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1735 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1736 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1737 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1738 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1739 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1741 /* Disable color compares */
1742 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1743 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1744 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1745 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1746 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1747 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1749 /* Zero out source */
1750 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1752 /* Put a compare color in for error checking */
1753 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1755 /* Set up color compare mask */
1756 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1758 /* screen/window/view */
1759 SETfield(r700
->CB_TARGET_MASK
.u32All
, 0xF, (4 * id
), TARGET0_ENABLE_mask
);
1761 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1765 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1767 functions
->UpdateState
= r700InvalidateState
;
1768 functions
->AlphaFunc
= r700AlphaFunc
;
1769 functions
->BlendColor
= r700BlendColor
;
1770 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1771 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1772 functions
->Enable
= r700Enable
;
1773 functions
->ColorMask
= r700ColorMask
;
1774 functions
->DepthFunc
= r700DepthFunc
;
1775 functions
->DepthMask
= r700DepthMask
;
1776 functions
->CullFace
= r700CullFace
;
1777 functions
->Fogfv
= r700Fogfv
;
1778 functions
->FrontFace
= r700FrontFace
;
1779 functions
->ShadeModel
= r700ShadeModel
;
1780 functions
->LogicOpcode
= r700LogicOpcode
;
1782 /* ARB_point_parameters */
1783 functions
->PointParameterfv
= r700PointParameter
;
1785 /* Stencil related */
1786 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1787 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1788 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1790 /* Viewport related */
1791 functions
->Viewport
= r700Viewport
;
1792 functions
->DepthRange
= r700DepthRange
;
1793 functions
->PointSize
= r700PointSize
;
1794 functions
->LineWidth
= r700LineWidth
;
1795 functions
->LineStipple
= r700LineStipple
;
1797 functions
->PolygonOffset
= r700PolygonOffset
;
1798 functions
->PolygonMode
= r700PolygonMode
;
1800 functions
->RenderMode
= r700RenderMode
;
1802 functions
->ClipPlane
= r700ClipPlane
;
1804 functions
->Scissor
= radeonScissor
;
1806 functions
->DrawBuffer
= radeonDrawBuffer
;
1807 functions
->ReadBuffer
= radeonReadBuffer
;