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Merge branch 'mesa_7_6_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57
58 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
59 static void r700UpdatePolygonMode(GLcontext * ctx);
60 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
61 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
62
63 void r700UpdateShaders(GLcontext * ctx)
64 {
65 context_t *context = R700_CONTEXT(ctx);
66
67 /* should only happenen once, just after context is created */
68 /* TODO: shouldn't we fallback to sw here? */
69 if (!ctx->FragmentProgram._Current) {
70 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
71 return;
72 }
73
74 r700SelectFragmentShader(ctx);
75
76 r700SelectVertexShader(ctx);
77 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
78 context->radeon.NewGLState = 0;
79 }
80
81 /*
82 * To correctly position primitives:
83 */
84 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
85 {
86 context_t *context = R700_CONTEXT(ctx);
87 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
88 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
89 GLfloat xoffset = (GLfloat) dPriv->x;
90 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
91 const GLfloat *v = ctx->Viewport._WindowMap.m;
92 int id = 0;
93
94 GLfloat tx = v[MAT_TX] + xoffset;
95 GLfloat ty = (-v[MAT_TY]) + yoffset;
96
97 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
98 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
99 /* Note: this should also modify whatever data the context reset
100 * code uses...
101 */
102 R600_STATECHANGE(context, vpt);
103 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
104 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
105 }
106
107 radeonUpdateScissor(ctx);
108 }
109
110 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
111 {
112 struct r700_fragment_program *fp =
113 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
114 struct gl_program_parameter_list *paramList;
115
116 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
117 return;
118
119 if (!ctx->FragmentProgram._Current || !fp)
120 return;
121
122 paramList = ctx->FragmentProgram._Current->Base.Parameters;
123
124 if (!paramList)
125 return;
126
127 _mesa_load_state_parameters(ctx, paramList);
128
129 }
130
131 /**
132 * Called by Mesa after an internal state update.
133 */
134 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
135 {
136 context_t *context = R700_CONTEXT(ctx);
137
138 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
139
140 _swrast_InvalidateState(ctx, new_state);
141 _swsetup_InvalidateState(ctx, new_state);
142 _vbo_InvalidateState(ctx, new_state);
143 _tnl_InvalidateState(ctx, new_state);
144 _ae_invalidate_state(ctx, new_state);
145
146 if (new_state & _NEW_BUFFERS) {
147 _mesa_update_framebuffer(ctx);
148 /* this updates the DrawBuffer's Width/Height if it's a FBO */
149 _mesa_update_draw_buffer_bounds(ctx);
150
151 R600_STATECHANGE(context, cb_target);
152 R600_STATECHANGE(context, db_target);
153 }
154
155 if (new_state & (_NEW_LIGHT)) {
156 R600_STATECHANGE(context, su);
157 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
158 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
159 else
160 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
161 }
162
163 r700UpdateStateParameters(ctx, new_state);
164
165 R600_STATECHANGE(context, cl);
166 R600_STATECHANGE(context, spi);
167
168 if(GL_TRUE == r700->bEnablePerspective)
169 {
170 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
171 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
172 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
173
174 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
175
176 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
177 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
178 }
179 else
180 {
181 /* For orthogonal case. */
182 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
183 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
184
185 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
186
187 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
188 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
189 }
190
191 context->radeon.NewGLState |= new_state;
192 }
193
194 static void r700SetDepthState(GLcontext * ctx)
195 {
196 context_t *context = R700_CONTEXT(ctx);
197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
198
199 R600_STATECHANGE(context, db);
200
201 if (ctx->Depth.Test)
202 {
203 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
204 if (ctx->Depth.Mask)
205 {
206 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
207 }
208 else
209 {
210 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
211 }
212
213 switch (ctx->Depth.Func)
214 {
215 case GL_NEVER:
216 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
217 ZFUNC_shift, ZFUNC_mask);
218 break;
219 case GL_LESS:
220 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
221 ZFUNC_shift, ZFUNC_mask);
222 break;
223 case GL_EQUAL:
224 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
225 ZFUNC_shift, ZFUNC_mask);
226 break;
227 case GL_LEQUAL:
228 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
229 ZFUNC_shift, ZFUNC_mask);
230 break;
231 case GL_GREATER:
232 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
233 ZFUNC_shift, ZFUNC_mask);
234 break;
235 case GL_NOTEQUAL:
236 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
237 ZFUNC_shift, ZFUNC_mask);
238 break;
239 case GL_GEQUAL:
240 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
241 ZFUNC_shift, ZFUNC_mask);
242 break;
243 case GL_ALWAYS:
244 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
245 ZFUNC_shift, ZFUNC_mask);
246 break;
247 default:
248 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
249 ZFUNC_shift, ZFUNC_mask);
250 break;
251 }
252 }
253 else
254 {
255 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
256 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
257 }
258 }
259
260 static void r700SetAlphaState(GLcontext * ctx)
261 {
262 context_t *context = R700_CONTEXT(ctx);
263 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
264 uint32_t alpha_func = REF_ALWAYS;
265 GLboolean really_enabled = ctx->Color.AlphaEnabled;
266
267 R600_STATECHANGE(context, sx);
268
269 switch (ctx->Color.AlphaFunc) {
270 case GL_NEVER:
271 alpha_func = REF_NEVER;
272 break;
273 case GL_LESS:
274 alpha_func = REF_LESS;
275 break;
276 case GL_EQUAL:
277 alpha_func = REF_EQUAL;
278 break;
279 case GL_LEQUAL:
280 alpha_func = REF_LEQUAL;
281 break;
282 case GL_GREATER:
283 alpha_func = REF_GREATER;
284 break;
285 case GL_NOTEQUAL:
286 alpha_func = REF_NOTEQUAL;
287 break;
288 case GL_GEQUAL:
289 alpha_func = REF_GEQUAL;
290 break;
291 case GL_ALWAYS:
292 /*alpha_func = REF_ALWAYS; */
293 really_enabled = GL_FALSE;
294 break;
295 }
296
297 if (really_enabled) {
298 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
299 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
300 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
301 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
302 } else {
303 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
304 }
305
306 }
307
308 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
309 {
310 (void)func;
311 (void)ref;
312 r700SetAlphaState(ctx);
313 }
314
315
316 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
317 {
318 context_t *context = R700_CONTEXT(ctx);
319 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
320
321 R600_STATECHANGE(context, blnd_clr);
322
323 r700->CB_BLEND_RED.f32All = cf[0];
324 r700->CB_BLEND_GREEN.f32All = cf[1];
325 r700->CB_BLEND_BLUE.f32All = cf[2];
326 r700->CB_BLEND_ALPHA.f32All = cf[3];
327 }
328
329 static int blend_factor(GLenum factor, GLboolean is_src)
330 {
331 switch (factor) {
332 case GL_ZERO:
333 return BLEND_ZERO;
334 break;
335 case GL_ONE:
336 return BLEND_ONE;
337 break;
338 case GL_DST_COLOR:
339 return BLEND_DST_COLOR;
340 break;
341 case GL_ONE_MINUS_DST_COLOR:
342 return BLEND_ONE_MINUS_DST_COLOR;
343 break;
344 case GL_SRC_COLOR:
345 return BLEND_SRC_COLOR;
346 break;
347 case GL_ONE_MINUS_SRC_COLOR:
348 return BLEND_ONE_MINUS_SRC_COLOR;
349 break;
350 case GL_SRC_ALPHA:
351 return BLEND_SRC_ALPHA;
352 break;
353 case GL_ONE_MINUS_SRC_ALPHA:
354 return BLEND_ONE_MINUS_SRC_ALPHA;
355 break;
356 case GL_DST_ALPHA:
357 return BLEND_DST_ALPHA;
358 break;
359 case GL_ONE_MINUS_DST_ALPHA:
360 return BLEND_ONE_MINUS_DST_ALPHA;
361 break;
362 case GL_SRC_ALPHA_SATURATE:
363 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
364 break;
365 case GL_CONSTANT_COLOR:
366 return BLEND_CONSTANT_COLOR;
367 break;
368 case GL_ONE_MINUS_CONSTANT_COLOR:
369 return BLEND_ONE_MINUS_CONSTANT_COLOR;
370 break;
371 case GL_CONSTANT_ALPHA:
372 return BLEND_CONSTANT_ALPHA;
373 break;
374 case GL_ONE_MINUS_CONSTANT_ALPHA:
375 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
376 break;
377 default:
378 fprintf(stderr, "unknown blend factor %x\n", factor);
379 return (is_src) ? BLEND_ONE : BLEND_ZERO;
380 break;
381 }
382 }
383
384 static void r700SetBlendState(GLcontext * ctx)
385 {
386 context_t *context = R700_CONTEXT(ctx);
387 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
388 int id = 0;
389 uint32_t blend_reg = 0, eqn, eqnA;
390
391 R600_STATECHANGE(context, blnd);
392
393 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
394 SETfield(blend_reg,
395 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
396 SETfield(blend_reg,
397 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
398 SETfield(blend_reg,
399 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
400 SETfield(blend_reg,
401 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
402 SETfield(blend_reg,
403 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
404 SETfield(blend_reg,
405 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
406 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
407 r700->CB_BLEND_CONTROL.u32All = blend_reg;
408 else
409 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
410 return;
411 }
412
413 SETfield(blend_reg,
414 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
415 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
416 SETfield(blend_reg,
417 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
418 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
419
420 switch (ctx->Color.BlendEquationRGB) {
421 case GL_FUNC_ADD:
422 eqn = COMB_DST_PLUS_SRC;
423 break;
424 case GL_FUNC_SUBTRACT:
425 eqn = COMB_SRC_MINUS_DST;
426 break;
427 case GL_FUNC_REVERSE_SUBTRACT:
428 eqn = COMB_DST_MINUS_SRC;
429 break;
430 case GL_MIN:
431 eqn = COMB_MIN_DST_SRC;
432 SETfield(blend_reg,
433 BLEND_ONE,
434 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
435 SETfield(blend_reg,
436 BLEND_ONE,
437 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
438 break;
439 case GL_MAX:
440 eqn = COMB_MAX_DST_SRC;
441 SETfield(blend_reg,
442 BLEND_ONE,
443 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
444 SETfield(blend_reg,
445 BLEND_ONE,
446 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
447 break;
448
449 default:
450 fprintf(stderr,
451 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
452 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
453 return;
454 }
455 SETfield(blend_reg,
456 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
457
458 SETfield(blend_reg,
459 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
460 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
461 SETfield(blend_reg,
462 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
463 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
464
465 switch (ctx->Color.BlendEquationA) {
466 case GL_FUNC_ADD:
467 eqnA = COMB_DST_PLUS_SRC;
468 break;
469 case GL_FUNC_SUBTRACT:
470 eqnA = COMB_SRC_MINUS_DST;
471 break;
472 case GL_FUNC_REVERSE_SUBTRACT:
473 eqnA = COMB_DST_MINUS_SRC;
474 break;
475 case GL_MIN:
476 eqnA = COMB_MIN_DST_SRC;
477 SETfield(blend_reg,
478 BLEND_ONE,
479 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
480 SETfield(blend_reg,
481 BLEND_ONE,
482 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
483 break;
484 case GL_MAX:
485 eqnA = COMB_MAX_DST_SRC;
486 SETfield(blend_reg,
487 BLEND_ONE,
488 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
489 SETfield(blend_reg,
490 BLEND_ONE,
491 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
492 break;
493 default:
494 fprintf(stderr,
495 "[%s:%u] Invalid A blend equation (0x%04x).\n",
496 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
497 return;
498 }
499
500 SETfield(blend_reg,
501 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
502
503 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
504
505 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
506 r700->CB_BLEND_CONTROL.u32All = blend_reg;
507 else {
508 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
509 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
510 }
511 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
512 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
513
514 }
515
516 static void r700BlendEquationSeparate(GLcontext * ctx,
517 GLenum modeRGB, GLenum modeA) //-----------------
518 {
519 r700SetBlendState(ctx);
520 }
521
522 static void r700BlendFuncSeparate(GLcontext * ctx,
523 GLenum sfactorRGB, GLenum dfactorRGB,
524 GLenum sfactorA, GLenum dfactorA) //------------------------
525 {
526 r700SetBlendState(ctx);
527 }
528
529 /**
530 * Translate LogicOp enums into hardware representation.
531 */
532 static GLuint translate_logicop(GLenum logicop)
533 {
534 switch (logicop) {
535 case GL_CLEAR:
536 return 0x00;
537 case GL_SET:
538 return 0xff;
539 case GL_COPY:
540 return 0xcc;
541 case GL_COPY_INVERTED:
542 return 0x33;
543 case GL_NOOP:
544 return 0xaa;
545 case GL_INVERT:
546 return 0x55;
547 case GL_AND:
548 return 0x88;
549 case GL_NAND:
550 return 0x77;
551 case GL_OR:
552 return 0xee;
553 case GL_NOR:
554 return 0x11;
555 case GL_XOR:
556 return 0x66;
557 case GL_EQUIV:
558 return 0xaa;
559 case GL_AND_REVERSE:
560 return 0x44;
561 case GL_AND_INVERTED:
562 return 0x22;
563 case GL_OR_REVERSE:
564 return 0xdd;
565 case GL_OR_INVERTED:
566 return 0xbb;
567 default:
568 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
569 return 0xcc;
570 }
571 }
572
573 /**
574 * Used internally to update the r300->hw hardware state to match the
575 * current OpenGL state.
576 */
577 static void r700SetLogicOpState(GLcontext *ctx)
578 {
579 context_t *context = R700_CONTEXT(ctx);
580 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
581
582 R600_STATECHANGE(context, blnd);
583
584 if (RGBA_LOGICOP_ENABLED(ctx))
585 SETfield(r700->CB_COLOR_CONTROL.u32All,
586 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
587 else
588 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
589 }
590
591 /**
592 * Called by Mesa when an application program changes the LogicOp state
593 * via glLogicOp.
594 */
595 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
596 {
597 if (RGBA_LOGICOP_ENABLED(ctx))
598 r700SetLogicOpState(ctx);
599 }
600
601 static void r700UpdateCulling(GLcontext * ctx)
602 {
603 context_t *context = R700_CONTEXT(ctx);
604 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
605
606 R600_STATECHANGE(context, su);
607
608 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
609 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
610 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
611
612 if (ctx->Polygon.CullFlag)
613 {
614 switch (ctx->Polygon.CullFaceMode)
615 {
616 case GL_FRONT:
617 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
618 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
619 break;
620 case GL_BACK:
621 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
622 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
623 break;
624 case GL_FRONT_AND_BACK:
625 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
626 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
627 break;
628 default:
629 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
630 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
631 break;
632 }
633 }
634
635 switch (ctx->Polygon.FrontFace)
636 {
637 case GL_CW:
638 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
639 break;
640 case GL_CCW:
641 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
642 break;
643 default:
644 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
645 break;
646 }
647 }
648
649 static void r700UpdateLineStipple(GLcontext * ctx)
650 {
651 context_t *context = R700_CONTEXT(ctx);
652 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
653
654 R600_STATECHANGE(context, sc);
655
656 if (ctx->Line.StippleFlag)
657 {
658 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
659 }
660 else
661 {
662 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
663 }
664 }
665
666 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
667 {
668 context_t *context = R700_CONTEXT(ctx);
669
670 switch (cap) {
671 case GL_TEXTURE_1D:
672 case GL_TEXTURE_2D:
673 case GL_TEXTURE_3D:
674 /* empty */
675 break;
676 case GL_FOG:
677 /* empty */
678 break;
679 case GL_ALPHA_TEST:
680 r700SetAlphaState(ctx);
681 break;
682 case GL_COLOR_LOGIC_OP:
683 r700SetLogicOpState(ctx);
684 /* fall-through, because logic op overrides blending */
685 case GL_BLEND:
686 r700SetBlendState(ctx);
687 break;
688 case GL_CLIP_PLANE0:
689 case GL_CLIP_PLANE1:
690 case GL_CLIP_PLANE2:
691 case GL_CLIP_PLANE3:
692 case GL_CLIP_PLANE4:
693 case GL_CLIP_PLANE5:
694 r700SetClipPlaneState(ctx, cap, state);
695 break;
696 case GL_DEPTH_TEST:
697 r700SetDepthState(ctx);
698 break;
699 case GL_STENCIL_TEST:
700 r700SetStencilState(ctx, state);
701 break;
702 case GL_CULL_FACE:
703 r700UpdateCulling(ctx);
704 break;
705 case GL_POLYGON_OFFSET_POINT:
706 case GL_POLYGON_OFFSET_LINE:
707 case GL_POLYGON_OFFSET_FILL:
708 r700SetPolygonOffsetState(ctx, state);
709 break;
710 case GL_SCISSOR_TEST:
711 radeon_firevertices(&context->radeon);
712 context->radeon.state.scissor.enabled = state;
713 radeonUpdateScissor(ctx);
714 break;
715 case GL_LINE_STIPPLE:
716 r700UpdateLineStipple(ctx);
717 break;
718 default:
719 break;
720 }
721
722 }
723
724 /**
725 * Handle glColorMask()
726 */
727 static void r700ColorMask(GLcontext * ctx,
728 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
729 {
730 context_t *context = R700_CONTEXT(ctx);
731 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
732 unsigned int mask = ((r ? 1 : 0) |
733 (g ? 2 : 0) |
734 (b ? 4 : 0) |
735 (a ? 8 : 0));
736
737 if (mask != r700->CB_TARGET_MASK.u32All) {
738 R600_STATECHANGE(context, cb);
739 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
740 }
741 }
742
743 /**
744 * Change the depth testing function.
745 *
746 * \note Mesa already filters redundant calls to this function.
747 */
748 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
749 {
750 r700SetDepthState(ctx);
751 }
752
753 /**
754 * Enable/Disable depth writing.
755 *
756 * \note Mesa already filters redundant calls to this function.
757 */
758 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
759 {
760 r700SetDepthState(ctx);
761 }
762
763 /**
764 * Change the culling mode.
765 *
766 * \note Mesa already filters redundant calls to this function.
767 */
768 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
769 {
770 r700UpdateCulling(ctx);
771 }
772
773 /* =============================================================
774 * Fog
775 */
776 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
777 {
778 }
779
780 /**
781 * Change the polygon orientation.
782 *
783 * \note Mesa already filters redundant calls to this function.
784 */
785 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
786 {
787 r700UpdateCulling(ctx);
788 r700UpdatePolygonMode(ctx);
789 }
790
791 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
792 {
793 context_t *context = R700_CONTEXT(ctx);
794 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
795
796 R600_STATECHANGE(context, spi);
797
798 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
799 switch (mode) {
800 case GL_FLAT:
801 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
802 break;
803 case GL_SMOOTH:
804 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
805 break;
806 default:
807 return;
808 }
809 }
810
811 /* =============================================================
812 * Point state
813 */
814 static void r700PointSize(GLcontext * ctx, GLfloat size)
815 {
816 context_t *context = R700_CONTEXT(ctx);
817 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
818
819 R600_STATECHANGE(context, su);
820
821 /* We need to clamp to user defined range here, because
822 * the HW clamping happens only for per vertex point size. */
823 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
824
825 /* same size limits for AA, non-AA points */
826 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
827
828 /* format is 12.4 fixed point */
829 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
830 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
831 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
832 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
833
834 }
835
836 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
837 {
838 context_t *context = R700_CONTEXT(ctx);
839 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
840
841 R600_STATECHANGE(context, su);
842
843 /* format is 12.4 fixed point */
844 switch (pname) {
845 case GL_POINT_SIZE_MIN:
846 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
847 MIN_SIZE_shift, MIN_SIZE_mask);
848 break;
849 case GL_POINT_SIZE_MAX:
850 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
851 MAX_SIZE_shift, MAX_SIZE_mask);
852 break;
853 case GL_POINT_DISTANCE_ATTENUATION:
854 break;
855 case GL_POINT_FADE_THRESHOLD_SIZE:
856 break;
857 default:
858 break;
859 }
860 }
861
862 static int translate_stencil_func(int func)
863 {
864 switch (func) {
865 case GL_NEVER:
866 return REF_NEVER;
867 case GL_LESS:
868 return REF_LESS;
869 case GL_EQUAL:
870 return REF_EQUAL;
871 case GL_LEQUAL:
872 return REF_LEQUAL;
873 case GL_GREATER:
874 return REF_GREATER;
875 case GL_NOTEQUAL:
876 return REF_NOTEQUAL;
877 case GL_GEQUAL:
878 return REF_GEQUAL;
879 case GL_ALWAYS:
880 return REF_ALWAYS;
881 }
882 return 0;
883 }
884
885 static int translate_stencil_op(int op)
886 {
887 switch (op) {
888 case GL_KEEP:
889 return STENCIL_KEEP;
890 case GL_ZERO:
891 return STENCIL_ZERO;
892 case GL_REPLACE:
893 return STENCIL_REPLACE;
894 case GL_INCR:
895 return STENCIL_INCR_CLAMP;
896 case GL_DECR:
897 return STENCIL_DECR_CLAMP;
898 case GL_INCR_WRAP_EXT:
899 return STENCIL_INCR_WRAP;
900 case GL_DECR_WRAP_EXT:
901 return STENCIL_DECR_WRAP;
902 case GL_INVERT:
903 return STENCIL_INVERT;
904 default:
905 WARN_ONCE("Do not know how to translate stencil op");
906 return STENCIL_KEEP;
907 }
908 return 0;
909 }
910
911 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
912 {
913 context_t *context = R700_CONTEXT(ctx);
914 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
915 GLboolean hw_stencil = GL_FALSE;
916
917 if (ctx->DrawBuffer) {
918 struct radeon_renderbuffer *rrbStencil
919 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
920 hw_stencil = (rrbStencil && rrbStencil->bo);
921 }
922
923 if (hw_stencil) {
924 R600_STATECHANGE(context, db);
925 if (state) {
926 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
927 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
928 } else
929 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
930 }
931 }
932
933 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
934 GLenum func, GLint ref, GLuint mask) //---------------------
935 {
936 context_t *context = R700_CONTEXT(ctx);
937 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
938 const unsigned back = ctx->Stencil._BackFace;
939
940 R600_STATECHANGE(context, stencil);
941 R600_STATECHANGE(context, db);
942
943 //front
944 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
945 STENCILREF_shift, STENCILREF_mask);
946 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
947 STENCILMASK_shift, STENCILMASK_mask);
948
949 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
950 STENCILFUNC_shift, STENCILFUNC_mask);
951
952 //back
953 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
954 STENCILREF_BF_shift, STENCILREF_BF_mask);
955 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
956 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
957
958 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
959 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
960
961 }
962
963 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
964 {
965 context_t *context = R700_CONTEXT(ctx);
966 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
967 const unsigned back = ctx->Stencil._BackFace;
968
969 R600_STATECHANGE(context, stencil);
970
971 // front
972 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
973 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
974
975 // back
976 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
977 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
978
979 }
980
981 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
982 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
983 {
984 context_t *context = R700_CONTEXT(ctx);
985 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
986 const unsigned back = ctx->Stencil._BackFace;
987
988 R600_STATECHANGE(context, db);
989
990 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
991 STENCILFAIL_shift, STENCILFAIL_mask);
992 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
993 STENCILZFAIL_shift, STENCILZFAIL_mask);
994 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
995 STENCILZPASS_shift, STENCILZPASS_mask);
996
997 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
998 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
999 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1000 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1001 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1002 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1003 }
1004
1005 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1006 {
1007 context_t *context = R700_CONTEXT(ctx);
1008 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1009 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1010 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1011 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1012 const GLfloat *v = ctx->Viewport._WindowMap.m;
1013 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1014 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1015 GLfloat y_scale, y_bias;
1016
1017 if (render_to_fbo) {
1018 y_scale = 1.0;
1019 y_bias = 0;
1020 } else {
1021 y_scale = -1.0;
1022 y_bias = yoffset;
1023 }
1024
1025 GLfloat sx = v[MAT_SX];
1026 GLfloat tx = v[MAT_TX] + xoffset;
1027 GLfloat sy = v[MAT_SY] * y_scale;
1028 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1029 GLfloat sz = v[MAT_SZ] * depthScale;
1030 GLfloat tz = v[MAT_TZ] * depthScale;
1031
1032 R600_STATECHANGE(context, vpt);
1033 R600_STATECHANGE(context, cl);
1034
1035 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1036 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1037
1038 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1039 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1040
1041 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1042 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1043
1044 if (ctx->Transform.DepthClamp) {
1045 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1046 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1047 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1048 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1049 } else {
1050 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1051 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1052 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1053 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1054 }
1055
1056 r700->viewport[id].enabled = GL_TRUE;
1057
1058 r700SetScissor(context);
1059 }
1060
1061
1062 static void r700Viewport(GLcontext * ctx,
1063 GLint x,
1064 GLint y,
1065 GLsizei width,
1066 GLsizei height) //--------------------
1067 {
1068 r700UpdateWindow(ctx, 0);
1069
1070 radeon_viewport(ctx, x, y, width, height);
1071 }
1072
1073 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1074 {
1075 r700UpdateWindow(ctx, 0);
1076 }
1077
1078 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1079 {
1080 context_t *context = R700_CONTEXT(ctx);
1081 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1082 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1083
1084 R600_STATECHANGE(context, su);
1085
1086 if (lineWidth > 0xFFFF)
1087 lineWidth = 0xFFFF;
1088 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1089 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1090 }
1091
1092 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1093 {
1094 context_t *context = R700_CONTEXT(ctx);
1095 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1096
1097 R600_STATECHANGE(context, sc);
1098
1099 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1100 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1101 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1102 }
1103
1104 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1105 {
1106 context_t *context = R700_CONTEXT(ctx);
1107 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1108
1109 R600_STATECHANGE(context, su);
1110
1111 if (state) {
1112 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1113 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1114 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1115 } else {
1116 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1117 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1118 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1119 }
1120 }
1121
1122 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1123 {
1124 context_t *context = R700_CONTEXT(ctx);
1125 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1126 GLfloat constant = units;
1127 GLchar depth = 0;
1128
1129 R600_STATECHANGE(context, poly);
1130
1131 switch (ctx->Visual.depthBits) {
1132 case 16:
1133 constant *= 4.0;
1134 depth = -16;
1135 break;
1136 case 24:
1137 constant *= 2.0;
1138 depth = -24;
1139 break;
1140 }
1141
1142 factor *= 12.0;
1143 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1144 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1145 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1146 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1147 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1148 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1149 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1150 }
1151
1152 static void r700UpdatePolygonMode(GLcontext * ctx)
1153 {
1154 context_t *context = R700_CONTEXT(ctx);
1155 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1156
1157 R600_STATECHANGE(context, su);
1158
1159 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1160
1161 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1162 if (ctx->Polygon.FrontMode != GL_FILL ||
1163 ctx->Polygon.BackMode != GL_FILL) {
1164 GLenum f, b;
1165
1166 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1167 * correctly by selecting the correct front and back face
1168 */
1169 if (ctx->Polygon.FrontFace == GL_CCW) {
1170 f = ctx->Polygon.FrontMode;
1171 b = ctx->Polygon.BackMode;
1172 } else {
1173 f = ctx->Polygon.BackMode;
1174 b = ctx->Polygon.FrontMode;
1175 }
1176
1177 /* Enable polygon mode */
1178 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1179
1180 switch (f) {
1181 case GL_LINE:
1182 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1183 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1184 break;
1185 case GL_POINT:
1186 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1187 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1188 break;
1189 case GL_FILL:
1190 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1191 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1192 break;
1193 }
1194
1195 switch (b) {
1196 case GL_LINE:
1197 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1198 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1199 break;
1200 case GL_POINT:
1201 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1202 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1203 break;
1204 case GL_FILL:
1205 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1206 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1207 break;
1208 }
1209 }
1210 }
1211
1212 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1213 {
1214 (void)face;
1215 (void)mode;
1216
1217 r700UpdatePolygonMode(ctx);
1218 }
1219
1220 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1221 {
1222 }
1223
1224 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1225 {
1226 context_t *context = R700_CONTEXT(ctx);
1227 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1228 GLint p;
1229 GLint *ip;
1230
1231 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1232 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1233
1234 R600_STATECHANGE(context, ucp);
1235
1236 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1237 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1238 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1239 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1240 }
1241
1242 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1243 {
1244 context_t *context = R700_CONTEXT(ctx);
1245 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1246 GLuint p;
1247
1248 p = cap - GL_CLIP_PLANE0;
1249
1250 R600_STATECHANGE(context, cl);
1251
1252 if (state) {
1253 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1254 r700->ucp[p].enabled = GL_TRUE;
1255 r700ClipPlane(ctx, cap, NULL);
1256 } else {
1257 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1258 r700->ucp[p].enabled = GL_FALSE;
1259 }
1260 }
1261
1262 void r700SetScissor(context_t *context) //---------------
1263 {
1264 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1265 unsigned x1, y1, x2, y2;
1266 int id = 0;
1267 struct radeon_renderbuffer *rrb;
1268
1269 rrb = radeon_get_colorbuffer(&context->radeon);
1270 if (!rrb || !rrb->bo) {
1271 return;
1272 }
1273 if (context->radeon.state.scissor.enabled) {
1274 x1 = context->radeon.state.scissor.rect.x1;
1275 y1 = context->radeon.state.scissor.rect.y1;
1276 x2 = context->radeon.state.scissor.rect.x2;
1277 y2 = context->radeon.state.scissor.rect.y2;
1278 /* r600 has exclusive BR scissors */
1279 if (context->radeon.radeonScreen->kernel_mm) {
1280 x2++;
1281 y2++;
1282 }
1283 } else {
1284 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1285 x1 = 0;
1286 y1 = 0;
1287 x2 = rrb->base.Width;
1288 y2 = rrb->base.Height;
1289 } else {
1290 x1 = rrb->dPriv->x;
1291 y1 = rrb->dPriv->y;
1292 x2 = rrb->dPriv->x + rrb->dPriv->w;
1293 y2 = rrb->dPriv->y + rrb->dPriv->h;
1294 }
1295 }
1296
1297 R600_STATECHANGE(context, scissor);
1298
1299 /* screen */
1300 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1301 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1302 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1303 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1304 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1305
1306 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1307 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1308 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1309 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1310
1311 /* window */
1312 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1313 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1314 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1315 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1316 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1317
1318 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1319 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1320 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1321 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1322
1323
1324 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1325 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1326 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1327 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1328 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1329 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1330 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1331 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1332
1333 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1334 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1335 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1336 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1337 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1338 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1339
1340 /* more....2d clip */
1341 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1342 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1343 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1344 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1345 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1346 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1347 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1348 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1349 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1350
1351 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1352 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1353 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1354 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1355 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1356 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1357 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1358 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1359 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1360
1361 r700->viewport[id].enabled = GL_TRUE;
1362 }
1363
1364 static void r700InitSQConfig(GLcontext * ctx)
1365 {
1366 context_t *context = R700_CONTEXT(ctx);
1367 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1368 int ps_prio;
1369 int vs_prio;
1370 int gs_prio;
1371 int es_prio;
1372 int num_ps_gprs;
1373 int num_vs_gprs;
1374 int num_gs_gprs;
1375 int num_es_gprs;
1376 int num_temp_gprs;
1377 int num_ps_threads;
1378 int num_vs_threads;
1379 int num_gs_threads;
1380 int num_es_threads;
1381 int num_ps_stack_entries;
1382 int num_vs_stack_entries;
1383 int num_gs_stack_entries;
1384 int num_es_stack_entries;
1385
1386 R600_STATECHANGE(context, sq);
1387
1388 // SQ
1389 ps_prio = 0;
1390 vs_prio = 1;
1391 gs_prio = 2;
1392 es_prio = 3;
1393 switch (context->radeon.radeonScreen->chip_family) {
1394 case CHIP_FAMILY_R600:
1395 num_ps_gprs = 192;
1396 num_vs_gprs = 56;
1397 num_temp_gprs = 4;
1398 num_gs_gprs = 0;
1399 num_es_gprs = 0;
1400 num_ps_threads = 136;
1401 num_vs_threads = 48;
1402 num_gs_threads = 4;
1403 num_es_threads = 4;
1404 num_ps_stack_entries = 128;
1405 num_vs_stack_entries = 128;
1406 num_gs_stack_entries = 0;
1407 num_es_stack_entries = 0;
1408 break;
1409 case CHIP_FAMILY_RV630:
1410 case CHIP_FAMILY_RV635:
1411 num_ps_gprs = 84;
1412 num_vs_gprs = 36;
1413 num_temp_gprs = 4;
1414 num_gs_gprs = 0;
1415 num_es_gprs = 0;
1416 num_ps_threads = 144;
1417 num_vs_threads = 40;
1418 num_gs_threads = 4;
1419 num_es_threads = 4;
1420 num_ps_stack_entries = 40;
1421 num_vs_stack_entries = 40;
1422 num_gs_stack_entries = 32;
1423 num_es_stack_entries = 16;
1424 break;
1425 case CHIP_FAMILY_RV610:
1426 case CHIP_FAMILY_RV620:
1427 case CHIP_FAMILY_RS780:
1428 case CHIP_FAMILY_RS880:
1429 default:
1430 num_ps_gprs = 84;
1431 num_vs_gprs = 36;
1432 num_temp_gprs = 4;
1433 num_gs_gprs = 0;
1434 num_es_gprs = 0;
1435 num_ps_threads = 136;
1436 num_vs_threads = 48;
1437 num_gs_threads = 4;
1438 num_es_threads = 4;
1439 num_ps_stack_entries = 40;
1440 num_vs_stack_entries = 40;
1441 num_gs_stack_entries = 32;
1442 num_es_stack_entries = 16;
1443 break;
1444 case CHIP_FAMILY_RV670:
1445 num_ps_gprs = 144;
1446 num_vs_gprs = 40;
1447 num_temp_gprs = 4;
1448 num_gs_gprs = 0;
1449 num_es_gprs = 0;
1450 num_ps_threads = 136;
1451 num_vs_threads = 48;
1452 num_gs_threads = 4;
1453 num_es_threads = 4;
1454 num_ps_stack_entries = 40;
1455 num_vs_stack_entries = 40;
1456 num_gs_stack_entries = 32;
1457 num_es_stack_entries = 16;
1458 break;
1459 case CHIP_FAMILY_RV770:
1460 num_ps_gprs = 192;
1461 num_vs_gprs = 56;
1462 num_temp_gprs = 4;
1463 num_gs_gprs = 0;
1464 num_es_gprs = 0;
1465 num_ps_threads = 188;
1466 num_vs_threads = 60;
1467 num_gs_threads = 0;
1468 num_es_threads = 0;
1469 num_ps_stack_entries = 256;
1470 num_vs_stack_entries = 256;
1471 num_gs_stack_entries = 0;
1472 num_es_stack_entries = 0;
1473 break;
1474 case CHIP_FAMILY_RV730:
1475 case CHIP_FAMILY_RV740:
1476 num_ps_gprs = 84;
1477 num_vs_gprs = 36;
1478 num_temp_gprs = 4;
1479 num_gs_gprs = 0;
1480 num_es_gprs = 0;
1481 num_ps_threads = 188;
1482 num_vs_threads = 60;
1483 num_gs_threads = 0;
1484 num_es_threads = 0;
1485 num_ps_stack_entries = 128;
1486 num_vs_stack_entries = 128;
1487 num_gs_stack_entries = 0;
1488 num_es_stack_entries = 0;
1489 break;
1490 case CHIP_FAMILY_RV710:
1491 num_ps_gprs = 192;
1492 num_vs_gprs = 56;
1493 num_temp_gprs = 4;
1494 num_gs_gprs = 0;
1495 num_es_gprs = 0;
1496 num_ps_threads = 144;
1497 num_vs_threads = 48;
1498 num_gs_threads = 0;
1499 num_es_threads = 0;
1500 num_ps_stack_entries = 128;
1501 num_vs_stack_entries = 128;
1502 num_gs_stack_entries = 0;
1503 num_es_stack_entries = 0;
1504 break;
1505 }
1506
1507 r700->sq_config.SQ_CONFIG.u32All = 0;
1508 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1509 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1510 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1511 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1512 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1513 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1514 else
1515 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1516 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1517 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1518 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1519 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1520 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1521 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1522
1523 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1524 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1525 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1526 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1527 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1528
1529 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1530 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1531 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1532
1533 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1534 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1535 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1536 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1537 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1538 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1539 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1540 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1541 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1542
1543 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1544 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1545 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1546 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1547 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1548
1549 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1550 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1551 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1552 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1553 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1554
1555 }
1556
1557 /**
1558 * Calculate initial hardware state and register state functions.
1559 * Assumes that the command buffer and state atoms have been
1560 * initialized already.
1561 */
1562 void r700InitState(GLcontext * ctx) //-------------------
1563 {
1564 context_t *context = R700_CONTEXT(ctx);
1565 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1566 int id = 0;
1567
1568 radeon_firevertices(&context->radeon);
1569
1570 r700->TA_CNTL_AUX.u32All = 0;
1571 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1572 r700->VC_ENHANCE.u32All = 0;
1573 r700->DB_WATERMARKS.u32All = 0;
1574 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1575 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1576 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1577 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1578 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1579 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1580 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1581 r700->DB_DEBUG.u32All = 0x82000000;
1582 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1583 } else {
1584 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1585 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1586 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1587 }
1588
1589 /* Turn off vgt reuse */
1590 r700->VGT_REUSE_OFF.u32All = 0;
1591 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1592
1593 /* Specify offsetting and clamp values for vertices */
1594 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1595 r700->VGT_MIN_VTX_INDX.u32All = 0;
1596 r700->VGT_INDX_OFFSET.u32All = 0;
1597
1598 /* default shader connections. */
1599 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1600 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1601 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1602 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1603
1604 r700->SPI_THREAD_GROUPING.u32All = 0;
1605 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1606 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1607
1608 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1609 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1610 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1611
1612 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1613 r700->PA_SC_EDGERULE.u32All = 0;
1614 else
1615 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1616
1617 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1618 r700->PA_SC_MODE_CNTL.u32All = 0;
1619 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1620 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1621 } else {
1622 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1623 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1624 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1625 }
1626
1627 /* Do scale XY and Z by 1/W0. */
1628 r700->bEnablePerspective = GL_TRUE;
1629 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1630 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1631 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1632
1633 /* Enable viewport scaling for all three axis */
1634 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1635 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1636 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1637 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1638 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1639 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1640
1641 /* GL uses last vtx for flat shading components */
1642 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1643
1644 /* Set up vertex control */
1645 r700->PA_SU_VTX_CNTL.u32All = 0;
1646 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1647 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1648 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1649 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1650
1651 /* to 1.0 = no guard band */
1652 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1653 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1654 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1655 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1656
1657 /* Enable all samples for multi-sample anti-aliasing */
1658 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1659 /* Turn off AA */
1660 r700->PA_SC_AA_CONFIG.u32All = 0;
1661
1662 r700->SX_MISC.u32All = 0;
1663
1664 r700InitSQConfig(ctx);
1665
1666 r700ColorMask(ctx,
1667 ctx->Color.ColorMask[RCOMP],
1668 ctx->Color.ColorMask[GCOMP],
1669 ctx->Color.ColorMask[BCOMP],
1670 ctx->Color.ColorMask[ACOMP]);
1671
1672 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1673 r700DepthMask(ctx, ctx->Depth.Mask);
1674 r700DepthFunc(ctx, ctx->Depth.Func);
1675 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1676
1677 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1678
1679 r700->DB_RENDER_CONTROL.u32All = 0;
1680 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1681 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1682 r700->DB_RENDER_OVERRIDE.u32All = 0;
1683 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1684 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1685 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1686 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1687 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1688 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
1689
1690 r700->DB_ALPHA_TO_MASK.u32All = 0;
1691 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1692 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1693 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1694 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1695
1696 /* stencil */
1697 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1698 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1699 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1700 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1701 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1702 ctx->Stencil.ZFailFunc[0],
1703 ctx->Stencil.ZPassFunc[0]);
1704
1705 r700UpdateCulling(ctx);
1706
1707 r700SetBlendState(ctx);
1708 r700SetLogicOpState(ctx);
1709
1710 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1711 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1712
1713 r700PointSize(ctx, 1.0);
1714
1715 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1716 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1717
1718 r700LineWidth(ctx, 1.0);
1719
1720 r700->PA_SC_LINE_CNTL.u32All = 0;
1721 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1722 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1723
1724 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1725 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1726 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1727 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1728 ctx->Polygon.OffsetUnits);
1729 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1730 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1731 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1732
1733 /* CB */
1734 r700BlendColor(ctx, ctx->Color.BlendColor);
1735
1736 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1737 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1738 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1739 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1740 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1741 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1742 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1743
1744 /* Disable color compares */
1745 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1746 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1747 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1748 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1749 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1750 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1751
1752 /* Zero out source */
1753 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1754
1755 /* Put a compare color in for error checking */
1756 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1757
1758 /* Set up color compare mask */
1759 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1760
1761 /* screen/window/view */
1762 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1763
1764 context->radeon.hw.all_dirty = GL_TRUE;
1765
1766 }
1767
1768 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1769 {
1770 functions->UpdateState = r700InvalidateState;
1771 functions->AlphaFunc = r700AlphaFunc;
1772 functions->BlendColor = r700BlendColor;
1773 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1774 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1775 functions->Enable = r700Enable;
1776 functions->ColorMask = r700ColorMask;
1777 functions->DepthFunc = r700DepthFunc;
1778 functions->DepthMask = r700DepthMask;
1779 functions->CullFace = r700CullFace;
1780 functions->Fogfv = r700Fogfv;
1781 functions->FrontFace = r700FrontFace;
1782 functions->ShadeModel = r700ShadeModel;
1783 functions->LogicOpcode = r700LogicOpcode;
1784
1785 /* ARB_point_parameters */
1786 functions->PointParameterfv = r700PointParameter;
1787
1788 /* Stencil related */
1789 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1790 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1791 functions->StencilOpSeparate = r700StencilOpSeparate;
1792
1793 /* Viewport related */
1794 functions->Viewport = r700Viewport;
1795 functions->DepthRange = r700DepthRange;
1796 functions->PointSize = r700PointSize;
1797 functions->LineWidth = r700LineWidth;
1798 functions->LineStipple = r700LineStipple;
1799
1800 functions->PolygonOffset = r700PolygonOffset;
1801 functions->PolygonMode = r700PolygonMode;
1802
1803 functions->RenderMode = r700RenderMode;
1804
1805 functions->ClipPlane = r700ClipPlane;
1806
1807 functions->Scissor = radeonScissor;
1808
1809 functions->DrawBuffer = radeonDrawBuffer;
1810 functions->ReadBuffer = radeonReadBuffer;
1811
1812 }
1813