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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63 static void r700SetRenderTarget(context_t *context, int id);
64 static void r700SetDepthTarget(context_t *context);
65
66 void r700SetDefaultStates(context_t *context) //--------------------
67 {
68
69 }
70
71 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
72 {
73 context_t *context = R700_CONTEXT(ctx);
74 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
75 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
76 int i;
77
78 /* should only happenen once, just after context is created */
79 /* TODO: shouldn't we fallback to sw here? */
80 if (!ctx->FragmentProgram._Current) {
81 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
82 return;
83 }
84
85 r700SelectFragmentShader(ctx);
86
87 if (context->radeon.NewGLState) {
88 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
89 /* mat states from state var not array for sw */
90 dummy_attrib[i].stride = 0;
91 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
92 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
93 }
94
95 _tnl_UpdateFixedFunctionProgram(ctx);
96
97 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
98 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
99 }
100 }
101
102 r700SelectVertexShader(ctx);
103 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
104 context->radeon.NewGLState = 0;
105 }
106
107 /*
108 * To correctly position primitives:
109 */
110 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
111 {
112 context_t *context = R700_CONTEXT(ctx);
113 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
114 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
115 GLfloat xoffset = (GLfloat) dPriv->x;
116 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
117 const GLfloat *v = ctx->Viewport._WindowMap.m;
118 int id = 0;
119
120 GLfloat tx = v[MAT_TX] + xoffset;
121 GLfloat ty = (-v[MAT_TY]) + yoffset;
122
123 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
124 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
125 /* Note: this should also modify whatever data the context reset
126 * code uses...
127 */
128 R600_STATECHANGE(context, vpt);
129 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
130 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
131 }
132
133 radeonUpdateScissor(ctx);
134 }
135
136 /**
137 * Tell the card where to render (offset, pitch).
138 * Effected by glDrawBuffer, etc
139 */
140 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
141 {
142 context_t *context = R700_CONTEXT(ctx);
143
144 R600_STATECHANGE(context, cb_target);
145 R600_STATECHANGE(context, db_target);
146
147 r700SetRenderTarget(context, 0);
148 r700SetDepthTarget(context);
149 }
150
151 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
152 {
153 struct r700_fragment_program *fp =
154 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
155 struct gl_program_parameter_list *paramList;
156
157 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
158 return;
159
160 if (!ctx->FragmentProgram._Current || !fp)
161 return;
162
163 paramList = ctx->FragmentProgram._Current->Base.Parameters;
164
165 if (!paramList)
166 return;
167
168 _mesa_load_state_parameters(ctx, paramList);
169
170 }
171
172 /**
173 * Called by Mesa after an internal state update.
174 */
175 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
176 {
177 context_t *context = R700_CONTEXT(ctx);
178
179 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
180
181 _swrast_InvalidateState(ctx, new_state);
182 _swsetup_InvalidateState(ctx, new_state);
183 _vbo_InvalidateState(ctx, new_state);
184 _tnl_InvalidateState(ctx, new_state);
185 _ae_invalidate_state(ctx, new_state);
186
187 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
188 {
189 _mesa_update_framebuffer(ctx);
190 /* this updates the DrawBuffer's Width/Height if it's a FBO */
191 _mesa_update_draw_buffer_bounds(ctx);
192
193 r700UpdateDrawBuffer(ctx);
194 }
195
196 r700UpdateStateParameters(ctx, new_state);
197
198 R600_STATECHANGE(context, cl);
199 R600_STATECHANGE(context, spi);
200
201 if(GL_TRUE == r700->bEnablePerspective)
202 {
203 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
204 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
205 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
206
207 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
208
209 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
210 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
211 }
212 else
213 {
214 /* For orthogonal case. */
215 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
216 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
217
218 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
219
220 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
221 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
222 }
223
224 context->radeon.NewGLState |= new_state;
225 }
226
227 static void r700SetDepthState(GLcontext * ctx)
228 {
229 context_t *context = R700_CONTEXT(ctx);
230 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
231
232 R600_STATECHANGE(context, db);
233
234 if (ctx->Depth.Test)
235 {
236 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
237 if (ctx->Depth.Mask)
238 {
239 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
240 }
241 else
242 {
243 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
244 }
245
246 switch (ctx->Depth.Func)
247 {
248 case GL_NEVER:
249 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
250 ZFUNC_shift, ZFUNC_mask);
251 break;
252 case GL_LESS:
253 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
254 ZFUNC_shift, ZFUNC_mask);
255 break;
256 case GL_EQUAL:
257 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
258 ZFUNC_shift, ZFUNC_mask);
259 break;
260 case GL_LEQUAL:
261 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
262 ZFUNC_shift, ZFUNC_mask);
263 break;
264 case GL_GREATER:
265 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
266 ZFUNC_shift, ZFUNC_mask);
267 break;
268 case GL_NOTEQUAL:
269 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
270 ZFUNC_shift, ZFUNC_mask);
271 break;
272 case GL_GEQUAL:
273 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
274 ZFUNC_shift, ZFUNC_mask);
275 break;
276 case GL_ALWAYS:
277 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
278 ZFUNC_shift, ZFUNC_mask);
279 break;
280 default:
281 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
282 ZFUNC_shift, ZFUNC_mask);
283 break;
284 }
285 }
286 else
287 {
288 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
289 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
290 }
291 }
292
293 static void r700SetAlphaState(GLcontext * ctx)
294 {
295 context_t *context = R700_CONTEXT(ctx);
296 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
297 uint32_t alpha_func = REF_ALWAYS;
298 GLboolean really_enabled = ctx->Color.AlphaEnabled;
299
300 R600_STATECHANGE(context, sx);
301
302 switch (ctx->Color.AlphaFunc) {
303 case GL_NEVER:
304 alpha_func = REF_NEVER;
305 break;
306 case GL_LESS:
307 alpha_func = REF_LESS;
308 break;
309 case GL_EQUAL:
310 alpha_func = REF_EQUAL;
311 break;
312 case GL_LEQUAL:
313 alpha_func = REF_LEQUAL;
314 break;
315 case GL_GREATER:
316 alpha_func = REF_GREATER;
317 break;
318 case GL_NOTEQUAL:
319 alpha_func = REF_NOTEQUAL;
320 break;
321 case GL_GEQUAL:
322 alpha_func = REF_GEQUAL;
323 break;
324 case GL_ALWAYS:
325 /*alpha_func = REF_ALWAYS; */
326 really_enabled = GL_FALSE;
327 break;
328 }
329
330 if (really_enabled) {
331 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
332 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
333 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
334 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
335 } else {
336 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
337 }
338
339 }
340
341 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
342 {
343 (void)func;
344 (void)ref;
345 r700SetAlphaState(ctx);
346 }
347
348
349 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
350 {
351 context_t *context = R700_CONTEXT(ctx);
352 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
353
354 R600_STATECHANGE(context, blnd_clr);
355
356 r700->CB_BLEND_RED.f32All = cf[0];
357 r700->CB_BLEND_GREEN.f32All = cf[1];
358 r700->CB_BLEND_BLUE.f32All = cf[2];
359 r700->CB_BLEND_ALPHA.f32All = cf[3];
360 }
361
362 static int blend_factor(GLenum factor, GLboolean is_src)
363 {
364 switch (factor) {
365 case GL_ZERO:
366 return BLEND_ZERO;
367 break;
368 case GL_ONE:
369 return BLEND_ONE;
370 break;
371 case GL_DST_COLOR:
372 return BLEND_DST_COLOR;
373 break;
374 case GL_ONE_MINUS_DST_COLOR:
375 return BLEND_ONE_MINUS_DST_COLOR;
376 break;
377 case GL_SRC_COLOR:
378 return BLEND_SRC_COLOR;
379 break;
380 case GL_ONE_MINUS_SRC_COLOR:
381 return BLEND_ONE_MINUS_SRC_COLOR;
382 break;
383 case GL_SRC_ALPHA:
384 return BLEND_SRC_ALPHA;
385 break;
386 case GL_ONE_MINUS_SRC_ALPHA:
387 return BLEND_ONE_MINUS_SRC_ALPHA;
388 break;
389 case GL_DST_ALPHA:
390 return BLEND_DST_ALPHA;
391 break;
392 case GL_ONE_MINUS_DST_ALPHA:
393 return BLEND_ONE_MINUS_DST_ALPHA;
394 break;
395 case GL_SRC_ALPHA_SATURATE:
396 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
397 break;
398 case GL_CONSTANT_COLOR:
399 return BLEND_CONSTANT_COLOR;
400 break;
401 case GL_ONE_MINUS_CONSTANT_COLOR:
402 return BLEND_ONE_MINUS_CONSTANT_COLOR;
403 break;
404 case GL_CONSTANT_ALPHA:
405 return BLEND_CONSTANT_ALPHA;
406 break;
407 case GL_ONE_MINUS_CONSTANT_ALPHA:
408 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
409 break;
410 default:
411 fprintf(stderr, "unknown blend factor %x\n", factor);
412 return (is_src) ? BLEND_ONE : BLEND_ZERO;
413 break;
414 }
415 }
416
417 static void r700SetBlendState(GLcontext * ctx)
418 {
419 context_t *context = R700_CONTEXT(ctx);
420 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
421 int id = 0;
422 uint32_t blend_reg = 0, eqn, eqnA;
423
424 R600_STATECHANGE(context, blnd);
425
426 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
427 SETfield(blend_reg,
428 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
429 SETfield(blend_reg,
430 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
431 SETfield(blend_reg,
432 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
433 SETfield(blend_reg,
434 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
435 SETfield(blend_reg,
436 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
437 SETfield(blend_reg,
438 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
439 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
440 r700->CB_BLEND_CONTROL.u32All = blend_reg;
441 else
442 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
443 return;
444 }
445
446 SETfield(blend_reg,
447 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
448 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
449 SETfield(blend_reg,
450 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
451 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
452
453 switch (ctx->Color.BlendEquationRGB) {
454 case GL_FUNC_ADD:
455 eqn = COMB_DST_PLUS_SRC;
456 break;
457 case GL_FUNC_SUBTRACT:
458 eqn = COMB_SRC_MINUS_DST;
459 break;
460 case GL_FUNC_REVERSE_SUBTRACT:
461 eqn = COMB_DST_MINUS_SRC;
462 break;
463 case GL_MIN:
464 eqn = COMB_MIN_DST_SRC;
465 SETfield(blend_reg,
466 BLEND_ONE,
467 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
468 SETfield(blend_reg,
469 BLEND_ONE,
470 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
471 break;
472 case GL_MAX:
473 eqn = COMB_MAX_DST_SRC;
474 SETfield(blend_reg,
475 BLEND_ONE,
476 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
477 SETfield(blend_reg,
478 BLEND_ONE,
479 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
480 break;
481
482 default:
483 fprintf(stderr,
484 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
485 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
486 return;
487 }
488 SETfield(blend_reg,
489 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
490
491 SETfield(blend_reg,
492 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
493 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
494 SETfield(blend_reg,
495 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
496 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
497
498 switch (ctx->Color.BlendEquationA) {
499 case GL_FUNC_ADD:
500 eqnA = COMB_DST_PLUS_SRC;
501 break;
502 case GL_FUNC_SUBTRACT:
503 eqnA = COMB_SRC_MINUS_DST;
504 break;
505 case GL_FUNC_REVERSE_SUBTRACT:
506 eqnA = COMB_DST_MINUS_SRC;
507 break;
508 case GL_MIN:
509 eqnA = COMB_MIN_DST_SRC;
510 SETfield(blend_reg,
511 BLEND_ONE,
512 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
513 SETfield(blend_reg,
514 BLEND_ONE,
515 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
516 break;
517 case GL_MAX:
518 eqnA = COMB_MAX_DST_SRC;
519 SETfield(blend_reg,
520 BLEND_ONE,
521 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
522 SETfield(blend_reg,
523 BLEND_ONE,
524 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
525 break;
526 default:
527 fprintf(stderr,
528 "[%s:%u] Invalid A blend equation (0x%04x).\n",
529 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
530 return;
531 }
532
533 SETfield(blend_reg,
534 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
535
536 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
537
538 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
539 r700->CB_BLEND_CONTROL.u32All = blend_reg;
540 else {
541 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
542 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
543 }
544 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
545 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
546
547 }
548
549 static void r700BlendEquationSeparate(GLcontext * ctx,
550 GLenum modeRGB, GLenum modeA) //-----------------
551 {
552 r700SetBlendState(ctx);
553 }
554
555 static void r700BlendFuncSeparate(GLcontext * ctx,
556 GLenum sfactorRGB, GLenum dfactorRGB,
557 GLenum sfactorA, GLenum dfactorA) //------------------------
558 {
559 r700SetBlendState(ctx);
560 }
561
562 /**
563 * Translate LogicOp enums into hardware representation.
564 */
565 static GLuint translate_logicop(GLenum logicop)
566 {
567 switch (logicop) {
568 case GL_CLEAR:
569 return 0x00;
570 case GL_SET:
571 return 0xff;
572 case GL_COPY:
573 return 0xcc;
574 case GL_COPY_INVERTED:
575 return 0x33;
576 case GL_NOOP:
577 return 0xaa;
578 case GL_INVERT:
579 return 0x55;
580 case GL_AND:
581 return 0x88;
582 case GL_NAND:
583 return 0x77;
584 case GL_OR:
585 return 0xee;
586 case GL_NOR:
587 return 0x11;
588 case GL_XOR:
589 return 0x66;
590 case GL_EQUIV:
591 return 0xaa;
592 case GL_AND_REVERSE:
593 return 0x44;
594 case GL_AND_INVERTED:
595 return 0x22;
596 case GL_OR_REVERSE:
597 return 0xdd;
598 case GL_OR_INVERTED:
599 return 0xbb;
600 default:
601 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
602 return 0xcc;
603 }
604 }
605
606 /**
607 * Used internally to update the r300->hw hardware state to match the
608 * current OpenGL state.
609 */
610 static void r700SetLogicOpState(GLcontext *ctx)
611 {
612 context_t *context = R700_CONTEXT(ctx);
613 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
614
615 R600_STATECHANGE(context, blnd);
616
617 if (RGBA_LOGICOP_ENABLED(ctx))
618 SETfield(r700->CB_COLOR_CONTROL.u32All,
619 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
620 else
621 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
622 }
623
624 /**
625 * Called by Mesa when an application program changes the LogicOp state
626 * via glLogicOp.
627 */
628 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
629 {
630 if (RGBA_LOGICOP_ENABLED(ctx))
631 r700SetLogicOpState(ctx);
632 }
633
634 static void r700UpdateCulling(GLcontext * ctx)
635 {
636 context_t *context = R700_CONTEXT(ctx);
637 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
638
639 R600_STATECHANGE(context, su);
640
641 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
642 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
643 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
644
645 if (ctx->Polygon.CullFlag)
646 {
647 switch (ctx->Polygon.CullFaceMode)
648 {
649 case GL_FRONT:
650 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
651 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
652 break;
653 case GL_BACK:
654 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
655 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
656 break;
657 case GL_FRONT_AND_BACK:
658 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
659 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
660 break;
661 default:
662 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
663 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
664 break;
665 }
666 }
667
668 switch (ctx->Polygon.FrontFace)
669 {
670 case GL_CW:
671 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
672 break;
673 case GL_CCW:
674 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
675 break;
676 default:
677 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
678 break;
679 }
680 }
681
682 static void r700UpdateLineStipple(GLcontext * ctx)
683 {
684 context_t *context = R700_CONTEXT(ctx);
685 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
686
687 R600_STATECHANGE(context, sc);
688
689 if (ctx->Line.StippleFlag)
690 {
691 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
692 }
693 else
694 {
695 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
696 }
697 }
698
699 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
700 {
701 context_t *context = R700_CONTEXT(ctx);
702
703 switch (cap) {
704 case GL_TEXTURE_1D:
705 case GL_TEXTURE_2D:
706 case GL_TEXTURE_3D:
707 /* empty */
708 break;
709 case GL_FOG:
710 /* empty */
711 break;
712 case GL_ALPHA_TEST:
713 r700SetAlphaState(ctx);
714 break;
715 case GL_COLOR_LOGIC_OP:
716 r700SetLogicOpState(ctx);
717 /* fall-through, because logic op overrides blending */
718 case GL_BLEND:
719 r700SetBlendState(ctx);
720 break;
721 case GL_CLIP_PLANE0:
722 case GL_CLIP_PLANE1:
723 case GL_CLIP_PLANE2:
724 case GL_CLIP_PLANE3:
725 case GL_CLIP_PLANE4:
726 case GL_CLIP_PLANE5:
727 r700SetClipPlaneState(ctx, cap, state);
728 break;
729 case GL_DEPTH_TEST:
730 r700SetDepthState(ctx);
731 break;
732 case GL_STENCIL_TEST:
733 r700SetStencilState(ctx, state);
734 break;
735 case GL_CULL_FACE:
736 r700UpdateCulling(ctx);
737 break;
738 case GL_POLYGON_OFFSET_POINT:
739 case GL_POLYGON_OFFSET_LINE:
740 case GL_POLYGON_OFFSET_FILL:
741 r700SetPolygonOffsetState(ctx, state);
742 break;
743 case GL_SCISSOR_TEST:
744 radeon_firevertices(&context->radeon);
745 context->radeon.state.scissor.enabled = state;
746 radeonUpdateScissor(ctx);
747 break;
748 case GL_LINE_STIPPLE:
749 r700UpdateLineStipple(ctx);
750 break;
751 default:
752 break;
753 }
754
755 }
756
757 /**
758 * Handle glColorMask()
759 */
760 static void r700ColorMask(GLcontext * ctx,
761 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
762 {
763 context_t *context = R700_CONTEXT(ctx);
764 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
765 unsigned int mask = ((r ? 1 : 0) |
766 (g ? 2 : 0) |
767 (b ? 4 : 0) |
768 (a ? 8 : 0));
769
770 if (mask != r700->CB_SHADER_MASK.u32All) {
771 R600_STATECHANGE(context, cb);
772 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
773 }
774 }
775
776 /**
777 * Change the depth testing function.
778 *
779 * \note Mesa already filters redundant calls to this function.
780 */
781 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
782 {
783 r700SetDepthState(ctx);
784 }
785
786 /**
787 * Enable/Disable depth writing.
788 *
789 * \note Mesa already filters redundant calls to this function.
790 */
791 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
792 {
793 r700SetDepthState(ctx);
794 }
795
796 /**
797 * Change the culling mode.
798 *
799 * \note Mesa already filters redundant calls to this function.
800 */
801 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
802 {
803 r700UpdateCulling(ctx);
804 }
805
806 /* =============================================================
807 * Fog
808 */
809 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
810 {
811 }
812
813 /**
814 * Change the polygon orientation.
815 *
816 * \note Mesa already filters redundant calls to this function.
817 */
818 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
819 {
820 r700UpdateCulling(ctx);
821 r700UpdatePolygonMode(ctx);
822 }
823
824 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
825 {
826 context_t *context = R700_CONTEXT(ctx);
827 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
828
829 R600_STATECHANGE(context, spi);
830
831 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
832 switch (mode) {
833 case GL_FLAT:
834 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
835 break;
836 case GL_SMOOTH:
837 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
838 break;
839 default:
840 return;
841 }
842 }
843
844 /* =============================================================
845 * Point state
846 */
847 static void r700PointSize(GLcontext * ctx, GLfloat size)
848 {
849 context_t *context = R700_CONTEXT(ctx);
850 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
851
852 R600_STATECHANGE(context, su);
853
854 /* We need to clamp to user defined range here, because
855 * the HW clamping happens only for per vertex point size. */
856 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
857
858 /* same size limits for AA, non-AA points */
859 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
860
861 /* format is 12.4 fixed point */
862 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
863 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
864 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
865 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
866
867 }
868
869 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
870 {
871 context_t *context = R700_CONTEXT(ctx);
872 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
873
874 R600_STATECHANGE(context, su);
875
876 /* format is 12.4 fixed point */
877 switch (pname) {
878 case GL_POINT_SIZE_MIN:
879 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
880 MIN_SIZE_shift, MIN_SIZE_mask);
881 break;
882 case GL_POINT_SIZE_MAX:
883 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
884 MAX_SIZE_shift, MAX_SIZE_mask);
885 break;
886 case GL_POINT_DISTANCE_ATTENUATION:
887 break;
888 case GL_POINT_FADE_THRESHOLD_SIZE:
889 break;
890 default:
891 break;
892 }
893 }
894
895 static int translate_stencil_func(int func)
896 {
897 switch (func) {
898 case GL_NEVER:
899 return REF_NEVER;
900 case GL_LESS:
901 return REF_LESS;
902 case GL_EQUAL:
903 return REF_EQUAL;
904 case GL_LEQUAL:
905 return REF_LEQUAL;
906 case GL_GREATER:
907 return REF_GREATER;
908 case GL_NOTEQUAL:
909 return REF_NOTEQUAL;
910 case GL_GEQUAL:
911 return REF_GEQUAL;
912 case GL_ALWAYS:
913 return REF_ALWAYS;
914 }
915 return 0;
916 }
917
918 static int translate_stencil_op(int op)
919 {
920 switch (op) {
921 case GL_KEEP:
922 return STENCIL_KEEP;
923 case GL_ZERO:
924 return STENCIL_ZERO;
925 case GL_REPLACE:
926 return STENCIL_REPLACE;
927 case GL_INCR:
928 return STENCIL_INCR_CLAMP;
929 case GL_DECR:
930 return STENCIL_DECR_CLAMP;
931 case GL_INCR_WRAP_EXT:
932 return STENCIL_INCR_WRAP;
933 case GL_DECR_WRAP_EXT:
934 return STENCIL_DECR_WRAP;
935 case GL_INVERT:
936 return STENCIL_INVERT;
937 default:
938 WARN_ONCE("Do not know how to translate stencil op");
939 return STENCIL_KEEP;
940 }
941 return 0;
942 }
943
944 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
945 {
946 context_t *context = R700_CONTEXT(ctx);
947 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
948 GLboolean hw_stencil = GL_FALSE;
949
950 if (ctx->DrawBuffer) {
951 struct radeon_renderbuffer *rrbStencil
952 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
953 hw_stencil = (rrbStencil && rrbStencil->bo);
954 }
955
956 if (hw_stencil) {
957 R600_STATECHANGE(context, db);
958 if (state) {
959 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
960 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
961 } else
962 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
963 }
964 }
965
966 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
967 GLenum func, GLint ref, GLuint mask) //---------------------
968 {
969 context_t *context = R700_CONTEXT(ctx);
970 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
971 const unsigned back = ctx->Stencil._BackFace;
972
973 R600_STATECHANGE(context, stencil);
974 R600_STATECHANGE(context, db);
975
976 //front
977 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
978 STENCILREF_shift, STENCILREF_mask);
979 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
980 STENCILMASK_shift, STENCILMASK_mask);
981
982 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
983 STENCILFUNC_shift, STENCILFUNC_mask);
984
985 //back
986 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
987 STENCILREF_BF_shift, STENCILREF_BF_mask);
988 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
989 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
990
991 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
992 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
993
994 }
995
996 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
997 {
998 context_t *context = R700_CONTEXT(ctx);
999 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1000 const unsigned back = ctx->Stencil._BackFace;
1001
1002 R600_STATECHANGE(context, stencil);
1003
1004 // front
1005 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1006 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1007
1008 // back
1009 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1010 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1011
1012 }
1013
1014 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1015 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1016 {
1017 context_t *context = R700_CONTEXT(ctx);
1018 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1019 const unsigned back = ctx->Stencil._BackFace;
1020
1021 R600_STATECHANGE(context, db);
1022
1023 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1024 STENCILFAIL_shift, STENCILFAIL_mask);
1025 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1026 STENCILZFAIL_shift, STENCILZFAIL_mask);
1027 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1028 STENCILZPASS_shift, STENCILZPASS_mask);
1029
1030 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1031 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1032 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1033 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1034 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1035 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1036 }
1037
1038 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1039 {
1040 context_t *context = R700_CONTEXT(ctx);
1041 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1042 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1043 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1044 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1045 const GLfloat *v = ctx->Viewport._WindowMap.m;
1046 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1047 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1048 GLfloat y_scale, y_bias;
1049
1050 if (render_to_fbo) {
1051 y_scale = 1.0;
1052 y_bias = 0;
1053 } else {
1054 y_scale = -1.0;
1055 y_bias = yoffset;
1056 }
1057
1058 GLfloat sx = v[MAT_SX];
1059 GLfloat tx = v[MAT_TX] + xoffset;
1060 GLfloat sy = v[MAT_SY] * y_scale;
1061 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1062 GLfloat sz = v[MAT_SZ] * depthScale;
1063 GLfloat tz = v[MAT_TZ] * depthScale;
1064
1065 R600_STATECHANGE(context, vpt);
1066
1067 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1068 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1069
1070 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1071 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1072
1073 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1074 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1075
1076 r700->viewport[id].enabled = GL_TRUE;
1077
1078 r700SetScissor(context);
1079 }
1080
1081
1082 static void r700Viewport(GLcontext * ctx,
1083 GLint x,
1084 GLint y,
1085 GLsizei width,
1086 GLsizei height) //--------------------
1087 {
1088 r700UpdateWindow(ctx, 0);
1089
1090 radeon_viewport(ctx, x, y, width, height);
1091 }
1092
1093 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1094 {
1095 r700UpdateWindow(ctx, 0);
1096 }
1097
1098 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1099 {
1100 context_t *context = R700_CONTEXT(ctx);
1101 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1102 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1103
1104 R600_STATECHANGE(context, su);
1105
1106 if (lineWidth > 0xFFFF)
1107 lineWidth = 0xFFFF;
1108 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1109 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1110 }
1111
1112 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1113 {
1114 context_t *context = R700_CONTEXT(ctx);
1115 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1116
1117 R600_STATECHANGE(context, sc);
1118
1119 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1120 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1121 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1122 }
1123
1124 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1125 {
1126 context_t *context = R700_CONTEXT(ctx);
1127 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1128
1129 R600_STATECHANGE(context, su);
1130
1131 if (state) {
1132 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1133 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1134 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1135 } else {
1136 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1137 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1138 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1139 }
1140 }
1141
1142 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1143 {
1144 context_t *context = R700_CONTEXT(ctx);
1145 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1146 GLfloat constant = units;
1147
1148 switch (ctx->Visual.depthBits) {
1149 case 16:
1150 constant *= 4.0;
1151 break;
1152 case 24:
1153 constant *= 2.0;
1154 break;
1155 }
1156
1157 factor *= 12.0;
1158
1159 R600_STATECHANGE(context, poly);
1160
1161 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1162 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1163 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1164 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1165 }
1166
1167 static void r700UpdatePolygonMode(GLcontext * ctx)
1168 {
1169 context_t *context = R700_CONTEXT(ctx);
1170 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1171
1172 R600_STATECHANGE(context, su);
1173
1174 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1175
1176 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1177 if (ctx->Polygon.FrontMode != GL_FILL ||
1178 ctx->Polygon.BackMode != GL_FILL) {
1179 GLenum f, b;
1180
1181 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1182 * correctly by selecting the correct front and back face
1183 */
1184 if (ctx->Polygon.FrontFace == GL_CCW) {
1185 f = ctx->Polygon.FrontMode;
1186 b = ctx->Polygon.BackMode;
1187 } else {
1188 f = ctx->Polygon.BackMode;
1189 b = ctx->Polygon.FrontMode;
1190 }
1191
1192 /* Enable polygon mode */
1193 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1194
1195 switch (f) {
1196 case GL_LINE:
1197 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1198 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1199 break;
1200 case GL_POINT:
1201 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1202 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1203 break;
1204 case GL_FILL:
1205 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1206 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1207 break;
1208 }
1209
1210 switch (b) {
1211 case GL_LINE:
1212 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1213 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1214 break;
1215 case GL_POINT:
1216 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1217 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1218 break;
1219 case GL_FILL:
1220 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1221 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1222 break;
1223 }
1224 }
1225 }
1226
1227 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1228 {
1229 (void)face;
1230 (void)mode;
1231
1232 r700UpdatePolygonMode(ctx);
1233 }
1234
1235 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1236 {
1237 }
1238
1239 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1240 {
1241 context_t *context = R700_CONTEXT(ctx);
1242 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1243 GLint p;
1244 GLint *ip;
1245
1246 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1247 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1248
1249 R600_STATECHANGE(context, ucp);
1250
1251 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1252 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1253 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1254 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1255 }
1256
1257 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1258 {
1259 context_t *context = R700_CONTEXT(ctx);
1260 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1261 GLuint p;
1262
1263 p = cap - GL_CLIP_PLANE0;
1264
1265 R600_STATECHANGE(context, cl);
1266
1267 if (state) {
1268 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1269 r700->ucp[p].enabled = GL_TRUE;
1270 r700ClipPlane(ctx, cap, NULL);
1271 } else {
1272 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1273 r700->ucp[p].enabled = GL_FALSE;
1274 }
1275 }
1276
1277 void r700SetScissor(context_t *context) //---------------
1278 {
1279 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1280 unsigned x1, y1, x2, y2;
1281 int id = 0;
1282 struct radeon_renderbuffer *rrb;
1283
1284 rrb = radeon_get_colorbuffer(&context->radeon);
1285 if (!rrb || !rrb->bo) {
1286 return;
1287 }
1288 if (context->radeon.state.scissor.enabled) {
1289 x1 = context->radeon.state.scissor.rect.x1;
1290 y1 = context->radeon.state.scissor.rect.y1;
1291 x2 = context->radeon.state.scissor.rect.x2;
1292 y2 = context->radeon.state.scissor.rect.y2;
1293 } else {
1294 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1295 x1 = 0;
1296 y1 = 0;
1297 x2 = rrb->base.Width - 1;
1298 y2 = rrb->base.Height - 1;
1299 } else {
1300 x1 = rrb->dPriv->x;
1301 y1 = rrb->dPriv->y;
1302 x2 = rrb->dPriv->x + rrb->dPriv->w;
1303 y2 = rrb->dPriv->y + rrb->dPriv->h;
1304 }
1305 }
1306
1307 R600_STATECHANGE(context, scissor);
1308
1309 /* screen */
1310 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1311 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1312 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1313 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1314 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1315
1316 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1317 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1318 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1319 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1320
1321 /* window */
1322 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1323 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1324 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1325 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1326 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1327
1328 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1329 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1330 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1331 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1332
1333
1334 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1335 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1336 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1337 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1338 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1339 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1340 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1341 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1342
1343 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1344 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1345 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1346 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1347 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1348 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1349
1350 /* more....2d clip */
1351 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1352 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1353 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1354 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1355 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1356 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1357 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1358 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1359 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1360
1361 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1362 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1363 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1364 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1365 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1366 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1367 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1368 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1369 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1370
1371 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1372 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1373 r700->viewport[id].enabled = GL_TRUE;
1374 }
1375
1376 static void r700SetRenderTarget(context_t *context, int id)
1377 {
1378 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1379
1380 struct radeon_renderbuffer *rrb;
1381 unsigned int nPitchInPixel;
1382
1383 rrb = radeon_get_colorbuffer(&context->radeon);
1384 if (!rrb || !rrb->bo) {
1385 return;
1386 }
1387
1388 R600_STATECHANGE(context, cb_target);
1389 R600_STATECHANGE(context, cb);
1390
1391 /* screen/window/view */
1392 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1393
1394 /* color buffer */
1395 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1396
1397 nPitchInPixel = rrb->pitch/rrb->cpp;
1398 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1399 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1400 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1401 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1402 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1403 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1404 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1405 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1406 if(4 == rrb->cpp)
1407 {
1408 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1409 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1410 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1411 }
1412 else
1413 {
1414 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1415 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1416 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1417 COMP_SWAP_shift, COMP_SWAP_mask);
1418 }
1419 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1420 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1421 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1422
1423 r700->render_target[id].enabled = GL_TRUE;
1424 }
1425
1426 static void r700SetDepthTarget(context_t *context)
1427 {
1428 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1429
1430 struct radeon_renderbuffer *rrb;
1431 unsigned int nPitchInPixel;
1432
1433 rrb = radeon_get_depthbuffer(&context->radeon);
1434 if (!rrb)
1435 return;
1436
1437 R600_STATECHANGE(context, db_target);
1438
1439 /* depth buf */
1440 r700->DB_DEPTH_SIZE.u32All = 0;
1441 r700->DB_DEPTH_BASE.u32All = 0;
1442 r700->DB_DEPTH_INFO.u32All = 0;
1443 r700->DB_DEPTH_VIEW.u32All = 0;
1444
1445 nPitchInPixel = rrb->pitch/rrb->cpp;
1446
1447 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1448 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1449 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1450 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1451
1452 if(4 == rrb->cpp)
1453 {
1454 switch (GL_CONTEXT(context)->Visual.depthBits)
1455 {
1456 case 16:
1457 case 24:
1458 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1459 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1460 break;
1461 default:
1462 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1463 GL_CONTEXT(context)->Visual.depthBits);
1464 _mesa_exit(-1);
1465 }
1466 }
1467 else
1468 {
1469 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1470 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1471 }
1472 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1473 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1474 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1475 }
1476
1477 static void r700InitSQConfig(GLcontext * ctx)
1478 {
1479 context_t *context = R700_CONTEXT(ctx);
1480 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1481 int ps_prio;
1482 int vs_prio;
1483 int gs_prio;
1484 int es_prio;
1485 int num_ps_gprs;
1486 int num_vs_gprs;
1487 int num_gs_gprs;
1488 int num_es_gprs;
1489 int num_temp_gprs;
1490 int num_ps_threads;
1491 int num_vs_threads;
1492 int num_gs_threads;
1493 int num_es_threads;
1494 int num_ps_stack_entries;
1495 int num_vs_stack_entries;
1496 int num_gs_stack_entries;
1497 int num_es_stack_entries;
1498
1499 R600_STATECHANGE(context, sq);
1500
1501 // SQ
1502 ps_prio = 0;
1503 vs_prio = 1;
1504 gs_prio = 2;
1505 es_prio = 3;
1506 switch (context->radeon.radeonScreen->chip_family) {
1507 case CHIP_FAMILY_R600:
1508 num_ps_gprs = 192;
1509 num_vs_gprs = 56;
1510 num_temp_gprs = 4;
1511 num_gs_gprs = 0;
1512 num_es_gprs = 0;
1513 num_ps_threads = 136;
1514 num_vs_threads = 48;
1515 num_gs_threads = 4;
1516 num_es_threads = 4;
1517 num_ps_stack_entries = 128;
1518 num_vs_stack_entries = 128;
1519 num_gs_stack_entries = 0;
1520 num_es_stack_entries = 0;
1521 break;
1522 case CHIP_FAMILY_RV630:
1523 case CHIP_FAMILY_RV635:
1524 num_ps_gprs = 84;
1525 num_vs_gprs = 36;
1526 num_temp_gprs = 4;
1527 num_gs_gprs = 0;
1528 num_es_gprs = 0;
1529 num_ps_threads = 144;
1530 num_vs_threads = 40;
1531 num_gs_threads = 4;
1532 num_es_threads = 4;
1533 num_ps_stack_entries = 40;
1534 num_vs_stack_entries = 40;
1535 num_gs_stack_entries = 32;
1536 num_es_stack_entries = 16;
1537 break;
1538 case CHIP_FAMILY_RV610:
1539 case CHIP_FAMILY_RV620:
1540 case CHIP_FAMILY_RS780:
1541 case CHIP_FAMILY_RS880:
1542 default:
1543 num_ps_gprs = 84;
1544 num_vs_gprs = 36;
1545 num_temp_gprs = 4;
1546 num_gs_gprs = 0;
1547 num_es_gprs = 0;
1548 num_ps_threads = 136;
1549 num_vs_threads = 48;
1550 num_gs_threads = 4;
1551 num_es_threads = 4;
1552 num_ps_stack_entries = 40;
1553 num_vs_stack_entries = 40;
1554 num_gs_stack_entries = 32;
1555 num_es_stack_entries = 16;
1556 break;
1557 case CHIP_FAMILY_RV670:
1558 num_ps_gprs = 144;
1559 num_vs_gprs = 40;
1560 num_temp_gprs = 4;
1561 num_gs_gprs = 0;
1562 num_es_gprs = 0;
1563 num_ps_threads = 136;
1564 num_vs_threads = 48;
1565 num_gs_threads = 4;
1566 num_es_threads = 4;
1567 num_ps_stack_entries = 40;
1568 num_vs_stack_entries = 40;
1569 num_gs_stack_entries = 32;
1570 num_es_stack_entries = 16;
1571 break;
1572 case CHIP_FAMILY_RV770:
1573 num_ps_gprs = 192;
1574 num_vs_gprs = 56;
1575 num_temp_gprs = 4;
1576 num_gs_gprs = 0;
1577 num_es_gprs = 0;
1578 num_ps_threads = 188;
1579 num_vs_threads = 60;
1580 num_gs_threads = 0;
1581 num_es_threads = 0;
1582 num_ps_stack_entries = 256;
1583 num_vs_stack_entries = 256;
1584 num_gs_stack_entries = 0;
1585 num_es_stack_entries = 0;
1586 break;
1587 case CHIP_FAMILY_RV730:
1588 case CHIP_FAMILY_RV740:
1589 num_ps_gprs = 84;
1590 num_vs_gprs = 36;
1591 num_temp_gprs = 4;
1592 num_gs_gprs = 0;
1593 num_es_gprs = 0;
1594 num_ps_threads = 188;
1595 num_vs_threads = 60;
1596 num_gs_threads = 0;
1597 num_es_threads = 0;
1598 num_ps_stack_entries = 128;
1599 num_vs_stack_entries = 128;
1600 num_gs_stack_entries = 0;
1601 num_es_stack_entries = 0;
1602 break;
1603 case CHIP_FAMILY_RV710:
1604 num_ps_gprs = 192;
1605 num_vs_gprs = 56;
1606 num_temp_gprs = 4;
1607 num_gs_gprs = 0;
1608 num_es_gprs = 0;
1609 num_ps_threads = 144;
1610 num_vs_threads = 48;
1611 num_gs_threads = 0;
1612 num_es_threads = 0;
1613 num_ps_stack_entries = 128;
1614 num_vs_stack_entries = 128;
1615 num_gs_stack_entries = 0;
1616 num_es_stack_entries = 0;
1617 break;
1618 }
1619
1620 r700->sq_config.SQ_CONFIG.u32All = 0;
1621 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1622 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1623 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1624 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1625 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1626 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1627 else
1628 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1629 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1630 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1631 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1632 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1633 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1634 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1635
1636 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1637 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1638 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1639 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1640 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1641
1642 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1643 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1644 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1645
1646 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1647 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1648 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1649 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1650 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1651 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1652 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1653 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1654 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1655
1656 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1657 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1658 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1659 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1660 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1661
1662 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1663 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1664 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1665 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1666 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1667
1668 }
1669
1670 /**
1671 * Calculate initial hardware state and register state functions.
1672 * Assumes that the command buffer and state atoms have been
1673 * initialized already.
1674 */
1675 void r700InitState(GLcontext * ctx) //-------------------
1676 {
1677 context_t *context = R700_CONTEXT(ctx);
1678 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1679
1680 radeon_firevertices(&context->radeon);
1681
1682 r700->TA_CNTL_AUX.u32All = 0;
1683 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1684 r700->VC_ENHANCE.u32All = 0;
1685 r700->DB_WATERMARKS.u32All = 0;
1686 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1687 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1688 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1689 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1690 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1691 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1692 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1693 r700->DB_DEBUG.u32All = 0x82000000;
1694 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1695 } else {
1696 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1697 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1698 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1699 }
1700
1701 /* Turn off vgt reuse */
1702 r700->VGT_REUSE_OFF.u32All = 0;
1703 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1704
1705 /* Specify offsetting and clamp values for vertices */
1706 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1707 r700->VGT_MIN_VTX_INDX.u32All = 0;
1708 r700->VGT_INDX_OFFSET.u32All = 0;
1709
1710 /* default shader connections. */
1711 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1712 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1713 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1714 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1715
1716 r700->SPI_THREAD_GROUPING.u32All = 0;
1717 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1718 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1719
1720 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1721 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1722 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1723
1724 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1725 r700->PA_SC_EDGERULE.u32All = 0;
1726 else
1727 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1728
1729 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1730 r700->PA_SC_MODE_CNTL.u32All = 0;
1731 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1732 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1733 } else {
1734 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1735 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1736 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1737 }
1738
1739 /* Do scale XY and Z by 1/W0. */
1740 r700->bEnablePerspective = GL_TRUE;
1741 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1742 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1743 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1744
1745 /* Enable viewport scaling for all three axis */
1746 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1747 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1748 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1749 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1750 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1751 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1752
1753 /* GL uses last vtx for flat shading components */
1754 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1755
1756 /* Set up vertex control */
1757 r700->PA_SU_VTX_CNTL.u32All = 0;
1758 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1759 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1760 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1761 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1762
1763 /* to 1.0 = no guard band */
1764 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1765 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1766 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1767 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1768
1769 /* Enable all samples for multi-sample anti-aliasing */
1770 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1771 /* Turn off AA */
1772 r700->PA_SC_AA_CONFIG.u32All = 0;
1773
1774 r700->SX_MISC.u32All = 0;
1775
1776 r700InitSQConfig(ctx);
1777
1778 r700ColorMask(ctx,
1779 ctx->Color.ColorMask[RCOMP],
1780 ctx->Color.ColorMask[GCOMP],
1781 ctx->Color.ColorMask[BCOMP],
1782 ctx->Color.ColorMask[ACOMP]);
1783
1784 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1785 r700DepthMask(ctx, ctx->Depth.Mask);
1786 r700DepthFunc(ctx, ctx->Depth.Func);
1787 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1788
1789 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1790
1791 r700->DB_RENDER_CONTROL.u32All = 0;
1792 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1793 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1794 r700->DB_RENDER_OVERRIDE.u32All = 0;
1795 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1796 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1797 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1798 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1799 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1800
1801 r700->DB_ALPHA_TO_MASK.u32All = 0;
1802 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1803 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1804 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1805 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1806
1807 /* stencil */
1808 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1809 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1810 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1811 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1812 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1813 ctx->Stencil.ZFailFunc[0],
1814 ctx->Stencil.ZPassFunc[0]);
1815
1816 r700UpdateCulling(ctx);
1817
1818 r700SetBlendState(ctx);
1819 r700SetLogicOpState(ctx);
1820
1821 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1822 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1823
1824 r700PointSize(ctx, 1.0);
1825
1826 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1827 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1828
1829 r700LineWidth(ctx, 1.0);
1830
1831 r700->PA_SC_LINE_CNTL.u32All = 0;
1832 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1833 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1834
1835 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1836 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1837 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1838 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1839 ctx->Polygon.OffsetUnits);
1840 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1841 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1842 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1843
1844 /* CB */
1845 r700BlendColor(ctx, ctx->Color.BlendColor);
1846
1847 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1848 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1849 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1850 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1851 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1852 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1853 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1854
1855 /* Disable color compares */
1856 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1857 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1858 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1859 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1860 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1861 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1862
1863 /* Zero out source */
1864 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1865
1866 /* Put a compare color in for error checking */
1867 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1868
1869 /* Set up color compare mask */
1870 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1871
1872 context->radeon.hw.all_dirty = GL_TRUE;
1873
1874 }
1875
1876 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1877 {
1878 functions->UpdateState = r700InvalidateState;
1879 functions->AlphaFunc = r700AlphaFunc;
1880 functions->BlendColor = r700BlendColor;
1881 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1882 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1883 functions->Enable = r700Enable;
1884 functions->ColorMask = r700ColorMask;
1885 functions->DepthFunc = r700DepthFunc;
1886 functions->DepthMask = r700DepthMask;
1887 functions->CullFace = r700CullFace;
1888 functions->Fogfv = r700Fogfv;
1889 functions->FrontFace = r700FrontFace;
1890 functions->ShadeModel = r700ShadeModel;
1891 functions->LogicOpcode = r700LogicOpcode;
1892
1893 /* ARB_point_parameters */
1894 functions->PointParameterfv = r700PointParameter;
1895
1896 /* Stencil related */
1897 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1898 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1899 functions->StencilOpSeparate = r700StencilOpSeparate;
1900
1901 /* Viewport related */
1902 functions->Viewport = r700Viewport;
1903 functions->DepthRange = r700DepthRange;
1904 functions->PointSize = r700PointSize;
1905 functions->LineWidth = r700LineWidth;
1906 functions->LineStipple = r700LineStipple;
1907
1908 functions->PolygonOffset = r700PolygonOffset;
1909 functions->PolygonMode = r700PolygonMode;
1910
1911 functions->RenderMode = r700RenderMode;
1912
1913 functions->ClipPlane = r700ClipPlane;
1914
1915 functions->Scissor = radeonScissor;
1916
1917 functions->DrawBuffer = radeonDrawBuffer;
1918 functions->ReadBuffer = radeonReadBuffer;
1919
1920 }
1921