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r600: add alpha test support
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60
61 void r700SetDefaultStates(context_t *context) //--------------------
62 {
63
64 }
65
66 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
67 {
68 context_t *context = R700_CONTEXT(ctx);
69
70 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
71 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
72
73 struct r700_vertex_program *vp;
74 int i;
75
76 if (context->radeon.NewGLState)
77 {
78 context->radeon.NewGLState = 0;
79
80 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
81 {
82 /* mat states from state var not array for sw */
83 dummy_attrib[i].stride = 0;
84
85 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
86 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
87 }
88
89 _tnl_UpdateFixedFunctionProgram(ctx);
90
91 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
92 {
93 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
94 }
95
96 r700SelectVertexShader(ctx);
97 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
98
99 if (vp->translated == GL_FALSE)
100 {
101 // TODO
102 //fprintf(stderr, "Failing back to sw-tcl\n");
103 //hw_tcl_on = future_hw_tcl_on = 0;
104 //r300ResetHwState(rmesa);
105 //
106 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
107 return;
108 }
109 }
110
111 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
112 }
113
114 /*
115 * To correctly position primitives:
116 */
117 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
118 {
119
120 //radeonUpdateScissor(ctx);
121
122 return;
123 }
124
125 /**
126 * Tell the card where to render (offset, pitch).
127 * Effected by glDrawBuffer, etc
128 */
129 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
130 {
131 #if 0 /* to be enabled */
132 context_t *context = R700_CONTEXT(ctx);
133
134 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
135 {
136 case BUFFER_FRONT_LEFT:
137 context->target.rt = context->screen->frontBuffer;
138 break;
139 case BUFFER_BACK_LEFT:
140 context->target.rt = context->screen->backBuffer;
141 break;
142 default:
143 memset (&context->target.rt, sizeof(context->target.rt), 0);
144 }
145 #endif /* to be enabled */
146 }
147
148 static void r700FetchStateParameter(GLcontext * ctx,
149 const gl_state_index state[STATE_LENGTH],
150 GLfloat * value)
151 {
152 context_t *context = R700_CONTEXT(ctx);
153
154 /* TODO */
155 }
156
157 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
158 {
159 struct r700_fragment_program *fp;
160 struct gl_program_parameter_list *paramList;
161 GLuint i;
162
163 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
164 return;
165
166 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
167 if (!fp)
168 {
169 return;
170 }
171
172 paramList = fp->mesa_program.Base.Parameters;
173
174 if (!paramList)
175 {
176 return;
177 }
178
179 for (i = 0; i < paramList->NumParameters; i++)
180 {
181 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
182 {
183 r700FetchStateParameter(ctx,
184 paramList->Parameters[i].
185 StateIndexes,
186 paramList->ParameterValues[i]);
187 }
188 }
189 }
190
191 /**
192 * Called by Mesa after an internal state update.
193 */
194 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
195 {
196 context_t *context = R700_CONTEXT(ctx);
197
198 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
199
200 _swrast_InvalidateState(ctx, new_state);
201 _swsetup_InvalidateState(ctx, new_state);
202 _vbo_InvalidateState(ctx, new_state);
203 _tnl_InvalidateState(ctx, new_state);
204 _ae_invalidate_state(ctx, new_state);
205
206 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
207 {
208 _mesa_update_framebuffer(ctx);
209 /* this updates the DrawBuffer's Width/Height if it's a FBO */
210 _mesa_update_draw_buffer_bounds(ctx);
211
212 r700UpdateDrawBuffer(ctx);
213 }
214
215 r700UpdateStateParameters(ctx, new_state);
216
217 if(GL_TRUE == r700->bEnablePerspective)
218 {
219 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
220 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
221 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
222
223 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
224
225 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
226 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
227 }
228 else
229 {
230 /* For orthogonal case. */
231 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
232 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
233
234 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
235
236 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
237 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
238 }
239
240 context->radeon.NewGLState |= new_state;
241 }
242
243 static void r700SetDepthState(GLcontext * ctx)
244 {
245 context_t *context = R700_CONTEXT(ctx);
246
247 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
248
249 if (ctx->Depth.Test)
250 {
251 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
252 if (ctx->Depth.Mask)
253 {
254 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
255 }
256 else
257 {
258 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
259 }
260
261 switch (ctx->Depth.Func)
262 {
263 case GL_NEVER:
264 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
265 ZFUNC_shift, ZFUNC_mask);
266 break;
267 case GL_LESS:
268 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
269 ZFUNC_shift, ZFUNC_mask);
270 break;
271 case GL_EQUAL:
272 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
273 ZFUNC_shift, ZFUNC_mask);
274 break;
275 case GL_LEQUAL:
276 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
277 ZFUNC_shift, ZFUNC_mask);
278 break;
279 case GL_GREATER:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 case GL_NOTEQUAL:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 case GL_GEQUAL:
288 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
289 ZFUNC_shift, ZFUNC_mask);
290 break;
291 case GL_ALWAYS:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 default:
296 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
297 ZFUNC_shift, ZFUNC_mask);
298 break;
299 }
300 }
301 else
302 {
303 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
304 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
305 }
306 }
307
308 static void r700SetAlphaState(GLcontext * ctx)
309 {
310 context_t *context = R700_CONTEXT(ctx);
311 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
312 uint32_t alpha_func;
313 GLboolean really_enabled = ctx->Color.AlphaEnabled;
314
315 switch (ctx->Color.AlphaFunc) {
316 case GL_NEVER:
317 alpha_func = REF_NEVER;
318 break;
319 case GL_LESS:
320 alpha_func = REF_LESS;
321 break;
322 case GL_EQUAL:
323 alpha_func = REF_EQUAL;
324 break;
325 case GL_LEQUAL:
326 alpha_func = REF_LEQUAL;
327 break;
328 case GL_GREATER:
329 alpha_func = REF_GREATER;
330 break;
331 case GL_NOTEQUAL:
332 alpha_func = REF_NOTEQUAL;
333 break;
334 case GL_GEQUAL:
335 alpha_func = REF_GEQUAL;
336 break;
337 case GL_ALWAYS:
338 /*alpha_func = REF_ALWAYS; */
339 really_enabled = GL_FALSE;
340 break;
341 }
342
343 if (really_enabled) {
344 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
345 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
346 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
347 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
348 } else {
349 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
350 }
351
352 }
353
354 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
355 {
356 (void)func;
357 (void)ref;
358 r700SetAlphaState(ctx);
359 }
360
361
362 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
363 {
364 context_t *context = R700_CONTEXT(ctx);
365 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
366
367 r700->CB_BLEND_RED.f32All = cf[0];
368 r700->CB_BLEND_GREEN.f32All = cf[1];
369 r700->CB_BLEND_BLUE.f32All = cf[2];
370 r700->CB_BLEND_ALPHA.f32All = cf[3];
371 }
372
373 static int blend_factor(GLenum factor, GLboolean is_src)
374 {
375 switch (factor) {
376 case GL_ZERO:
377 return BLEND_ZERO;
378 break;
379 case GL_ONE:
380 return BLEND_ONE;
381 break;
382 case GL_DST_COLOR:
383 return BLEND_DST_COLOR;
384 break;
385 case GL_ONE_MINUS_DST_COLOR:
386 return BLEND_ONE_MINUS_DST_COLOR;
387 break;
388 case GL_SRC_COLOR:
389 return BLEND_SRC_COLOR;
390 break;
391 case GL_ONE_MINUS_SRC_COLOR:
392 return BLEND_ONE_MINUS_SRC_COLOR;
393 break;
394 case GL_SRC_ALPHA:
395 return BLEND_SRC_ALPHA;
396 break;
397 case GL_ONE_MINUS_SRC_ALPHA:
398 return BLEND_ONE_MINUS_SRC_ALPHA;
399 break;
400 case GL_DST_ALPHA:
401 return BLEND_DST_ALPHA;
402 break;
403 case GL_ONE_MINUS_DST_ALPHA:
404 return BLEND_ONE_MINUS_DST_ALPHA;
405 break;
406 case GL_SRC_ALPHA_SATURATE:
407 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
408 break;
409 case GL_CONSTANT_COLOR:
410 return BLEND_CONSTANT_COLOR;
411 break;
412 case GL_ONE_MINUS_CONSTANT_COLOR:
413 return BLEND_ONE_MINUS_CONSTANT_COLOR;
414 break;
415 case GL_CONSTANT_ALPHA:
416 return BLEND_CONSTANT_ALPHA;
417 break;
418 case GL_ONE_MINUS_CONSTANT_ALPHA:
419 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
420 break;
421 default:
422 fprintf(stderr, "unknown blend factor %x\n", factor);
423 return (is_src) ? BLEND_ONE : BLEND_ZERO;
424 break;
425 }
426 }
427
428 static void r700SetBlendState(GLcontext * ctx)
429 {
430 context_t *context = R700_CONTEXT(ctx);
431 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
432 int id = 0;
433 uint32_t blend_reg = 0, eqn, eqnA;
434
435 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
436 SETfield(blend_reg,
437 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
438 SETfield(blend_reg,
439 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
440 SETfield(blend_reg,
441 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
442 SETfield(blend_reg,
443 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
444 SETfield(blend_reg,
445 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
446 SETfield(blend_reg,
447 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
448 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
449 r700->CB_BLEND_CONTROL.u32All = blend_reg;
450 else
451 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
452 return;
453 }
454
455 SETfield(blend_reg,
456 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
457 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
458 SETfield(blend_reg,
459 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
460 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
461
462 switch (ctx->Color.BlendEquationRGB) {
463 case GL_FUNC_ADD:
464 eqn = COMB_DST_PLUS_SRC;
465 break;
466 case GL_FUNC_SUBTRACT:
467 eqn = COMB_SRC_MINUS_DST;
468 break;
469 case GL_FUNC_REVERSE_SUBTRACT:
470 eqn = COMB_DST_MINUS_SRC;
471 break;
472 case GL_MIN:
473 eqn = COMB_MIN_DST_SRC;
474 SETfield(blend_reg,
475 BLEND_ONE,
476 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
477 SETfield(blend_reg,
478 BLEND_ONE,
479 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
480 break;
481 case GL_MAX:
482 eqn = COMB_MAX_DST_SRC;
483 SETfield(blend_reg,
484 BLEND_ONE,
485 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
486 SETfield(blend_reg,
487 BLEND_ONE,
488 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
489 break;
490
491 default:
492 fprintf(stderr,
493 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
494 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
495 return;
496 }
497 SETfield(blend_reg,
498 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
499
500 SETfield(blend_reg,
501 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
502 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
503 SETfield(blend_reg,
504 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
505 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
506
507 switch (ctx->Color.BlendEquationA) {
508 case GL_FUNC_ADD:
509 eqnA = COMB_DST_PLUS_SRC;
510 break;
511 case GL_FUNC_SUBTRACT:
512 eqnA = COMB_SRC_MINUS_DST;
513 break;
514 case GL_FUNC_REVERSE_SUBTRACT:
515 eqnA = COMB_DST_MINUS_SRC;
516 break;
517 case GL_MIN:
518 eqnA = COMB_MIN_DST_SRC;
519 SETfield(blend_reg,
520 BLEND_ONE,
521 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
522 SETfield(blend_reg,
523 BLEND_ONE,
524 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
525 break;
526 case GL_MAX:
527 eqnA = COMB_MAX_DST_SRC;
528 SETfield(blend_reg,
529 BLEND_ONE,
530 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
531 SETfield(blend_reg,
532 BLEND_ONE,
533 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
534 break;
535 default:
536 fprintf(stderr,
537 "[%s:%u] Invalid A blend equation (0x%04x).\n",
538 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
539 return;
540 }
541
542 SETfield(blend_reg,
543 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
544
545 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
546
547 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
548 r700->CB_BLEND_CONTROL.u32All = blend_reg;
549 else {
550 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
551 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
552 }
553 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
554 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
555
556 }
557
558 static void r700BlendEquationSeparate(GLcontext * ctx,
559 GLenum modeRGB, GLenum modeA) //-----------------
560 {
561 r700SetBlendState(ctx);
562 }
563
564 static void r700BlendFuncSeparate(GLcontext * ctx,
565 GLenum sfactorRGB, GLenum dfactorRGB,
566 GLenum sfactorA, GLenum dfactorA) //------------------------
567 {
568 r700SetBlendState(ctx);
569 }
570
571 /**
572 * Translate LogicOp enums into hardware representation.
573 * Both use a very logical bit-wise layout, but unfortunately the order
574 * of bits is reversed.
575 */
576 static GLuint translate_logicop(GLenum logicop)
577 {
578 GLuint bits = logicop - GL_CLEAR;
579 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
580 return bits;
581 }
582
583 /**
584 * Used internally to update the r300->hw hardware state to match the
585 * current OpenGL state.
586 */
587 static void r700SetLogicOpState(GLcontext *ctx)
588 {
589 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
590
591 if (RGBA_LOGICOP_ENABLED(ctx))
592 SETfield(r700->CB_COLOR_CONTROL.u32All,
593 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
594 else
595 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
596 }
597
598 /**
599 * Called by Mesa when an application program changes the LogicOp state
600 * via glLogicOp.
601 */
602 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
603 {
604 if (RGBA_LOGICOP_ENABLED(ctx))
605 r700SetLogicOpState(ctx);
606 }
607
608 static void r700UpdateCulling(GLcontext * ctx)
609 {
610 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
611
612 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
613 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
614 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
615
616 if (ctx->Polygon.CullFlag)
617 {
618 switch (ctx->Polygon.CullFaceMode)
619 {
620 case GL_FRONT:
621 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
622 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
623 break;
624 case GL_BACK:
625 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
626 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
627 break;
628 case GL_FRONT_AND_BACK:
629 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
630 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
631 break;
632 default:
633 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
634 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
635 break;
636 }
637 }
638
639 switch (ctx->Polygon.FrontFace)
640 {
641 case GL_CW:
642 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
643 break;
644 case GL_CCW:
645 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
646 break;
647 default:
648 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
649 break;
650 }
651 }
652
653 static void r700UpdateLineStipple(GLcontext * ctx)
654 {
655 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
656 if (ctx->Line.StippleFlag)
657 {
658 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
659 }
660 else
661 {
662 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
663 }
664 }
665
666 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
667 {
668 context_t *context = R700_CONTEXT(ctx);
669
670 switch (cap) {
671 case GL_TEXTURE_1D:
672 case GL_TEXTURE_2D:
673 case GL_TEXTURE_3D:
674 /* empty */
675 break;
676 case GL_FOG:
677 /* empty */
678 break;
679 case GL_ALPHA_TEST:
680 r700SetAlphaState(ctx);
681 break;
682 case GL_COLOR_LOGIC_OP:
683 r700SetLogicOpState(ctx);
684 /* fall-through, because logic op overrides blending */
685 case GL_BLEND:
686 r700SetBlendState(ctx);
687 break;
688 case GL_CLIP_PLANE0:
689 case GL_CLIP_PLANE1:
690 case GL_CLIP_PLANE2:
691 case GL_CLIP_PLANE3:
692 case GL_CLIP_PLANE4:
693 case GL_CLIP_PLANE5:
694 r700SetClipPlaneState(ctx, cap, state);
695 break;
696 case GL_DEPTH_TEST:
697 r700SetDepthState(ctx);
698 break;
699 case GL_STENCIL_TEST:
700 //r700SetStencilState(ctx, state);
701 break;
702 case GL_CULL_FACE:
703 r700UpdateCulling(ctx);
704 break;
705 case GL_POLYGON_OFFSET_POINT:
706 case GL_POLYGON_OFFSET_LINE:
707 case GL_POLYGON_OFFSET_FILL:
708 //r700SetPolygonOffsetState(ctx, state);
709 break;
710 case GL_SCISSOR_TEST:
711 radeon_firevertices(&context->radeon);
712 context->radeon.state.scissor.enabled = state;
713 radeonUpdateScissor(ctx);
714 break;
715 case GL_LINE_STIPPLE:
716 r700UpdateLineStipple(ctx);
717 break;
718 default:
719 break;
720 }
721
722 }
723
724 /**
725 * Handle glColorMask()
726 */
727 static void r700ColorMask(GLcontext * ctx,
728 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
729 {
730 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
731 unsigned int mask = ((r ? 1 : 0) |
732 (g ? 2 : 0) |
733 (b ? 4 : 0) |
734 (a ? 8 : 0));
735
736 if (mask != r700->CB_SHADER_MASK.u32All)
737 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
738 }
739
740 /**
741 * Change the depth testing function.
742 *
743 * \note Mesa already filters redundant calls to this function.
744 */
745 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
746 {
747 r700SetDepthState(ctx);
748 }
749
750 /**
751 * Enable/Disable depth writing.
752 *
753 * \note Mesa already filters redundant calls to this function.
754 */
755 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
756 {
757 r700SetDepthState(ctx);
758 }
759
760 /**
761 * Change the culling mode.
762 *
763 * \note Mesa already filters redundant calls to this function.
764 */
765 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
766 {
767 r700UpdateCulling(ctx);
768 }
769
770 /* =============================================================
771 * Fog
772 */
773 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
774 {
775 }
776
777 /**
778 * Change the polygon orientation.
779 *
780 * \note Mesa already filters redundant calls to this function.
781 */
782 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
783 {
784 r700UpdateCulling(ctx);
785 }
786
787 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
788 {
789 context_t *context = R700_CONTEXT(ctx);
790 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
791
792 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
793 switch (mode) {
794 case GL_FLAT:
795 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
796 break;
797 case GL_SMOOTH:
798 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
799 break;
800 default:
801 return;
802 }
803 }
804
805 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
806 {
807 }
808
809 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
810 GLenum func, GLint ref, GLuint mask) //---------------------
811 {
812 }
813
814
815 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
816 {
817 }
818
819 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
820 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
821 {
822 }
823
824 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
825 {
826
827 context_t *context = R700_CONTEXT(ctx);
828 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
829 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
830 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
831 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
832 const GLfloat *v = ctx->Viewport._WindowMap.m;
833 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
834 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
835 GLfloat y_scale, y_bias;
836
837 if (render_to_fbo) {
838 y_scale = 1.0;
839 y_bias = 0;
840 } else {
841 y_scale = -1.0;
842 y_bias = yoffset;
843 }
844
845 GLfloat sx = v[MAT_SX];
846 GLfloat tx = v[MAT_TX] + xoffset;
847 GLfloat sy = v[MAT_SY] * y_scale;
848 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
849 GLfloat sz = v[MAT_SZ] * depthScale;
850 GLfloat tz = v[MAT_TZ] * depthScale;
851
852 /* TODO : Need DMA flush as well. */
853
854 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
855 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
856
857 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
858 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
859
860 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
861 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
862
863 r700->viewport[id].enabled = GL_TRUE;
864
865 r700SetScissor(context);
866 }
867
868
869 static void r700Viewport(GLcontext * ctx,
870 GLint x,
871 GLint y,
872 GLsizei width,
873 GLsizei height) //--------------------
874 {
875 r700UpdateWindow(ctx, 0);
876
877 radeon_viewport(ctx, x, y, width, height);
878 }
879
880 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
881 {
882 r700UpdateWindow(ctx, 0);
883 }
884
885 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
886 {
887 }
888
889 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
890 {
891 context_t *context = R700_CONTEXT(ctx);
892 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
893 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
894 if (lineWidth > 0xFFFF)
895 lineWidth = 0xFFFF;
896 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
897 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
898 }
899
900 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
901 {
902 context_t *context = R700_CONTEXT(ctx);
903 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
904
905 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
906 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
907 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
908 }
909
910 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
911 {
912 }
913
914
915 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
916 {
917 }
918
919 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
920 {
921 }
922
923 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
924 {
925 context_t *context = R700_CONTEXT(ctx);
926 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
927 GLint p;
928 GLint *ip;
929
930 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
931 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
932
933 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
934 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
935 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
936 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
937 }
938
939 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
940 {
941 context_t *context = R700_CONTEXT(ctx);
942 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
943 GLuint p;
944
945 p = cap - GL_CLIP_PLANE0;
946 if (state) {
947 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
948 r700->ucp[p].enabled = GL_TRUE;
949 r700ClipPlane(ctx, cap, NULL);
950 } else {
951 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
952 r700->ucp[p].enabled = GL_FALSE;
953 }
954 }
955
956 void r700SetScissor(context_t *context) //---------------
957 {
958 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
959 unsigned x1, y1, x2, y2;
960 int id = 0;
961 struct radeon_renderbuffer *rrb;
962
963 rrb = radeon_get_colorbuffer(&context->radeon);
964 if (!rrb || !rrb->bo) {
965 return;
966 }
967 if (context->radeon.state.scissor.enabled) {
968 x1 = context->radeon.state.scissor.rect.x1;
969 y1 = context->radeon.state.scissor.rect.y1;
970 x2 = context->radeon.state.scissor.rect.x2 - 1;
971 y2 = context->radeon.state.scissor.rect.y2 - 1;
972 } else {
973 x1 = rrb->dPriv->x;
974 y1 = rrb->dPriv->y;
975 x2 = rrb->dPriv->x + rrb->dPriv->w;
976 y2 = rrb->dPriv->y + rrb->dPriv->h;
977 }
978
979 /* window */
980 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
981 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
982 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
983 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
984 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
985
986 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
987 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
988 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
989 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
990
991
992 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
993 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
994 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
995 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
996 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
997 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
998 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
999 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1000
1001 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1002 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1003 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1004 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1005 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1006 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1007
1008 /* more....2d clip */
1009 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1010 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1011 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1012 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1013 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1014 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1015 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1016 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1017 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1018
1019 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1020 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1021 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1022 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1023 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1024 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1025 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1026 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1027 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1028
1029 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1030 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1031 r700->viewport[id].enabled = GL_TRUE;
1032 }
1033
1034 void r700SetRenderTarget(context_t *context, int id)
1035 {
1036 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1037
1038 struct radeon_renderbuffer *rrb;
1039 unsigned int nPitchInPixel;
1040
1041 /* screen/window/view */
1042 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1043
1044 rrb = radeon_get_colorbuffer(&context->radeon);
1045 if (!rrb || !rrb->bo) {
1046 fprintf(stderr, "no rrb\n");
1047 return;
1048 }
1049
1050 /* color buffer */
1051 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1052
1053 nPitchInPixel = rrb->pitch/rrb->cpp;
1054 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1055 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1056 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1057 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1058 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1059 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1060 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1061 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1062 if(4 == rrb->cpp)
1063 {
1064 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1065 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1066 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1067 }
1068 else
1069 {
1070 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1071 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1072 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1073 COMP_SWAP_shift, COMP_SWAP_mask);
1074 }
1075 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1076 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1077 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1078
1079 r700->render_target[id].enabled = GL_TRUE;
1080 }
1081
1082 void r700SetDepthTarget(context_t *context)
1083 {
1084 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1085
1086 struct radeon_renderbuffer *rrb;
1087 unsigned int nPitchInPixel;
1088
1089 /* depth buf */
1090 r700->DB_DEPTH_SIZE.u32All = 0;
1091 r700->DB_DEPTH_BASE.u32All = 0;
1092 r700->DB_DEPTH_INFO.u32All = 0;
1093
1094 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1095 r700->DB_DEPTH_VIEW.u32All = 0;
1096 r700->DB_RENDER_CONTROL.u32All = 0;
1097 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1098 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1099 r700->DB_RENDER_OVERRIDE.u32All = 0;
1100 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1101 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1102 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1103 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1104 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1105
1106 r700->DB_ALPHA_TO_MASK.u32All = 0;
1107 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1108 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1109 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1110 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1111
1112 rrb = radeon_get_depthbuffer(&context->radeon);
1113 if (!rrb)
1114 return;
1115
1116 nPitchInPixel = rrb->pitch/rrb->cpp;
1117
1118 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1119 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1120 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1121 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1122
1123 if(4 == rrb->cpp)
1124 {
1125 switch (GL_CONTEXT(context)->Visual.depthBits)
1126 {
1127 case 16:
1128 case 24:
1129 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1130 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1131 break;
1132 default:
1133 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1134 GL_CONTEXT(context)->Visual.depthBits);
1135 _mesa_exit(-1);
1136 }
1137 }
1138 else
1139 {
1140 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1141 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1142 }
1143 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1144 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1145 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1146 }
1147
1148 static void r700InitSQConfig(GLcontext * ctx)
1149 {
1150 context_t *context = R700_CONTEXT(ctx);
1151 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1152 int ps_prio;
1153 int vs_prio;
1154 int gs_prio;
1155 int es_prio;
1156 int num_ps_gprs;
1157 int num_vs_gprs;
1158 int num_gs_gprs;
1159 int num_es_gprs;
1160 int num_temp_gprs;
1161 int num_ps_threads;
1162 int num_vs_threads;
1163 int num_gs_threads;
1164 int num_es_threads;
1165 int num_ps_stack_entries;
1166 int num_vs_stack_entries;
1167 int num_gs_stack_entries;
1168 int num_es_stack_entries;
1169
1170 // SQ
1171 ps_prio = 0;
1172 vs_prio = 1;
1173 gs_prio = 2;
1174 es_prio = 3;
1175 switch (context->radeon.radeonScreen->chip_family) {
1176 case CHIP_FAMILY_R600:
1177 num_ps_gprs = 192;
1178 num_vs_gprs = 56;
1179 num_temp_gprs = 4;
1180 num_gs_gprs = 0;
1181 num_es_gprs = 0;
1182 num_ps_threads = 136;
1183 num_vs_threads = 48;
1184 num_gs_threads = 4;
1185 num_es_threads = 4;
1186 num_ps_stack_entries = 128;
1187 num_vs_stack_entries = 128;
1188 num_gs_stack_entries = 0;
1189 num_es_stack_entries = 0;
1190 break;
1191 case CHIP_FAMILY_RV630:
1192 case CHIP_FAMILY_RV635:
1193 num_ps_gprs = 84;
1194 num_vs_gprs = 36;
1195 num_temp_gprs = 4;
1196 num_gs_gprs = 0;
1197 num_es_gprs = 0;
1198 num_ps_threads = 144;
1199 num_vs_threads = 40;
1200 num_gs_threads = 4;
1201 num_es_threads = 4;
1202 num_ps_stack_entries = 40;
1203 num_vs_stack_entries = 40;
1204 num_gs_stack_entries = 32;
1205 num_es_stack_entries = 16;
1206 break;
1207 case CHIP_FAMILY_RV610:
1208 case CHIP_FAMILY_RV620:
1209 case CHIP_FAMILY_RS780:
1210 default:
1211 num_ps_gprs = 84;
1212 num_vs_gprs = 36;
1213 num_temp_gprs = 4;
1214 num_gs_gprs = 0;
1215 num_es_gprs = 0;
1216 num_ps_threads = 136;
1217 num_vs_threads = 48;
1218 num_gs_threads = 4;
1219 num_es_threads = 4;
1220 num_ps_stack_entries = 40;
1221 num_vs_stack_entries = 40;
1222 num_gs_stack_entries = 32;
1223 num_es_stack_entries = 16;
1224 break;
1225 case CHIP_FAMILY_RV670:
1226 num_ps_gprs = 144;
1227 num_vs_gprs = 40;
1228 num_temp_gprs = 4;
1229 num_gs_gprs = 0;
1230 num_es_gprs = 0;
1231 num_ps_threads = 136;
1232 num_vs_threads = 48;
1233 num_gs_threads = 4;
1234 num_es_threads = 4;
1235 num_ps_stack_entries = 40;
1236 num_vs_stack_entries = 40;
1237 num_gs_stack_entries = 32;
1238 num_es_stack_entries = 16;
1239 break;
1240 case CHIP_FAMILY_RV770:
1241 num_ps_gprs = 192;
1242 num_vs_gprs = 56;
1243 num_temp_gprs = 4;
1244 num_gs_gprs = 0;
1245 num_es_gprs = 0;
1246 num_ps_threads = 188;
1247 num_vs_threads = 60;
1248 num_gs_threads = 0;
1249 num_es_threads = 0;
1250 num_ps_stack_entries = 256;
1251 num_vs_stack_entries = 256;
1252 num_gs_stack_entries = 0;
1253 num_es_stack_entries = 0;
1254 break;
1255 case CHIP_FAMILY_RV730:
1256 case CHIP_FAMILY_RV740:
1257 num_ps_gprs = 84;
1258 num_vs_gprs = 36;
1259 num_temp_gprs = 4;
1260 num_gs_gprs = 0;
1261 num_es_gprs = 0;
1262 num_ps_threads = 188;
1263 num_vs_threads = 60;
1264 num_gs_threads = 0;
1265 num_es_threads = 0;
1266 num_ps_stack_entries = 128;
1267 num_vs_stack_entries = 128;
1268 num_gs_stack_entries = 0;
1269 num_es_stack_entries = 0;
1270 break;
1271 case CHIP_FAMILY_RV710:
1272 num_ps_gprs = 192;
1273 num_vs_gprs = 56;
1274 num_temp_gprs = 4;
1275 num_gs_gprs = 0;
1276 num_es_gprs = 0;
1277 num_ps_threads = 144;
1278 num_vs_threads = 48;
1279 num_gs_threads = 0;
1280 num_es_threads = 0;
1281 num_ps_stack_entries = 128;
1282 num_vs_stack_entries = 128;
1283 num_gs_stack_entries = 0;
1284 num_es_stack_entries = 0;
1285 break;
1286 }
1287
1288 r700->sq_config.SQ_CONFIG.u32All = 0;
1289 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1290 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1291 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1292 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1293 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1294 else
1295 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1296 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1297 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1298 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1299 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1300 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1301 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1302
1303 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1304 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1305 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1306 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1307 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1308
1309 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1310 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1311 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1312
1313 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1314 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1315 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1316 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1317 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1318 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1319 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1320 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1321 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1322
1323 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1324 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1325 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1326 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1327 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1328
1329 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1330 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1331 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1332 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1333 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1334
1335 }
1336
1337 /**
1338 * Calculate initial hardware state and register state functions.
1339 * Assumes that the command buffer and state atoms have been
1340 * initialized already.
1341 */
1342 void r700InitState(GLcontext * ctx) //-------------------
1343 {
1344 context_t *context = R700_CONTEXT(ctx);
1345
1346 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1347
1348 r700->TA_CNTL_AUX.u32All = 0;
1349 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1350 r700->VC_ENHANCE.u32All = 0;
1351 r700->DB_WATERMARKS.u32All = 0;
1352 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1353 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1354 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1355 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1356 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1357 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1358 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1359 r700->DB_DEBUG.u32All = 0x82000000;
1360 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1361 } else {
1362 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1363 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1364 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1365 }
1366
1367 /* Turn off vgt reuse */
1368 r700->VGT_REUSE_OFF.u32All = 0;
1369 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1370
1371 /* Specify offsetting and clamp values for vertices */
1372 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1373 r700->VGT_MIN_VTX_INDX.u32All = 0;
1374 r700->VGT_INDX_OFFSET.u32All = 0;
1375
1376 /* Specify the number of instances */
1377 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
1378
1379 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1380
1381 /* default shader connections. */
1382 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1383 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1384
1385 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
1386 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
1387 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
1388
1389 r700->SPI_THREAD_GROUPING.u32All = 0;
1390 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1391 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1392
1393 r700SetBlendState(ctx);
1394 r700SetLogicOpState(ctx);
1395
1396 r700->DB_SHADER_CONTROL.u32All = 0;
1397 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1398
1399 /* Set up the culling control register */
1400 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1401 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1402 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1403 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1404
1405 /* screen */
1406 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1407
1408 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1409 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1410 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1411 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1412 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1413 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1414
1415 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1416 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1417 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1418
1419 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1420 r700->PA_SC_EDGERULE.u32All = 0;
1421 else
1422 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1423
1424 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1425 r700->PA_SC_MODE_CNTL.u32All = 0;
1426 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1427 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1428 } else {
1429 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1430 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1431 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1432 }
1433
1434 /* Do scale XY and Z by 1/W0. */
1435 r700->bEnablePerspective = GL_TRUE;
1436 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1437 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1438 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1439
1440 /* Enable viewport scaling for all three axis */
1441 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1442 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1443 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1444 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1445 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1446 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1447
1448 /* Set up point sizes and min/max values */
1449 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1450 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
1451 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1452 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
1453 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1454 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1455
1456 /* Set up line control */
1457 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
1458 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1459
1460 r700->PA_SC_LINE_CNTL.u32All = 0;
1461 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1462 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1463
1464 /* Set up vertex control */
1465 r700->PA_SU_VTX_CNTL.u32All = 0;
1466 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1467 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1468 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1469 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1470
1471 /* to 1.0 = no guard band */
1472 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1473 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1474 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1475 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1476
1477 /* CB */
1478 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1479 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1480 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1481 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1482 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1483 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1484 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1485
1486 /* Disable color compares */
1487 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1488 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1489 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1490 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1491 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1492 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1493
1494 /* Zero out source */
1495 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1496
1497 /* Put a compare color in for error checking */
1498 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1499
1500 /* Set up color compare mask */
1501 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1502
1503 /* default color mask */
1504 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
1505
1506 /* Enable all samples for multi-sample anti-aliasing */
1507 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1508 /* Turn off AA */
1509 r700->PA_SC_AA_CONFIG.u32All = 0;
1510
1511 r700->SX_MISC.u32All = 0;
1512
1513 r700InitSQConfig(ctx);
1514 }
1515
1516 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1517 {
1518 functions->UpdateState = r700InvalidateState;
1519 functions->AlphaFunc = r700AlphaFunc;
1520 functions->BlendColor = r700BlendColor;
1521 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1522 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1523 functions->Enable = r700Enable;
1524 functions->ColorMask = r700ColorMask;
1525 functions->DepthFunc = r700DepthFunc;
1526 functions->DepthMask = r700DepthMask;
1527 functions->CullFace = r700CullFace;
1528 functions->Fogfv = r700Fogfv;
1529 functions->FrontFace = r700FrontFace;
1530 functions->ShadeModel = r700ShadeModel;
1531 functions->LogicOpcode = r700LogicOpcode;
1532
1533 /* ARB_point_parameters */
1534 functions->PointParameterfv = r700PointParameter;
1535
1536 /* Stencil related */
1537 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1538 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1539 functions->StencilOpSeparate = r700StencilOpSeparate;
1540
1541 /* Viewport related */
1542 functions->Viewport = r700Viewport;
1543 functions->DepthRange = r700DepthRange;
1544 functions->PointSize = r700PointSize;
1545 functions->LineWidth = r700LineWidth;
1546 functions->LineStipple = r700LineStipple;
1547
1548 functions->PolygonOffset = r700PolygonOffset;
1549 functions->PolygonMode = r700PolygonMode;
1550
1551 functions->RenderMode = r700RenderMode;
1552
1553 functions->ClipPlane = r700ClipPlane;
1554
1555 functions->Scissor = radeonScissor;
1556
1557 functions->DrawBuffer = radeonDrawBuffer;
1558 functions->ReadBuffer = radeonReadBuffer;
1559
1560 }
1561