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r600: convert to using common radeon state atoms
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63 static void r700SetRenderTarget(context_t *context, int id);
64 static void r700SetDepthTarget(context_t *context);
65
66 void r700SetDefaultStates(context_t *context) //--------------------
67 {
68
69 }
70
71 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
72 {
73 context_t *context = R700_CONTEXT(ctx);
74
75 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
76 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
77 int i;
78
79 if (ctx->FragmentProgram._Current) {
80 struct r700_fragment_program *fp = (struct r700_fragment_program *)
81 (ctx->FragmentProgram._Current);
82 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
83 {
84 fp->r700AsmCode.bR6xx = 1;
85 }
86
87 if(GL_FALSE == fp->translated)
88 {
89 if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
90 {
91 //return GL_TRUE;
92 }
93 }
94 }
95
96 if (context->radeon.NewGLState)
97 {
98 struct r700_vertex_program *vp;
99 context->radeon.NewGLState = 0;
100
101 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
102 {
103 /* mat states from state var not array for sw */
104 dummy_attrib[i].stride = 0;
105
106 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
107 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
108 }
109
110 _tnl_UpdateFixedFunctionProgram(ctx);
111
112 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
113 {
114 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
115 }
116
117 r700SelectVertexShader(ctx);
118 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
119
120 if (vp->translated == GL_FALSE)
121 {
122 // TODO
123 //fprintf(stderr, "Failing back to sw-tcl\n");
124 //hw_tcl_on = future_hw_tcl_on = 0;
125 //r300ResetHwState(rmesa);
126 //
127 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
128 return;
129 }
130 }
131
132 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
133 }
134
135 /*
136 * To correctly position primitives:
137 */
138 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
139 {
140 context_t *context = R700_CONTEXT(ctx);
141 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
142 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
143 GLfloat xoffset = (GLfloat) dPriv->x;
144 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
145 const GLfloat *v = ctx->Viewport._WindowMap.m;
146 int id = 0;
147
148 GLfloat tx = v[MAT_TX] + xoffset;
149 GLfloat ty = (-v[MAT_TY]) + yoffset;
150
151 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
152 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
153 /* Note: this should also modify whatever data the context reset
154 * code uses...
155 */
156 R600_STATECHANGE(context, vpt);
157 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
158 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
159 }
160
161 radeonUpdateScissor(ctx);
162 }
163
164 /**
165 * Tell the card where to render (offset, pitch).
166 * Effected by glDrawBuffer, etc
167 */
168 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
169 {
170 context_t *context = R700_CONTEXT(ctx);
171 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
172
173 R600_STATECHANGE(context, cb_target);
174 R600_STATECHANGE(context, db_target);
175
176 r700SetRenderTarget(context, 0);
177 r700SetDepthTarget(context);
178 }
179
180 static void r700FetchStateParameter(GLcontext * ctx,
181 const gl_state_index state[STATE_LENGTH],
182 GLfloat * value)
183 {
184 /* TODO */
185 }
186
187 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
188 {
189 struct r700_fragment_program *fp;
190 struct gl_program_parameter_list *paramList;
191 GLuint i;
192
193 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
194 return;
195
196 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
197 if (!fp)
198 {
199 return;
200 }
201
202 paramList = fp->mesa_program.Base.Parameters;
203
204 if (!paramList)
205 {
206 return;
207 }
208
209 for (i = 0; i < paramList->NumParameters; i++)
210 {
211 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
212 {
213 r700FetchStateParameter(ctx,
214 paramList->Parameters[i].
215 StateIndexes,
216 paramList->ParameterValues[i]);
217 }
218 }
219 }
220
221 /**
222 * Called by Mesa after an internal state update.
223 */
224 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
225 {
226 context_t *context = R700_CONTEXT(ctx);
227
228 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
229
230 _swrast_InvalidateState(ctx, new_state);
231 _swsetup_InvalidateState(ctx, new_state);
232 _vbo_InvalidateState(ctx, new_state);
233 _tnl_InvalidateState(ctx, new_state);
234 _ae_invalidate_state(ctx, new_state);
235
236 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
237 {
238 _mesa_update_framebuffer(ctx);
239 /* this updates the DrawBuffer's Width/Height if it's a FBO */
240 _mesa_update_draw_buffer_bounds(ctx);
241
242 r700UpdateDrawBuffer(ctx);
243 }
244
245 r700UpdateStateParameters(ctx, new_state);
246
247 R600_STATECHANGE(context, cl);
248 R600_STATECHANGE(context, spi);
249
250 if(GL_TRUE == r700->bEnablePerspective)
251 {
252 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
253 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
254 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
255
256 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
257
258 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
259 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
260 }
261 else
262 {
263 /* For orthogonal case. */
264 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
265 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
266
267 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
268
269 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
270 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
271 }
272
273 context->radeon.NewGLState |= new_state;
274 }
275
276 static void r700SetDepthState(GLcontext * ctx)
277 {
278 context_t *context = R700_CONTEXT(ctx);
279 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
280
281 R600_STATECHANGE(context, db);
282
283 if (ctx->Depth.Test)
284 {
285 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
286 if (ctx->Depth.Mask)
287 {
288 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
289 }
290 else
291 {
292 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
293 }
294
295 switch (ctx->Depth.Func)
296 {
297 case GL_NEVER:
298 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
299 ZFUNC_shift, ZFUNC_mask);
300 break;
301 case GL_LESS:
302 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
303 ZFUNC_shift, ZFUNC_mask);
304 break;
305 case GL_EQUAL:
306 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
307 ZFUNC_shift, ZFUNC_mask);
308 break;
309 case GL_LEQUAL:
310 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
311 ZFUNC_shift, ZFUNC_mask);
312 break;
313 case GL_GREATER:
314 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
315 ZFUNC_shift, ZFUNC_mask);
316 break;
317 case GL_NOTEQUAL:
318 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
319 ZFUNC_shift, ZFUNC_mask);
320 break;
321 case GL_GEQUAL:
322 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
323 ZFUNC_shift, ZFUNC_mask);
324 break;
325 case GL_ALWAYS:
326 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
327 ZFUNC_shift, ZFUNC_mask);
328 break;
329 default:
330 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
331 ZFUNC_shift, ZFUNC_mask);
332 break;
333 }
334 }
335 else
336 {
337 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
338 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
339 }
340 }
341
342 static void r700SetAlphaState(GLcontext * ctx)
343 {
344 context_t *context = R700_CONTEXT(ctx);
345 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
346 uint32_t alpha_func = REF_ALWAYS;
347 GLboolean really_enabled = ctx->Color.AlphaEnabled;
348
349 R600_STATECHANGE(context, sx);
350
351 switch (ctx->Color.AlphaFunc) {
352 case GL_NEVER:
353 alpha_func = REF_NEVER;
354 break;
355 case GL_LESS:
356 alpha_func = REF_LESS;
357 break;
358 case GL_EQUAL:
359 alpha_func = REF_EQUAL;
360 break;
361 case GL_LEQUAL:
362 alpha_func = REF_LEQUAL;
363 break;
364 case GL_GREATER:
365 alpha_func = REF_GREATER;
366 break;
367 case GL_NOTEQUAL:
368 alpha_func = REF_NOTEQUAL;
369 break;
370 case GL_GEQUAL:
371 alpha_func = REF_GEQUAL;
372 break;
373 case GL_ALWAYS:
374 /*alpha_func = REF_ALWAYS; */
375 really_enabled = GL_FALSE;
376 break;
377 }
378
379 if (really_enabled) {
380 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
381 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
382 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
383 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
384 } else {
385 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
386 }
387
388 }
389
390 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
391 {
392 (void)func;
393 (void)ref;
394 r700SetAlphaState(ctx);
395 }
396
397
398 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
399 {
400 context_t *context = R700_CONTEXT(ctx);
401 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
402
403 R600_STATECHANGE(context, cb);
404
405 r700->CB_BLEND_RED.f32All = cf[0];
406 r700->CB_BLEND_GREEN.f32All = cf[1];
407 r700->CB_BLEND_BLUE.f32All = cf[2];
408 r700->CB_BLEND_ALPHA.f32All = cf[3];
409 }
410
411 static int blend_factor(GLenum factor, GLboolean is_src)
412 {
413 switch (factor) {
414 case GL_ZERO:
415 return BLEND_ZERO;
416 break;
417 case GL_ONE:
418 return BLEND_ONE;
419 break;
420 case GL_DST_COLOR:
421 return BLEND_DST_COLOR;
422 break;
423 case GL_ONE_MINUS_DST_COLOR:
424 return BLEND_ONE_MINUS_DST_COLOR;
425 break;
426 case GL_SRC_COLOR:
427 return BLEND_SRC_COLOR;
428 break;
429 case GL_ONE_MINUS_SRC_COLOR:
430 return BLEND_ONE_MINUS_SRC_COLOR;
431 break;
432 case GL_SRC_ALPHA:
433 return BLEND_SRC_ALPHA;
434 break;
435 case GL_ONE_MINUS_SRC_ALPHA:
436 return BLEND_ONE_MINUS_SRC_ALPHA;
437 break;
438 case GL_DST_ALPHA:
439 return BLEND_DST_ALPHA;
440 break;
441 case GL_ONE_MINUS_DST_ALPHA:
442 return BLEND_ONE_MINUS_DST_ALPHA;
443 break;
444 case GL_SRC_ALPHA_SATURATE:
445 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
446 break;
447 case GL_CONSTANT_COLOR:
448 return BLEND_CONSTANT_COLOR;
449 break;
450 case GL_ONE_MINUS_CONSTANT_COLOR:
451 return BLEND_ONE_MINUS_CONSTANT_COLOR;
452 break;
453 case GL_CONSTANT_ALPHA:
454 return BLEND_CONSTANT_ALPHA;
455 break;
456 case GL_ONE_MINUS_CONSTANT_ALPHA:
457 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
458 break;
459 default:
460 fprintf(stderr, "unknown blend factor %x\n", factor);
461 return (is_src) ? BLEND_ONE : BLEND_ZERO;
462 break;
463 }
464 }
465
466 static void r700SetBlendState(GLcontext * ctx)
467 {
468 context_t *context = R700_CONTEXT(ctx);
469 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
470 int id = 0;
471 uint32_t blend_reg = 0, eqn, eqnA;
472
473 R600_STATECHANGE(context, cb);
474
475 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
476 SETfield(blend_reg,
477 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
478 SETfield(blend_reg,
479 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
480 SETfield(blend_reg,
481 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
482 SETfield(blend_reg,
483 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
484 SETfield(blend_reg,
485 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
486 SETfield(blend_reg,
487 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
488 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
489 r700->CB_BLEND_CONTROL.u32All = blend_reg;
490 else
491 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
492 return;
493 }
494
495 SETfield(blend_reg,
496 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
497 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
498 SETfield(blend_reg,
499 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
500 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
501
502 switch (ctx->Color.BlendEquationRGB) {
503 case GL_FUNC_ADD:
504 eqn = COMB_DST_PLUS_SRC;
505 break;
506 case GL_FUNC_SUBTRACT:
507 eqn = COMB_SRC_MINUS_DST;
508 break;
509 case GL_FUNC_REVERSE_SUBTRACT:
510 eqn = COMB_DST_MINUS_SRC;
511 break;
512 case GL_MIN:
513 eqn = COMB_MIN_DST_SRC;
514 SETfield(blend_reg,
515 BLEND_ONE,
516 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
517 SETfield(blend_reg,
518 BLEND_ONE,
519 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
520 break;
521 case GL_MAX:
522 eqn = COMB_MAX_DST_SRC;
523 SETfield(blend_reg,
524 BLEND_ONE,
525 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
526 SETfield(blend_reg,
527 BLEND_ONE,
528 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
529 break;
530
531 default:
532 fprintf(stderr,
533 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
534 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
535 return;
536 }
537 SETfield(blend_reg,
538 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
539
540 SETfield(blend_reg,
541 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
542 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
543 SETfield(blend_reg,
544 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
545 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
546
547 switch (ctx->Color.BlendEquationA) {
548 case GL_FUNC_ADD:
549 eqnA = COMB_DST_PLUS_SRC;
550 break;
551 case GL_FUNC_SUBTRACT:
552 eqnA = COMB_SRC_MINUS_DST;
553 break;
554 case GL_FUNC_REVERSE_SUBTRACT:
555 eqnA = COMB_DST_MINUS_SRC;
556 break;
557 case GL_MIN:
558 eqnA = COMB_MIN_DST_SRC;
559 SETfield(blend_reg,
560 BLEND_ONE,
561 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
562 SETfield(blend_reg,
563 BLEND_ONE,
564 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
565 break;
566 case GL_MAX:
567 eqnA = COMB_MAX_DST_SRC;
568 SETfield(blend_reg,
569 BLEND_ONE,
570 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
571 SETfield(blend_reg,
572 BLEND_ONE,
573 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
574 break;
575 default:
576 fprintf(stderr,
577 "[%s:%u] Invalid A blend equation (0x%04x).\n",
578 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
579 return;
580 }
581
582 SETfield(blend_reg,
583 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
584
585 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
586
587 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
588 r700->CB_BLEND_CONTROL.u32All = blend_reg;
589 else {
590 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
591 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
592 }
593 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
594 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
595
596 }
597
598 static void r700BlendEquationSeparate(GLcontext * ctx,
599 GLenum modeRGB, GLenum modeA) //-----------------
600 {
601 r700SetBlendState(ctx);
602 }
603
604 static void r700BlendFuncSeparate(GLcontext * ctx,
605 GLenum sfactorRGB, GLenum dfactorRGB,
606 GLenum sfactorA, GLenum dfactorA) //------------------------
607 {
608 r700SetBlendState(ctx);
609 }
610
611 /**
612 * Translate LogicOp enums into hardware representation.
613 */
614 static GLuint translate_logicop(GLenum logicop)
615 {
616 switch (logicop) {
617 case GL_CLEAR:
618 return 0x00;
619 case GL_SET:
620 return 0xff;
621 case GL_COPY:
622 return 0xcc;
623 case GL_COPY_INVERTED:
624 return 0x33;
625 case GL_NOOP:
626 return 0xaa;
627 case GL_INVERT:
628 return 0x55;
629 case GL_AND:
630 return 0x88;
631 case GL_NAND:
632 return 0x77;
633 case GL_OR:
634 return 0xee;
635 case GL_NOR:
636 return 0x11;
637 case GL_XOR:
638 return 0x66;
639 case GL_EQUIV:
640 return 0xaa;
641 case GL_AND_REVERSE:
642 return 0x44;
643 case GL_AND_INVERTED:
644 return 0x22;
645 case GL_OR_REVERSE:
646 return 0xdd;
647 case GL_OR_INVERTED:
648 return 0xbb;
649 default:
650 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
651 return 0xcc;
652 }
653 }
654
655 /**
656 * Used internally to update the r300->hw hardware state to match the
657 * current OpenGL state.
658 */
659 static void r700SetLogicOpState(GLcontext *ctx)
660 {
661 context_t *context = R700_CONTEXT(ctx);
662 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
663
664 R600_STATECHANGE(context, cb);
665
666 if (RGBA_LOGICOP_ENABLED(ctx))
667 SETfield(r700->CB_COLOR_CONTROL.u32All,
668 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
669 else
670 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
671 }
672
673 /**
674 * Called by Mesa when an application program changes the LogicOp state
675 * via glLogicOp.
676 */
677 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
678 {
679 if (RGBA_LOGICOP_ENABLED(ctx))
680 r700SetLogicOpState(ctx);
681 }
682
683 static void r700UpdateCulling(GLcontext * ctx)
684 {
685 context_t *context = R700_CONTEXT(ctx);
686 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
687
688 R600_STATECHANGE(context, su);
689
690 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
691 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
692 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
693
694 if (ctx->Polygon.CullFlag)
695 {
696 switch (ctx->Polygon.CullFaceMode)
697 {
698 case GL_FRONT:
699 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
700 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
701 break;
702 case GL_BACK:
703 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
704 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
705 break;
706 case GL_FRONT_AND_BACK:
707 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
708 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
709 break;
710 default:
711 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
712 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
713 break;
714 }
715 }
716
717 switch (ctx->Polygon.FrontFace)
718 {
719 case GL_CW:
720 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
721 break;
722 case GL_CCW:
723 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
724 break;
725 default:
726 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
727 break;
728 }
729 }
730
731 static void r700UpdateLineStipple(GLcontext * ctx)
732 {
733 context_t *context = R700_CONTEXT(ctx);
734 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
735
736 R600_STATECHANGE(context, sc);
737
738 if (ctx->Line.StippleFlag)
739 {
740 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
741 }
742 else
743 {
744 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
745 }
746 }
747
748 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
749 {
750 context_t *context = R700_CONTEXT(ctx);
751
752 switch (cap) {
753 case GL_TEXTURE_1D:
754 case GL_TEXTURE_2D:
755 case GL_TEXTURE_3D:
756 /* empty */
757 break;
758 case GL_FOG:
759 /* empty */
760 break;
761 case GL_ALPHA_TEST:
762 r700SetAlphaState(ctx);
763 break;
764 case GL_COLOR_LOGIC_OP:
765 r700SetLogicOpState(ctx);
766 /* fall-through, because logic op overrides blending */
767 case GL_BLEND:
768 r700SetBlendState(ctx);
769 break;
770 case GL_CLIP_PLANE0:
771 case GL_CLIP_PLANE1:
772 case GL_CLIP_PLANE2:
773 case GL_CLIP_PLANE3:
774 case GL_CLIP_PLANE4:
775 case GL_CLIP_PLANE5:
776 r700SetClipPlaneState(ctx, cap, state);
777 break;
778 case GL_DEPTH_TEST:
779 r700SetDepthState(ctx);
780 break;
781 case GL_STENCIL_TEST:
782 r700SetStencilState(ctx, state);
783 break;
784 case GL_CULL_FACE:
785 r700UpdateCulling(ctx);
786 break;
787 case GL_POLYGON_OFFSET_POINT:
788 case GL_POLYGON_OFFSET_LINE:
789 case GL_POLYGON_OFFSET_FILL:
790 r700SetPolygonOffsetState(ctx, state);
791 break;
792 case GL_SCISSOR_TEST:
793 radeon_firevertices(&context->radeon);
794 context->radeon.state.scissor.enabled = state;
795 radeonUpdateScissor(ctx);
796 break;
797 case GL_LINE_STIPPLE:
798 r700UpdateLineStipple(ctx);
799 break;
800 default:
801 break;
802 }
803
804 }
805
806 /**
807 * Handle glColorMask()
808 */
809 static void r700ColorMask(GLcontext * ctx,
810 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
811 {
812 context_t *context = R700_CONTEXT(ctx);
813 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
814 unsigned int mask = ((r ? 1 : 0) |
815 (g ? 2 : 0) |
816 (b ? 4 : 0) |
817 (a ? 8 : 0));
818
819 if (mask != r700->CB_SHADER_MASK.u32All) {
820 R600_STATECHANGE(context, cb);
821 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
822 }
823 }
824
825 /**
826 * Change the depth testing function.
827 *
828 * \note Mesa already filters redundant calls to this function.
829 */
830 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
831 {
832 r700SetDepthState(ctx);
833 }
834
835 /**
836 * Enable/Disable depth writing.
837 *
838 * \note Mesa already filters redundant calls to this function.
839 */
840 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
841 {
842 r700SetDepthState(ctx);
843 }
844
845 /**
846 * Change the culling mode.
847 *
848 * \note Mesa already filters redundant calls to this function.
849 */
850 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
851 {
852 r700UpdateCulling(ctx);
853 }
854
855 /* =============================================================
856 * Fog
857 */
858 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
859 {
860 }
861
862 /**
863 * Change the polygon orientation.
864 *
865 * \note Mesa already filters redundant calls to this function.
866 */
867 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
868 {
869 r700UpdateCulling(ctx);
870 r700UpdatePolygonMode(ctx);
871 }
872
873 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
874 {
875 context_t *context = R700_CONTEXT(ctx);
876 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
877
878 R600_STATECHANGE(context, spi);
879
880 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
881 switch (mode) {
882 case GL_FLAT:
883 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
884 break;
885 case GL_SMOOTH:
886 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
887 break;
888 default:
889 return;
890 }
891 }
892
893 /* =============================================================
894 * Point state
895 */
896 static void r700PointSize(GLcontext * ctx, GLfloat size)
897 {
898 context_t *context = R700_CONTEXT(ctx);
899 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
900
901 R600_STATECHANGE(context, su);
902
903 /* We need to clamp to user defined range here, because
904 * the HW clamping happens only for per vertex point size. */
905 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
906
907 /* same size limits for AA, non-AA points */
908 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
909
910 /* format is 12.4 fixed point */
911 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
912 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
913 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
914 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
915
916 }
917
918 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
919 {
920 context_t *context = R700_CONTEXT(ctx);
921 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
922
923 R600_STATECHANGE(context, su);
924
925 /* format is 12.4 fixed point */
926 switch (pname) {
927 case GL_POINT_SIZE_MIN:
928 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
929 MIN_SIZE_shift, MIN_SIZE_mask);
930 break;
931 case GL_POINT_SIZE_MAX:
932 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
933 MAX_SIZE_shift, MAX_SIZE_mask);
934 break;
935 case GL_POINT_DISTANCE_ATTENUATION:
936 break;
937 case GL_POINT_FADE_THRESHOLD_SIZE:
938 break;
939 default:
940 break;
941 }
942 }
943
944 static int translate_stencil_func(int func)
945 {
946 switch (func) {
947 case GL_NEVER:
948 return REF_NEVER;
949 case GL_LESS:
950 return REF_LESS;
951 case GL_EQUAL:
952 return REF_EQUAL;
953 case GL_LEQUAL:
954 return REF_LEQUAL;
955 case GL_GREATER:
956 return REF_GREATER;
957 case GL_NOTEQUAL:
958 return REF_NOTEQUAL;
959 case GL_GEQUAL:
960 return REF_GEQUAL;
961 case GL_ALWAYS:
962 return REF_ALWAYS;
963 }
964 return 0;
965 }
966
967 static int translate_stencil_op(int op)
968 {
969 switch (op) {
970 case GL_KEEP:
971 return STENCIL_KEEP;
972 case GL_ZERO:
973 return STENCIL_ZERO;
974 case GL_REPLACE:
975 return STENCIL_REPLACE;
976 case GL_INCR:
977 return STENCIL_INCR_CLAMP;
978 case GL_DECR:
979 return STENCIL_DECR_CLAMP;
980 case GL_INCR_WRAP_EXT:
981 return STENCIL_INCR_WRAP;
982 case GL_DECR_WRAP_EXT:
983 return STENCIL_DECR_WRAP;
984 case GL_INVERT:
985 return STENCIL_INVERT;
986 default:
987 WARN_ONCE("Do not know how to translate stencil op");
988 return STENCIL_KEEP;
989 }
990 return 0;
991 }
992
993 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
994 {
995 context_t *context = R700_CONTEXT(ctx);
996 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
997 GLboolean hw_stencil = GL_FALSE;
998
999 //fixme
1000 //r300CatchStencilFallback(ctx);
1001
1002 if (ctx->DrawBuffer) {
1003 struct radeon_renderbuffer *rrbStencil
1004 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1005 hw_stencil = (rrbStencil && rrbStencil->bo);
1006 }
1007
1008 if (hw_stencil) {
1009 R600_STATECHANGE(context, db);
1010 if (state)
1011 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
1012 else
1013 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
1014 }
1015 }
1016
1017 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
1018 GLenum func, GLint ref, GLuint mask) //---------------------
1019 {
1020 context_t *context = R700_CONTEXT(ctx);
1021 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1022 const unsigned back = ctx->Stencil._BackFace;
1023
1024 //fixme
1025 //r300CatchStencilFallback(ctx);
1026
1027 R600_STATECHANGE(context, db);
1028
1029 //front
1030 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1031 STENCILREF_shift, STENCILREF_mask);
1032 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1033 STENCILMASK_shift, STENCILMASK_mask);
1034
1035 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1036 STENCILFUNC_shift, STENCILFUNC_mask);
1037
1038 //back
1039 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1040 STENCILREF_BF_shift, STENCILREF_BF_mask);
1041 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1042 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1043
1044 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1045 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1046
1047 }
1048
1049 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1050 {
1051 context_t *context = R700_CONTEXT(ctx);
1052 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1053 const unsigned back = ctx->Stencil._BackFace;
1054
1055 //fixme
1056 //r300CatchStencilFallback(ctx);
1057
1058 R600_STATECHANGE(context, db);
1059
1060 // front
1061 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1062 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1063
1064 // back
1065 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1066 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1067
1068 }
1069
1070 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1071 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1072 {
1073 context_t *context = R700_CONTEXT(ctx);
1074 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1075 const unsigned back = ctx->Stencil._BackFace;
1076
1077 //fixme
1078 //r300CatchStencilFallback(ctx);
1079
1080 R600_STATECHANGE(context, db);
1081
1082 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1083 STENCILFAIL_shift, STENCILFAIL_mask);
1084 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1085 STENCILZFAIL_shift, STENCILZFAIL_mask);
1086 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1087 STENCILZPASS_shift, STENCILZPASS_mask);
1088
1089 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1090 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1091 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1092 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1093 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1094 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1095 }
1096
1097 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1098 {
1099 context_t *context = R700_CONTEXT(ctx);
1100 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1101 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1102 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1103 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1104 const GLfloat *v = ctx->Viewport._WindowMap.m;
1105 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1106 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1107 GLfloat y_scale, y_bias;
1108
1109 if (render_to_fbo) {
1110 y_scale = 1.0;
1111 y_bias = 0;
1112 } else {
1113 y_scale = -1.0;
1114 y_bias = yoffset;
1115 }
1116
1117 GLfloat sx = v[MAT_SX];
1118 GLfloat tx = v[MAT_TX] + xoffset;
1119 GLfloat sy = v[MAT_SY] * y_scale;
1120 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1121 GLfloat sz = v[MAT_SZ] * depthScale;
1122 GLfloat tz = v[MAT_TZ] * depthScale;
1123
1124 R600_STATECHANGE(context, vpt);
1125
1126 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1127 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1128
1129 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1130 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1131
1132 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1133 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1134
1135 r700->viewport[id].enabled = GL_TRUE;
1136
1137 r700SetScissor(context);
1138 }
1139
1140
1141 static void r700Viewport(GLcontext * ctx,
1142 GLint x,
1143 GLint y,
1144 GLsizei width,
1145 GLsizei height) //--------------------
1146 {
1147 r700UpdateWindow(ctx, 0);
1148
1149 radeon_viewport(ctx, x, y, width, height);
1150 }
1151
1152 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1153 {
1154 r700UpdateWindow(ctx, 0);
1155 }
1156
1157 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1158 {
1159 context_t *context = R700_CONTEXT(ctx);
1160 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1161 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1162
1163 R600_STATECHANGE(context, su);
1164
1165 if (lineWidth > 0xFFFF)
1166 lineWidth = 0xFFFF;
1167 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1168 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1169 }
1170
1171 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1172 {
1173 context_t *context = R700_CONTEXT(ctx);
1174 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1175
1176 R600_STATECHANGE(context, sc);
1177
1178 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1179 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1180 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1181 }
1182
1183 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1184 {
1185 context_t *context = R700_CONTEXT(ctx);
1186 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1187
1188 R600_STATECHANGE(context, su);
1189
1190 if (state) {
1191 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1192 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1193 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1194 } else {
1195 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1196 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1197 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1198 }
1199 }
1200
1201 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1202 {
1203 context_t *context = R700_CONTEXT(ctx);
1204 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1205 GLfloat constant = units;
1206
1207 switch (ctx->Visual.depthBits) {
1208 case 16:
1209 constant *= 4.0;
1210 break;
1211 case 24:
1212 constant *= 2.0;
1213 break;
1214 }
1215
1216 factor *= 12.0;
1217
1218 R600_STATECHANGE(context, su);
1219
1220 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1221 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1222 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1223 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1224 }
1225
1226 static void r700UpdatePolygonMode(GLcontext * ctx)
1227 {
1228 context_t *context = R700_CONTEXT(ctx);
1229 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1230
1231 R600_STATECHANGE(context, su);
1232
1233 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1234
1235 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1236 if (ctx->Polygon.FrontMode != GL_FILL ||
1237 ctx->Polygon.BackMode != GL_FILL) {
1238 GLenum f, b;
1239
1240 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1241 * correctly by selecting the correct front and back face
1242 */
1243 if (ctx->Polygon.FrontFace == GL_CCW) {
1244 f = ctx->Polygon.FrontMode;
1245 b = ctx->Polygon.BackMode;
1246 } else {
1247 f = ctx->Polygon.BackMode;
1248 b = ctx->Polygon.FrontMode;
1249 }
1250
1251 /* Enable polygon mode */
1252 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1253
1254 switch (f) {
1255 case GL_LINE:
1256 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1257 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1258 break;
1259 case GL_POINT:
1260 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1261 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1262 break;
1263 case GL_FILL:
1264 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1265 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1266 break;
1267 }
1268
1269 switch (b) {
1270 case GL_LINE:
1271 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1272 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1273 break;
1274 case GL_POINT:
1275 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1276 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1277 break;
1278 case GL_FILL:
1279 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1280 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1281 break;
1282 }
1283 }
1284 }
1285
1286 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1287 {
1288 (void)face;
1289 (void)mode;
1290
1291 r700UpdatePolygonMode(ctx);
1292 }
1293
1294 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1295 {
1296 }
1297
1298 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1299 {
1300 context_t *context = R700_CONTEXT(ctx);
1301 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1302 GLint p;
1303 GLint *ip;
1304
1305 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1306 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1307
1308 R600_STATECHANGE(context, ucp);
1309
1310 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1311 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1312 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1313 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1314 }
1315
1316 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1317 {
1318 context_t *context = R700_CONTEXT(ctx);
1319 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1320 GLuint p;
1321
1322 p = cap - GL_CLIP_PLANE0;
1323
1324 R600_STATECHANGE(context, cl);
1325
1326 if (state) {
1327 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1328 r700->ucp[p].enabled = GL_TRUE;
1329 r700ClipPlane(ctx, cap, NULL);
1330 } else {
1331 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1332 r700->ucp[p].enabled = GL_FALSE;
1333 }
1334 }
1335
1336 void r700SetScissor(context_t *context) //---------------
1337 {
1338 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1339 unsigned x1, y1, x2, y2;
1340 int id = 0;
1341 struct radeon_renderbuffer *rrb;
1342
1343 rrb = radeon_get_colorbuffer(&context->radeon);
1344 if (!rrb || !rrb->bo) {
1345 return;
1346 }
1347 if (context->radeon.state.scissor.enabled) {
1348 x1 = context->radeon.state.scissor.rect.x1;
1349 y1 = context->radeon.state.scissor.rect.y1;
1350 x2 = context->radeon.state.scissor.rect.x2 - 1;
1351 y2 = context->radeon.state.scissor.rect.y2 - 1;
1352 } else {
1353 x1 = rrb->dPriv->x;
1354 y1 = rrb->dPriv->y;
1355 x2 = rrb->dPriv->x + rrb->dPriv->w;
1356 y2 = rrb->dPriv->y + rrb->dPriv->h;
1357 }
1358
1359 R600_STATECHANGE(context, sc);
1360
1361 /* window */
1362 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1363 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1364 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1365 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1366 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1367
1368 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1369 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1370 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1371 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1372
1373
1374 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1375 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1376 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1377 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1378 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1379 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1380 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1381 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1382
1383 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1384 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1385 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1386 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1387 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1388 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1389
1390 /* more....2d clip */
1391 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1392 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1393 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1394 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1395 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1396 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1397 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1398 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1399 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1400
1401 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1402 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1403 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1404 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1405 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1406 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1407 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1408 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1409 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1410
1411 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1412 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1413 r700->viewport[id].enabled = GL_TRUE;
1414 }
1415
1416 static void r700SetRenderTarget(context_t *context, int id)
1417 {
1418 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1419
1420 struct radeon_renderbuffer *rrb;
1421 unsigned int nPitchInPixel;
1422
1423 rrb = radeon_get_colorbuffer(&context->radeon);
1424 if (!rrb || !rrb->bo) {
1425 fprintf(stderr, "no rrb\n");
1426 return;
1427 }
1428
1429 R600_STATECHANGE(context, cb_target);
1430 R600_STATECHANGE(context, cb);
1431
1432 /* screen/window/view */
1433 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1434
1435 /* color buffer */
1436 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1437
1438 nPitchInPixel = rrb->pitch/rrb->cpp;
1439 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1440 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1441 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1442 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1443 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1444 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1445 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1446 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1447 if(4 == rrb->cpp)
1448 {
1449 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1450 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1451 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1452 }
1453 else
1454 {
1455 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1456 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1457 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1458 COMP_SWAP_shift, COMP_SWAP_mask);
1459 }
1460 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1461 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1462 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1463
1464 r700->render_target[id].enabled = GL_TRUE;
1465 }
1466
1467 static void r700SetDepthTarget(context_t *context)
1468 {
1469 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1470
1471 struct radeon_renderbuffer *rrb;
1472 unsigned int nPitchInPixel;
1473
1474 rrb = radeon_get_depthbuffer(&context->radeon);
1475 if (!rrb)
1476 return;
1477
1478 R600_STATECHANGE(context, db_target);
1479
1480 /* depth buf */
1481 r700->DB_DEPTH_SIZE.u32All = 0;
1482 r700->DB_DEPTH_BASE.u32All = 0;
1483 r700->DB_DEPTH_INFO.u32All = 0;
1484 r700->DB_DEPTH_VIEW.u32All = 0;
1485
1486 nPitchInPixel = rrb->pitch/rrb->cpp;
1487
1488 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1489 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1490 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1491 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1492
1493 if(4 == rrb->cpp)
1494 {
1495 switch (GL_CONTEXT(context)->Visual.depthBits)
1496 {
1497 case 16:
1498 case 24:
1499 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1500 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1501 break;
1502 default:
1503 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1504 GL_CONTEXT(context)->Visual.depthBits);
1505 _mesa_exit(-1);
1506 }
1507 }
1508 else
1509 {
1510 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1511 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1512 }
1513 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1514 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1515 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1516 }
1517
1518 static void r700InitSQConfig(GLcontext * ctx)
1519 {
1520 context_t *context = R700_CONTEXT(ctx);
1521 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1522 int ps_prio;
1523 int vs_prio;
1524 int gs_prio;
1525 int es_prio;
1526 int num_ps_gprs;
1527 int num_vs_gprs;
1528 int num_gs_gprs;
1529 int num_es_gprs;
1530 int num_temp_gprs;
1531 int num_ps_threads;
1532 int num_vs_threads;
1533 int num_gs_threads;
1534 int num_es_threads;
1535 int num_ps_stack_entries;
1536 int num_vs_stack_entries;
1537 int num_gs_stack_entries;
1538 int num_es_stack_entries;
1539
1540 R600_STATECHANGE(context, sq);
1541
1542 // SQ
1543 ps_prio = 0;
1544 vs_prio = 1;
1545 gs_prio = 2;
1546 es_prio = 3;
1547 switch (context->radeon.radeonScreen->chip_family) {
1548 case CHIP_FAMILY_R600:
1549 num_ps_gprs = 192;
1550 num_vs_gprs = 56;
1551 num_temp_gprs = 4;
1552 num_gs_gprs = 0;
1553 num_es_gprs = 0;
1554 num_ps_threads = 136;
1555 num_vs_threads = 48;
1556 num_gs_threads = 4;
1557 num_es_threads = 4;
1558 num_ps_stack_entries = 128;
1559 num_vs_stack_entries = 128;
1560 num_gs_stack_entries = 0;
1561 num_es_stack_entries = 0;
1562 break;
1563 case CHIP_FAMILY_RV630:
1564 case CHIP_FAMILY_RV635:
1565 num_ps_gprs = 84;
1566 num_vs_gprs = 36;
1567 num_temp_gprs = 4;
1568 num_gs_gprs = 0;
1569 num_es_gprs = 0;
1570 num_ps_threads = 144;
1571 num_vs_threads = 40;
1572 num_gs_threads = 4;
1573 num_es_threads = 4;
1574 num_ps_stack_entries = 40;
1575 num_vs_stack_entries = 40;
1576 num_gs_stack_entries = 32;
1577 num_es_stack_entries = 16;
1578 break;
1579 case CHIP_FAMILY_RV610:
1580 case CHIP_FAMILY_RV620:
1581 case CHIP_FAMILY_RS780:
1582 default:
1583 num_ps_gprs = 84;
1584 num_vs_gprs = 36;
1585 num_temp_gprs = 4;
1586 num_gs_gprs = 0;
1587 num_es_gprs = 0;
1588 num_ps_threads = 136;
1589 num_vs_threads = 48;
1590 num_gs_threads = 4;
1591 num_es_threads = 4;
1592 num_ps_stack_entries = 40;
1593 num_vs_stack_entries = 40;
1594 num_gs_stack_entries = 32;
1595 num_es_stack_entries = 16;
1596 break;
1597 case CHIP_FAMILY_RV670:
1598 num_ps_gprs = 144;
1599 num_vs_gprs = 40;
1600 num_temp_gprs = 4;
1601 num_gs_gprs = 0;
1602 num_es_gprs = 0;
1603 num_ps_threads = 136;
1604 num_vs_threads = 48;
1605 num_gs_threads = 4;
1606 num_es_threads = 4;
1607 num_ps_stack_entries = 40;
1608 num_vs_stack_entries = 40;
1609 num_gs_stack_entries = 32;
1610 num_es_stack_entries = 16;
1611 break;
1612 case CHIP_FAMILY_RV770:
1613 num_ps_gprs = 192;
1614 num_vs_gprs = 56;
1615 num_temp_gprs = 4;
1616 num_gs_gprs = 0;
1617 num_es_gprs = 0;
1618 num_ps_threads = 188;
1619 num_vs_threads = 60;
1620 num_gs_threads = 0;
1621 num_es_threads = 0;
1622 num_ps_stack_entries = 256;
1623 num_vs_stack_entries = 256;
1624 num_gs_stack_entries = 0;
1625 num_es_stack_entries = 0;
1626 break;
1627 case CHIP_FAMILY_RV730:
1628 case CHIP_FAMILY_RV740:
1629 num_ps_gprs = 84;
1630 num_vs_gprs = 36;
1631 num_temp_gprs = 4;
1632 num_gs_gprs = 0;
1633 num_es_gprs = 0;
1634 num_ps_threads = 188;
1635 num_vs_threads = 60;
1636 num_gs_threads = 0;
1637 num_es_threads = 0;
1638 num_ps_stack_entries = 128;
1639 num_vs_stack_entries = 128;
1640 num_gs_stack_entries = 0;
1641 num_es_stack_entries = 0;
1642 break;
1643 case CHIP_FAMILY_RV710:
1644 num_ps_gprs = 192;
1645 num_vs_gprs = 56;
1646 num_temp_gprs = 4;
1647 num_gs_gprs = 0;
1648 num_es_gprs = 0;
1649 num_ps_threads = 144;
1650 num_vs_threads = 48;
1651 num_gs_threads = 0;
1652 num_es_threads = 0;
1653 num_ps_stack_entries = 128;
1654 num_vs_stack_entries = 128;
1655 num_gs_stack_entries = 0;
1656 num_es_stack_entries = 0;
1657 break;
1658 }
1659
1660 r700->sq_config.SQ_CONFIG.u32All = 0;
1661 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1662 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1663 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1664 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1665 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1666 else
1667 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1668 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1669 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1670 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1671 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1672 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1673 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1674
1675 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1676 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1677 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1678 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1679 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1680
1681 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1682 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1683 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1684
1685 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1686 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1687 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1688 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1689 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1690 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1691 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1692 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1693 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1694
1695 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1696 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1697 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1698 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1699 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1700
1701 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1702 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1703 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1704 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1705 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1706
1707 }
1708
1709 /**
1710 * Calculate initial hardware state and register state functions.
1711 * Assumes that the command buffer and state atoms have been
1712 * initialized already.
1713 */
1714 void r700InitState(GLcontext * ctx) //-------------------
1715 {
1716 context_t *context = R700_CONTEXT(ctx);
1717 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1718
1719 radeon_firevertices(&context->radeon);
1720
1721 r700->TA_CNTL_AUX.u32All = 0;
1722 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1723 r700->VC_ENHANCE.u32All = 0;
1724 r700->DB_WATERMARKS.u32All = 0;
1725 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1726 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1727 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1728 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1729 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1730 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1731 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1732 r700->DB_DEBUG.u32All = 0x82000000;
1733 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1734 } else {
1735 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1736 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1737 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1738 }
1739
1740 /* Turn off vgt reuse */
1741 r700->VGT_REUSE_OFF.u32All = 0;
1742 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1743
1744 /* Specify offsetting and clamp values for vertices */
1745 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1746 r700->VGT_MIN_VTX_INDX.u32All = 0;
1747 r700->VGT_INDX_OFFSET.u32All = 0;
1748
1749 /* default shader connections. */
1750 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1751 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1752
1753 r700->SPI_THREAD_GROUPING.u32All = 0;
1754 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1755 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1756
1757 /* screen */
1758 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1759
1760 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1761 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1762 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1763 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1764 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1765 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1766
1767 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1768 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1769 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1770
1771 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1772 r700->PA_SC_EDGERULE.u32All = 0;
1773 else
1774 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1775
1776 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1777 r700->PA_SC_MODE_CNTL.u32All = 0;
1778 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1779 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1780 } else {
1781 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1782 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1783 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1784 }
1785
1786 /* Do scale XY and Z by 1/W0. */
1787 r700->bEnablePerspective = GL_TRUE;
1788 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1789 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1790 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1791
1792 /* Enable viewport scaling for all three axis */
1793 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1794 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1795 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1796 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1797 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1798 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1799
1800 /* GL uses last vtx for flat shading components */
1801 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1802
1803 /* Set up vertex control */
1804 r700->PA_SU_VTX_CNTL.u32All = 0;
1805 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1806 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1807 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1808 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1809
1810 /* to 1.0 = no guard band */
1811 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1812 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1813 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1814 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1815
1816 /* Enable all samples for multi-sample anti-aliasing */
1817 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1818 /* Turn off AA */
1819 r700->PA_SC_AA_CONFIG.u32All = 0;
1820
1821 r700->SX_MISC.u32All = 0;
1822
1823 r700InitSQConfig(ctx);
1824
1825 r700ColorMask(ctx,
1826 ctx->Color.ColorMask[RCOMP],
1827 ctx->Color.ColorMask[GCOMP],
1828 ctx->Color.ColorMask[BCOMP],
1829 ctx->Color.ColorMask[ACOMP]);
1830
1831 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1832 r700DepthMask(ctx, ctx->Depth.Mask);
1833 r700DepthFunc(ctx, ctx->Depth.Func);
1834 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1835
1836 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1837
1838 r700->DB_RENDER_CONTROL.u32All = 0;
1839 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1840 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1841 r700->DB_RENDER_OVERRIDE.u32All = 0;
1842 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1843 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1844 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1845 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1846 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1847
1848 r700->DB_ALPHA_TO_MASK.u32All = 0;
1849 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1850 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1851 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1852 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1853
1854 /* stencil */
1855 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1856 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1857 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1858 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1859 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1860 ctx->Stencil.ZFailFunc[0],
1861 ctx->Stencil.ZPassFunc[0]);
1862
1863 r700UpdateCulling(ctx);
1864
1865 r700SetBlendState(ctx);
1866 r700SetLogicOpState(ctx);
1867
1868 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1869 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1870
1871 r700PointSize(ctx, 1.0);
1872
1873 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1874 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1875
1876 r700LineWidth(ctx, 1.0);
1877
1878 r700->PA_SC_LINE_CNTL.u32All = 0;
1879 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1880 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1881
1882 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1883 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1884 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1885 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1886 ctx->Polygon.OffsetUnits);
1887 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1888 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1889 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1890
1891 /* CB */
1892 r700BlendColor(ctx, ctx->Color.BlendColor);
1893
1894 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1895 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1896 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1897 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1898 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1899 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1900 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1901
1902 /* Disable color compares */
1903 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1904 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1905 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1906 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1907 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1908 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1909
1910 /* Zero out source */
1911 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1912
1913 /* Put a compare color in for error checking */
1914 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1915
1916 /* Set up color compare mask */
1917 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1918
1919 context->radeon.hw.all_dirty = GL_TRUE;
1920
1921 }
1922
1923 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1924 {
1925 functions->UpdateState = r700InvalidateState;
1926 functions->AlphaFunc = r700AlphaFunc;
1927 functions->BlendColor = r700BlendColor;
1928 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1929 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1930 functions->Enable = r700Enable;
1931 functions->ColorMask = r700ColorMask;
1932 functions->DepthFunc = r700DepthFunc;
1933 functions->DepthMask = r700DepthMask;
1934 functions->CullFace = r700CullFace;
1935 functions->Fogfv = r700Fogfv;
1936 functions->FrontFace = r700FrontFace;
1937 functions->ShadeModel = r700ShadeModel;
1938 functions->LogicOpcode = r700LogicOpcode;
1939
1940 /* ARB_point_parameters */
1941 functions->PointParameterfv = r700PointParameter;
1942
1943 /* Stencil related */
1944 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1945 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1946 functions->StencilOpSeparate = r700StencilOpSeparate;
1947
1948 /* Viewport related */
1949 functions->Viewport = r700Viewport;
1950 functions->DepthRange = r700DepthRange;
1951 functions->PointSize = r700PointSize;
1952 functions->LineWidth = r700LineWidth;
1953 functions->LineStipple = r700LineStipple;
1954
1955 functions->PolygonOffset = r700PolygonOffset;
1956 functions->PolygonMode = r700PolygonMode;
1957
1958 functions->RenderMode = r700RenderMode;
1959
1960 functions->ClipPlane = r700ClipPlane;
1961
1962 functions->Scissor = radeonScissor;
1963
1964 functions->DrawBuffer = radeonDrawBuffer;
1965 functions->ReadBuffer = radeonReadBuffer;
1966
1967 }
1968