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r600: fill in point functions
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62
63 void r700SetDefaultStates(context_t *context) //--------------------
64 {
65
66 }
67
68 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
69 {
70 context_t *context = R700_CONTEXT(ctx);
71
72 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
73 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
74
75 struct r700_vertex_program *vp;
76 int i;
77
78 if (context->radeon.NewGLState)
79 {
80 context->radeon.NewGLState = 0;
81
82 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
83 {
84 /* mat states from state var not array for sw */
85 dummy_attrib[i].stride = 0;
86
87 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
88 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
89 }
90
91 _tnl_UpdateFixedFunctionProgram(ctx);
92
93 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
94 {
95 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
96 }
97
98 r700SelectVertexShader(ctx);
99 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
100
101 if (vp->translated == GL_FALSE)
102 {
103 // TODO
104 //fprintf(stderr, "Failing back to sw-tcl\n");
105 //hw_tcl_on = future_hw_tcl_on = 0;
106 //r300ResetHwState(rmesa);
107 //
108 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
109 return;
110 }
111 }
112
113 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
114 }
115
116 /*
117 * To correctly position primitives:
118 */
119 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
120 {
121 context_t *context = R700_CONTEXT(ctx);
122 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
123 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
124 GLfloat xoffset = (GLfloat) dPriv->x;
125 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
126 const GLfloat *v = ctx->Viewport._WindowMap.m;
127 int id = 0;
128
129 GLfloat tx = v[MAT_TX] + xoffset;
130 GLfloat ty = (-v[MAT_TY]) + yoffset;
131
132 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
133 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
134
135 radeonUpdateScissor(ctx);
136 }
137
138 /**
139 * Tell the card where to render (offset, pitch).
140 * Effected by glDrawBuffer, etc
141 */
142 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
143 {
144 #if 0 /* to be enabled */
145 context_t *context = R700_CONTEXT(ctx);
146
147 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
148 {
149 case BUFFER_FRONT_LEFT:
150 context->target.rt = context->screen->frontBuffer;
151 break;
152 case BUFFER_BACK_LEFT:
153 context->target.rt = context->screen->backBuffer;
154 break;
155 default:
156 memset (&context->target.rt, sizeof(context->target.rt), 0);
157 }
158 #endif /* to be enabled */
159 }
160
161 static void r700FetchStateParameter(GLcontext * ctx,
162 const gl_state_index state[STATE_LENGTH],
163 GLfloat * value)
164 {
165 context_t *context = R700_CONTEXT(ctx);
166
167 /* TODO */
168 }
169
170 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
171 {
172 struct r700_fragment_program *fp;
173 struct gl_program_parameter_list *paramList;
174 GLuint i;
175
176 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
177 return;
178
179 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
180 if (!fp)
181 {
182 return;
183 }
184
185 paramList = fp->mesa_program.Base.Parameters;
186
187 if (!paramList)
188 {
189 return;
190 }
191
192 for (i = 0; i < paramList->NumParameters; i++)
193 {
194 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
195 {
196 r700FetchStateParameter(ctx,
197 paramList->Parameters[i].
198 StateIndexes,
199 paramList->ParameterValues[i]);
200 }
201 }
202 }
203
204 /**
205 * Called by Mesa after an internal state update.
206 */
207 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
208 {
209 context_t *context = R700_CONTEXT(ctx);
210
211 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
212
213 _swrast_InvalidateState(ctx, new_state);
214 _swsetup_InvalidateState(ctx, new_state);
215 _vbo_InvalidateState(ctx, new_state);
216 _tnl_InvalidateState(ctx, new_state);
217 _ae_invalidate_state(ctx, new_state);
218
219 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
220 {
221 _mesa_update_framebuffer(ctx);
222 /* this updates the DrawBuffer's Width/Height if it's a FBO */
223 _mesa_update_draw_buffer_bounds(ctx);
224
225 r700UpdateDrawBuffer(ctx);
226 }
227
228 r700UpdateStateParameters(ctx, new_state);
229
230 if(GL_TRUE == r700->bEnablePerspective)
231 {
232 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
233 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
234 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
235
236 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
237
238 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
239 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
240 }
241 else
242 {
243 /* For orthogonal case. */
244 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
245 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
246
247 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
248
249 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
250 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
251 }
252
253 context->radeon.NewGLState |= new_state;
254 }
255
256 static void r700SetDepthState(GLcontext * ctx)
257 {
258 context_t *context = R700_CONTEXT(ctx);
259
260 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
261
262 if (ctx->Depth.Test)
263 {
264 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
265 if (ctx->Depth.Mask)
266 {
267 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
268 }
269 else
270 {
271 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
272 }
273
274 switch (ctx->Depth.Func)
275 {
276 case GL_NEVER:
277 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
278 ZFUNC_shift, ZFUNC_mask);
279 break;
280 case GL_LESS:
281 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
282 ZFUNC_shift, ZFUNC_mask);
283 break;
284 case GL_EQUAL:
285 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
286 ZFUNC_shift, ZFUNC_mask);
287 break;
288 case GL_LEQUAL:
289 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
290 ZFUNC_shift, ZFUNC_mask);
291 break;
292 case GL_GREATER:
293 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
294 ZFUNC_shift, ZFUNC_mask);
295 break;
296 case GL_NOTEQUAL:
297 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
298 ZFUNC_shift, ZFUNC_mask);
299 break;
300 case GL_GEQUAL:
301 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
302 ZFUNC_shift, ZFUNC_mask);
303 break;
304 case GL_ALWAYS:
305 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
306 ZFUNC_shift, ZFUNC_mask);
307 break;
308 default:
309 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
310 ZFUNC_shift, ZFUNC_mask);
311 break;
312 }
313 }
314 else
315 {
316 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
317 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
318 }
319 }
320
321 static void r700SetAlphaState(GLcontext * ctx)
322 {
323 context_t *context = R700_CONTEXT(ctx);
324 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
325 uint32_t alpha_func = REF_ALWAYS;
326 GLboolean really_enabled = ctx->Color.AlphaEnabled;
327
328 switch (ctx->Color.AlphaFunc) {
329 case GL_NEVER:
330 alpha_func = REF_NEVER;
331 break;
332 case GL_LESS:
333 alpha_func = REF_LESS;
334 break;
335 case GL_EQUAL:
336 alpha_func = REF_EQUAL;
337 break;
338 case GL_LEQUAL:
339 alpha_func = REF_LEQUAL;
340 break;
341 case GL_GREATER:
342 alpha_func = REF_GREATER;
343 break;
344 case GL_NOTEQUAL:
345 alpha_func = REF_NOTEQUAL;
346 break;
347 case GL_GEQUAL:
348 alpha_func = REF_GEQUAL;
349 break;
350 case GL_ALWAYS:
351 /*alpha_func = REF_ALWAYS; */
352 really_enabled = GL_FALSE;
353 break;
354 }
355
356 if (really_enabled) {
357 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
358 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
359 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
360 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
361 } else {
362 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
363 }
364
365 }
366
367 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
368 {
369 (void)func;
370 (void)ref;
371 r700SetAlphaState(ctx);
372 }
373
374
375 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
376 {
377 context_t *context = R700_CONTEXT(ctx);
378 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
379
380 r700->CB_BLEND_RED.f32All = cf[0];
381 r700->CB_BLEND_GREEN.f32All = cf[1];
382 r700->CB_BLEND_BLUE.f32All = cf[2];
383 r700->CB_BLEND_ALPHA.f32All = cf[3];
384 }
385
386 static int blend_factor(GLenum factor, GLboolean is_src)
387 {
388 switch (factor) {
389 case GL_ZERO:
390 return BLEND_ZERO;
391 break;
392 case GL_ONE:
393 return BLEND_ONE;
394 break;
395 case GL_DST_COLOR:
396 return BLEND_DST_COLOR;
397 break;
398 case GL_ONE_MINUS_DST_COLOR:
399 return BLEND_ONE_MINUS_DST_COLOR;
400 break;
401 case GL_SRC_COLOR:
402 return BLEND_SRC_COLOR;
403 break;
404 case GL_ONE_MINUS_SRC_COLOR:
405 return BLEND_ONE_MINUS_SRC_COLOR;
406 break;
407 case GL_SRC_ALPHA:
408 return BLEND_SRC_ALPHA;
409 break;
410 case GL_ONE_MINUS_SRC_ALPHA:
411 return BLEND_ONE_MINUS_SRC_ALPHA;
412 break;
413 case GL_DST_ALPHA:
414 return BLEND_DST_ALPHA;
415 break;
416 case GL_ONE_MINUS_DST_ALPHA:
417 return BLEND_ONE_MINUS_DST_ALPHA;
418 break;
419 case GL_SRC_ALPHA_SATURATE:
420 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
421 break;
422 case GL_CONSTANT_COLOR:
423 return BLEND_CONSTANT_COLOR;
424 break;
425 case GL_ONE_MINUS_CONSTANT_COLOR:
426 return BLEND_ONE_MINUS_CONSTANT_COLOR;
427 break;
428 case GL_CONSTANT_ALPHA:
429 return BLEND_CONSTANT_ALPHA;
430 break;
431 case GL_ONE_MINUS_CONSTANT_ALPHA:
432 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
433 break;
434 default:
435 fprintf(stderr, "unknown blend factor %x\n", factor);
436 return (is_src) ? BLEND_ONE : BLEND_ZERO;
437 break;
438 }
439 }
440
441 static void r700SetBlendState(GLcontext * ctx)
442 {
443 context_t *context = R700_CONTEXT(ctx);
444 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
445 int id = 0;
446 uint32_t blend_reg = 0, eqn, eqnA;
447
448 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
449 SETfield(blend_reg,
450 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
451 SETfield(blend_reg,
452 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
453 SETfield(blend_reg,
454 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
455 SETfield(blend_reg,
456 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
457 SETfield(blend_reg,
458 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
459 SETfield(blend_reg,
460 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
461 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
462 r700->CB_BLEND_CONTROL.u32All = blend_reg;
463 else
464 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
465 return;
466 }
467
468 SETfield(blend_reg,
469 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
470 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
471 SETfield(blend_reg,
472 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
473 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
474
475 switch (ctx->Color.BlendEquationRGB) {
476 case GL_FUNC_ADD:
477 eqn = COMB_DST_PLUS_SRC;
478 break;
479 case GL_FUNC_SUBTRACT:
480 eqn = COMB_SRC_MINUS_DST;
481 break;
482 case GL_FUNC_REVERSE_SUBTRACT:
483 eqn = COMB_DST_MINUS_SRC;
484 break;
485 case GL_MIN:
486 eqn = COMB_MIN_DST_SRC;
487 SETfield(blend_reg,
488 BLEND_ONE,
489 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
490 SETfield(blend_reg,
491 BLEND_ONE,
492 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
493 break;
494 case GL_MAX:
495 eqn = COMB_MAX_DST_SRC;
496 SETfield(blend_reg,
497 BLEND_ONE,
498 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
499 SETfield(blend_reg,
500 BLEND_ONE,
501 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
502 break;
503
504 default:
505 fprintf(stderr,
506 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
507 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
508 return;
509 }
510 SETfield(blend_reg,
511 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
512
513 SETfield(blend_reg,
514 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
515 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
516 SETfield(blend_reg,
517 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
518 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
519
520 switch (ctx->Color.BlendEquationA) {
521 case GL_FUNC_ADD:
522 eqnA = COMB_DST_PLUS_SRC;
523 break;
524 case GL_FUNC_SUBTRACT:
525 eqnA = COMB_SRC_MINUS_DST;
526 break;
527 case GL_FUNC_REVERSE_SUBTRACT:
528 eqnA = COMB_DST_MINUS_SRC;
529 break;
530 case GL_MIN:
531 eqnA = COMB_MIN_DST_SRC;
532 SETfield(blend_reg,
533 BLEND_ONE,
534 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
535 SETfield(blend_reg,
536 BLEND_ONE,
537 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
538 break;
539 case GL_MAX:
540 eqnA = COMB_MAX_DST_SRC;
541 SETfield(blend_reg,
542 BLEND_ONE,
543 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
544 SETfield(blend_reg,
545 BLEND_ONE,
546 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
547 break;
548 default:
549 fprintf(stderr,
550 "[%s:%u] Invalid A blend equation (0x%04x).\n",
551 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
552 return;
553 }
554
555 SETfield(blend_reg,
556 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
557
558 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
559
560 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
561 r700->CB_BLEND_CONTROL.u32All = blend_reg;
562 else {
563 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
564 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
565 }
566 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
567 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
568
569 }
570
571 static void r700BlendEquationSeparate(GLcontext * ctx,
572 GLenum modeRGB, GLenum modeA) //-----------------
573 {
574 r700SetBlendState(ctx);
575 }
576
577 static void r700BlendFuncSeparate(GLcontext * ctx,
578 GLenum sfactorRGB, GLenum dfactorRGB,
579 GLenum sfactorA, GLenum dfactorA) //------------------------
580 {
581 r700SetBlendState(ctx);
582 }
583
584 /**
585 * Translate LogicOp enums into hardware representation.
586 * Both use a very logical bit-wise layout, but unfortunately the order
587 * of bits is reversed.
588 */
589 static GLuint translate_logicop(GLenum logicop)
590 {
591 GLuint bits = logicop - GL_CLEAR;
592 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
593 return bits;
594 }
595
596 /**
597 * Used internally to update the r300->hw hardware state to match the
598 * current OpenGL state.
599 */
600 static void r700SetLogicOpState(GLcontext *ctx)
601 {
602 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
603
604 if (RGBA_LOGICOP_ENABLED(ctx))
605 SETfield(r700->CB_COLOR_CONTROL.u32All,
606 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
607 else
608 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
609 }
610
611 /**
612 * Called by Mesa when an application program changes the LogicOp state
613 * via glLogicOp.
614 */
615 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
616 {
617 if (RGBA_LOGICOP_ENABLED(ctx))
618 r700SetLogicOpState(ctx);
619 }
620
621 static void r700UpdateCulling(GLcontext * ctx)
622 {
623 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
624
625 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
626 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
627 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
628
629 if (ctx->Polygon.CullFlag)
630 {
631 switch (ctx->Polygon.CullFaceMode)
632 {
633 case GL_FRONT:
634 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
635 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
636 break;
637 case GL_BACK:
638 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
639 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
640 break;
641 case GL_FRONT_AND_BACK:
642 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
643 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
644 break;
645 default:
646 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
647 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
648 break;
649 }
650 }
651
652 switch (ctx->Polygon.FrontFace)
653 {
654 case GL_CW:
655 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
656 break;
657 case GL_CCW:
658 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
659 break;
660 default:
661 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
662 break;
663 }
664 }
665
666 static void r700UpdateLineStipple(GLcontext * ctx)
667 {
668 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
669 if (ctx->Line.StippleFlag)
670 {
671 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
672 }
673 else
674 {
675 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
676 }
677 }
678
679 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
680 {
681 context_t *context = R700_CONTEXT(ctx);
682
683 switch (cap) {
684 case GL_TEXTURE_1D:
685 case GL_TEXTURE_2D:
686 case GL_TEXTURE_3D:
687 /* empty */
688 break;
689 case GL_FOG:
690 /* empty */
691 break;
692 case GL_ALPHA_TEST:
693 r700SetAlphaState(ctx);
694 break;
695 case GL_COLOR_LOGIC_OP:
696 r700SetLogicOpState(ctx);
697 /* fall-through, because logic op overrides blending */
698 case GL_BLEND:
699 r700SetBlendState(ctx);
700 break;
701 case GL_CLIP_PLANE0:
702 case GL_CLIP_PLANE1:
703 case GL_CLIP_PLANE2:
704 case GL_CLIP_PLANE3:
705 case GL_CLIP_PLANE4:
706 case GL_CLIP_PLANE5:
707 r700SetClipPlaneState(ctx, cap, state);
708 break;
709 case GL_DEPTH_TEST:
710 r700SetDepthState(ctx);
711 break;
712 case GL_STENCIL_TEST:
713 //r700SetStencilState(ctx, state);
714 break;
715 case GL_CULL_FACE:
716 r700UpdateCulling(ctx);
717 break;
718 case GL_POLYGON_OFFSET_POINT:
719 case GL_POLYGON_OFFSET_LINE:
720 case GL_POLYGON_OFFSET_FILL:
721 r700SetPolygonOffsetState(ctx, state);
722 break;
723 case GL_SCISSOR_TEST:
724 radeon_firevertices(&context->radeon);
725 context->radeon.state.scissor.enabled = state;
726 radeonUpdateScissor(ctx);
727 break;
728 case GL_LINE_STIPPLE:
729 r700UpdateLineStipple(ctx);
730 break;
731 default:
732 break;
733 }
734
735 }
736
737 /**
738 * Handle glColorMask()
739 */
740 static void r700ColorMask(GLcontext * ctx,
741 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
742 {
743 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
744 unsigned int mask = ((r ? 1 : 0) |
745 (g ? 2 : 0) |
746 (b ? 4 : 0) |
747 (a ? 8 : 0));
748
749 if (mask != r700->CB_SHADER_MASK.u32All)
750 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
751 }
752
753 /**
754 * Change the depth testing function.
755 *
756 * \note Mesa already filters redundant calls to this function.
757 */
758 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
759 {
760 r700SetDepthState(ctx);
761 }
762
763 /**
764 * Enable/Disable depth writing.
765 *
766 * \note Mesa already filters redundant calls to this function.
767 */
768 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
769 {
770 r700SetDepthState(ctx);
771 }
772
773 /**
774 * Change the culling mode.
775 *
776 * \note Mesa already filters redundant calls to this function.
777 */
778 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
779 {
780 r700UpdateCulling(ctx);
781 }
782
783 /* =============================================================
784 * Fog
785 */
786 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
787 {
788 }
789
790 /**
791 * Change the polygon orientation.
792 *
793 * \note Mesa already filters redundant calls to this function.
794 */
795 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
796 {
797 r700UpdateCulling(ctx);
798 r700UpdatePolygonMode(ctx);
799 }
800
801 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
802 {
803 context_t *context = R700_CONTEXT(ctx);
804 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
805
806 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
807 switch (mode) {
808 case GL_FLAT:
809 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
810 break;
811 case GL_SMOOTH:
812 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
813 break;
814 default:
815 return;
816 }
817 }
818
819 /* =============================================================
820 * Point state
821 */
822 static void r700PointSize(GLcontext * ctx, GLfloat size)
823 {
824 context_t *context = R700_CONTEXT(ctx);
825 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
826
827 /* We need to clamp to user defined range here, because
828 * the HW clamping happens only for per vertex point size. */
829 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
830
831 /* same size limits for AA, non-AA points */
832 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
833
834 /* format is 12.4 fixed point */
835 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
836 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
837 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
838 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
839
840 }
841
842 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
843 {
844 context_t *context = R700_CONTEXT(ctx);
845 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
846
847 /* format is 12.4 fixed point */
848 switch (pname) {
849 case GL_POINT_SIZE_MIN:
850 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
851 MIN_SIZE_shift, MIN_SIZE_mask);
852 break;
853 case GL_POINT_SIZE_MAX:
854 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
855 MAX_SIZE_shift, MAX_SIZE_mask);
856 break;
857 case GL_POINT_DISTANCE_ATTENUATION:
858 break;
859 case GL_POINT_FADE_THRESHOLD_SIZE:
860 break;
861 default:
862 break;
863 }
864 }
865
866 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
867 GLenum func, GLint ref, GLuint mask) //---------------------
868 {
869 }
870
871
872 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
873 {
874 }
875
876 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
877 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
878 {
879 }
880
881 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
882 {
883
884 context_t *context = R700_CONTEXT(ctx);
885 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
886 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
887 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
888 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
889 const GLfloat *v = ctx->Viewport._WindowMap.m;
890 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
891 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
892 GLfloat y_scale, y_bias;
893
894 if (render_to_fbo) {
895 y_scale = 1.0;
896 y_bias = 0;
897 } else {
898 y_scale = -1.0;
899 y_bias = yoffset;
900 }
901
902 GLfloat sx = v[MAT_SX];
903 GLfloat tx = v[MAT_TX] + xoffset;
904 GLfloat sy = v[MAT_SY] * y_scale;
905 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
906 GLfloat sz = v[MAT_SZ] * depthScale;
907 GLfloat tz = v[MAT_TZ] * depthScale;
908
909 /* TODO : Need DMA flush as well. */
910
911 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
912 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
913
914 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
915 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
916
917 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
918 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
919
920 r700->viewport[id].enabled = GL_TRUE;
921
922 r700SetScissor(context);
923 }
924
925
926 static void r700Viewport(GLcontext * ctx,
927 GLint x,
928 GLint y,
929 GLsizei width,
930 GLsizei height) //--------------------
931 {
932 r700UpdateWindow(ctx, 0);
933
934 radeon_viewport(ctx, x, y, width, height);
935 }
936
937 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
938 {
939 r700UpdateWindow(ctx, 0);
940 }
941
942 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
943 {
944 context_t *context = R700_CONTEXT(ctx);
945 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
946 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
947 if (lineWidth > 0xFFFF)
948 lineWidth = 0xFFFF;
949 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
950 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
951 }
952
953 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
954 {
955 context_t *context = R700_CONTEXT(ctx);
956 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
957
958 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
959 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
960 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
961 }
962
963 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
964 {
965 context_t *context = R700_CONTEXT(ctx);
966 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
967
968 if (state) {
969 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
970 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
971 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
972 } else {
973 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
974 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
975 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
976 }
977 }
978
979 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
980 {
981 context_t *context = R700_CONTEXT(ctx);
982 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
983 GLfloat constant = units;
984
985 switch (ctx->Visual.depthBits) {
986 case 16:
987 constant *= 4.0;
988 break;
989 case 24:
990 constant *= 2.0;
991 break;
992 }
993
994 factor *= 12.0;
995
996 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
997 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
998 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
999 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1000 }
1001
1002 static void r700UpdatePolygonMode(GLcontext * ctx)
1003 {
1004 context_t *context = R700_CONTEXT(ctx);
1005 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1006
1007 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1008
1009 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1010 if (ctx->Polygon.FrontMode != GL_FILL ||
1011 ctx->Polygon.BackMode != GL_FILL) {
1012 GLenum f, b;
1013
1014 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1015 * correctly by selecting the correct front and back face
1016 */
1017 if (ctx->Polygon.FrontFace == GL_CCW) {
1018 f = ctx->Polygon.FrontMode;
1019 b = ctx->Polygon.BackMode;
1020 } else {
1021 f = ctx->Polygon.BackMode;
1022 b = ctx->Polygon.FrontMode;
1023 }
1024
1025 /* Enable polygon mode */
1026 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1027
1028 switch (f) {
1029 case GL_LINE:
1030 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1031 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1032 break;
1033 case GL_POINT:
1034 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1035 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1036 break;
1037 case GL_FILL:
1038 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1039 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1040 break;
1041 }
1042
1043 switch (b) {
1044 case GL_LINE:
1045 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1046 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1047 break;
1048 case GL_POINT:
1049 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1050 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1051 break;
1052 case GL_FILL:
1053 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1054 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1055 break;
1056 }
1057 }
1058 }
1059
1060 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1061 {
1062 (void)face;
1063 (void)mode;
1064
1065 r700UpdatePolygonMode(ctx);
1066 }
1067
1068 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1069 {
1070 }
1071
1072 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1073 {
1074 context_t *context = R700_CONTEXT(ctx);
1075 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1076 GLint p;
1077 GLint *ip;
1078
1079 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1080 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1081
1082 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1083 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1084 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1085 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1086 }
1087
1088 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1089 {
1090 context_t *context = R700_CONTEXT(ctx);
1091 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1092 GLuint p;
1093
1094 p = cap - GL_CLIP_PLANE0;
1095 if (state) {
1096 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1097 r700->ucp[p].enabled = GL_TRUE;
1098 r700ClipPlane(ctx, cap, NULL);
1099 } else {
1100 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1101 r700->ucp[p].enabled = GL_FALSE;
1102 }
1103 }
1104
1105 void r700SetScissor(context_t *context) //---------------
1106 {
1107 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1108 unsigned x1, y1, x2, y2;
1109 int id = 0;
1110 struct radeon_renderbuffer *rrb;
1111
1112 rrb = radeon_get_colorbuffer(&context->radeon);
1113 if (!rrb || !rrb->bo) {
1114 return;
1115 }
1116 if (context->radeon.state.scissor.enabled) {
1117 x1 = context->radeon.state.scissor.rect.x1;
1118 y1 = context->radeon.state.scissor.rect.y1;
1119 x2 = context->radeon.state.scissor.rect.x2 - 1;
1120 y2 = context->radeon.state.scissor.rect.y2 - 1;
1121 } else {
1122 x1 = rrb->dPriv->x;
1123 y1 = rrb->dPriv->y;
1124 x2 = rrb->dPriv->x + rrb->dPriv->w;
1125 y2 = rrb->dPriv->y + rrb->dPriv->h;
1126 }
1127
1128 /* window */
1129 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1130 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1131 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1132 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1133 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1134
1135 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1136 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1137 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1138 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1139
1140
1141 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1142 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1143 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1144 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1145 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1146 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1147 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1148 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1149
1150 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1151 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1152 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1153 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1154 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1155 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1156
1157 /* more....2d clip */
1158 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1159 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1160 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1161 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1162 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1163 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1164 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1165 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1166 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1167
1168 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1169 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1170 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1171 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1172 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1173 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1174 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1175 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1176 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1177
1178 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1179 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1180 r700->viewport[id].enabled = GL_TRUE;
1181 }
1182
1183 void r700SetRenderTarget(context_t *context, int id)
1184 {
1185 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1186
1187 struct radeon_renderbuffer *rrb;
1188 unsigned int nPitchInPixel;
1189
1190 /* screen/window/view */
1191 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1192
1193 rrb = radeon_get_colorbuffer(&context->radeon);
1194 if (!rrb || !rrb->bo) {
1195 fprintf(stderr, "no rrb\n");
1196 return;
1197 }
1198
1199 /* color buffer */
1200 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1201
1202 nPitchInPixel = rrb->pitch/rrb->cpp;
1203 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1204 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1205 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1206 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1207 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1208 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1209 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1210 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1211 if(4 == rrb->cpp)
1212 {
1213 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1214 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1215 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1216 }
1217 else
1218 {
1219 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1220 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1221 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1222 COMP_SWAP_shift, COMP_SWAP_mask);
1223 }
1224 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1225 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1226 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1227
1228 r700->render_target[id].enabled = GL_TRUE;
1229 }
1230
1231 void r700SetDepthTarget(context_t *context)
1232 {
1233 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1234
1235 struct radeon_renderbuffer *rrb;
1236 unsigned int nPitchInPixel;
1237
1238 /* depth buf */
1239 r700->DB_DEPTH_SIZE.u32All = 0;
1240 r700->DB_DEPTH_BASE.u32All = 0;
1241 r700->DB_DEPTH_INFO.u32All = 0;
1242
1243 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1244 r700->DB_DEPTH_VIEW.u32All = 0;
1245 r700->DB_RENDER_CONTROL.u32All = 0;
1246 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1247 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1248 r700->DB_RENDER_OVERRIDE.u32All = 0;
1249 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1250 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1251 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1252 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1253 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1254
1255 r700->DB_ALPHA_TO_MASK.u32All = 0;
1256 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1257 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1258 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1259 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1260
1261 rrb = radeon_get_depthbuffer(&context->radeon);
1262 if (!rrb)
1263 return;
1264
1265 nPitchInPixel = rrb->pitch/rrb->cpp;
1266
1267 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1268 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1269 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1270 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1271
1272 if(4 == rrb->cpp)
1273 {
1274 switch (GL_CONTEXT(context)->Visual.depthBits)
1275 {
1276 case 16:
1277 case 24:
1278 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1279 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1280 break;
1281 default:
1282 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1283 GL_CONTEXT(context)->Visual.depthBits);
1284 _mesa_exit(-1);
1285 }
1286 }
1287 else
1288 {
1289 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1290 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1291 }
1292 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1293 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1294 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1295 }
1296
1297 static void r700InitSQConfig(GLcontext * ctx)
1298 {
1299 context_t *context = R700_CONTEXT(ctx);
1300 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1301 int ps_prio;
1302 int vs_prio;
1303 int gs_prio;
1304 int es_prio;
1305 int num_ps_gprs;
1306 int num_vs_gprs;
1307 int num_gs_gprs;
1308 int num_es_gprs;
1309 int num_temp_gprs;
1310 int num_ps_threads;
1311 int num_vs_threads;
1312 int num_gs_threads;
1313 int num_es_threads;
1314 int num_ps_stack_entries;
1315 int num_vs_stack_entries;
1316 int num_gs_stack_entries;
1317 int num_es_stack_entries;
1318
1319 // SQ
1320 ps_prio = 0;
1321 vs_prio = 1;
1322 gs_prio = 2;
1323 es_prio = 3;
1324 switch (context->radeon.radeonScreen->chip_family) {
1325 case CHIP_FAMILY_R600:
1326 num_ps_gprs = 192;
1327 num_vs_gprs = 56;
1328 num_temp_gprs = 4;
1329 num_gs_gprs = 0;
1330 num_es_gprs = 0;
1331 num_ps_threads = 136;
1332 num_vs_threads = 48;
1333 num_gs_threads = 4;
1334 num_es_threads = 4;
1335 num_ps_stack_entries = 128;
1336 num_vs_stack_entries = 128;
1337 num_gs_stack_entries = 0;
1338 num_es_stack_entries = 0;
1339 break;
1340 case CHIP_FAMILY_RV630:
1341 case CHIP_FAMILY_RV635:
1342 num_ps_gprs = 84;
1343 num_vs_gprs = 36;
1344 num_temp_gprs = 4;
1345 num_gs_gprs = 0;
1346 num_es_gprs = 0;
1347 num_ps_threads = 144;
1348 num_vs_threads = 40;
1349 num_gs_threads = 4;
1350 num_es_threads = 4;
1351 num_ps_stack_entries = 40;
1352 num_vs_stack_entries = 40;
1353 num_gs_stack_entries = 32;
1354 num_es_stack_entries = 16;
1355 break;
1356 case CHIP_FAMILY_RV610:
1357 case CHIP_FAMILY_RV620:
1358 case CHIP_FAMILY_RS780:
1359 default:
1360 num_ps_gprs = 84;
1361 num_vs_gprs = 36;
1362 num_temp_gprs = 4;
1363 num_gs_gprs = 0;
1364 num_es_gprs = 0;
1365 num_ps_threads = 136;
1366 num_vs_threads = 48;
1367 num_gs_threads = 4;
1368 num_es_threads = 4;
1369 num_ps_stack_entries = 40;
1370 num_vs_stack_entries = 40;
1371 num_gs_stack_entries = 32;
1372 num_es_stack_entries = 16;
1373 break;
1374 case CHIP_FAMILY_RV670:
1375 num_ps_gprs = 144;
1376 num_vs_gprs = 40;
1377 num_temp_gprs = 4;
1378 num_gs_gprs = 0;
1379 num_es_gprs = 0;
1380 num_ps_threads = 136;
1381 num_vs_threads = 48;
1382 num_gs_threads = 4;
1383 num_es_threads = 4;
1384 num_ps_stack_entries = 40;
1385 num_vs_stack_entries = 40;
1386 num_gs_stack_entries = 32;
1387 num_es_stack_entries = 16;
1388 break;
1389 case CHIP_FAMILY_RV770:
1390 num_ps_gprs = 192;
1391 num_vs_gprs = 56;
1392 num_temp_gprs = 4;
1393 num_gs_gprs = 0;
1394 num_es_gprs = 0;
1395 num_ps_threads = 188;
1396 num_vs_threads = 60;
1397 num_gs_threads = 0;
1398 num_es_threads = 0;
1399 num_ps_stack_entries = 256;
1400 num_vs_stack_entries = 256;
1401 num_gs_stack_entries = 0;
1402 num_es_stack_entries = 0;
1403 break;
1404 case CHIP_FAMILY_RV730:
1405 case CHIP_FAMILY_RV740:
1406 num_ps_gprs = 84;
1407 num_vs_gprs = 36;
1408 num_temp_gprs = 4;
1409 num_gs_gprs = 0;
1410 num_es_gprs = 0;
1411 num_ps_threads = 188;
1412 num_vs_threads = 60;
1413 num_gs_threads = 0;
1414 num_es_threads = 0;
1415 num_ps_stack_entries = 128;
1416 num_vs_stack_entries = 128;
1417 num_gs_stack_entries = 0;
1418 num_es_stack_entries = 0;
1419 break;
1420 case CHIP_FAMILY_RV710:
1421 num_ps_gprs = 192;
1422 num_vs_gprs = 56;
1423 num_temp_gprs = 4;
1424 num_gs_gprs = 0;
1425 num_es_gprs = 0;
1426 num_ps_threads = 144;
1427 num_vs_threads = 48;
1428 num_gs_threads = 0;
1429 num_es_threads = 0;
1430 num_ps_stack_entries = 128;
1431 num_vs_stack_entries = 128;
1432 num_gs_stack_entries = 0;
1433 num_es_stack_entries = 0;
1434 break;
1435 }
1436
1437 r700->sq_config.SQ_CONFIG.u32All = 0;
1438 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1439 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1440 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1441 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1442 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1443 else
1444 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1445 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1446 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1447 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1448 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1449 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1450 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1451
1452 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1453 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1454 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1455 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1456 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1457
1458 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1459 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1460 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1461
1462 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1463 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1464 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1465 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1466 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1467 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1468 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1469 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1470 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1471
1472 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1473 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1474 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1475 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1476 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1477
1478 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1479 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1480 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1481 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1482 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1483
1484 }
1485
1486 /**
1487 * Calculate initial hardware state and register state functions.
1488 * Assumes that the command buffer and state atoms have been
1489 * initialized already.
1490 */
1491 void r700InitState(GLcontext * ctx) //-------------------
1492 {
1493 context_t *context = R700_CONTEXT(ctx);
1494
1495 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1496
1497 r700->TA_CNTL_AUX.u32All = 0;
1498 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1499 r700->VC_ENHANCE.u32All = 0;
1500 r700->DB_WATERMARKS.u32All = 0;
1501 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1502 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1503 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1504 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1505 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1506 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1507 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1508 r700->DB_DEBUG.u32All = 0x82000000;
1509 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1510 } else {
1511 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1512 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1513 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1514 }
1515
1516 /* Turn off vgt reuse */
1517 r700->VGT_REUSE_OFF.u32All = 0;
1518 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1519
1520 /* Specify offsetting and clamp values for vertices */
1521 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1522 r700->VGT_MIN_VTX_INDX.u32All = 0;
1523 r700->VGT_INDX_OFFSET.u32All = 0;
1524
1525 /* Specify the number of instances */
1526 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
1527
1528 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1529
1530 /* default shader connections. */
1531 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1532 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1533
1534 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
1535 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
1536 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
1537
1538 r700->SPI_THREAD_GROUPING.u32All = 0;
1539 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1540 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1541
1542 r700SetBlendState(ctx);
1543 r700SetLogicOpState(ctx);
1544
1545 r700->DB_SHADER_CONTROL.u32All = 0;
1546 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1547
1548 /* screen */
1549 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1550
1551 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1552 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1553 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1554 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1555 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1556 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1557
1558 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1559 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1560 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1561
1562 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1563 r700->PA_SC_EDGERULE.u32All = 0;
1564 else
1565 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1566
1567 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1568 r700->PA_SC_MODE_CNTL.u32All = 0;
1569 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1570 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1571 } else {
1572 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1573 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1574 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1575 }
1576
1577 /* Do scale XY and Z by 1/W0. */
1578 r700->bEnablePerspective = GL_TRUE;
1579 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1580 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1581 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1582
1583 /* Enable viewport scaling for all three axis */
1584 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1585 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1586 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1587 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1588 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1589 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1590
1591 /* Set up point sizes and min/max values */
1592 r700PointSize(ctx, 1.0);
1593
1594 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1595 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1596
1597 /* GL uses last vtx for flat shading components */
1598 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1599
1600 /* Set up line control */
1601 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
1602 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1603
1604 r700->PA_SC_LINE_CNTL.u32All = 0;
1605 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1606 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1607
1608 /* Set up vertex control */
1609 r700->PA_SU_VTX_CNTL.u32All = 0;
1610 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1611 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1612 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1613 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1614
1615 /* to 1.0 = no guard band */
1616 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1617 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1618 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1619 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1620
1621 /* CB */
1622 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1623 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1624 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1625 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1626 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1627 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1628 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1629
1630 /* Disable color compares */
1631 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1632 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1633 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1634 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1635 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1636 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1637
1638 /* Zero out source */
1639 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1640
1641 /* Put a compare color in for error checking */
1642 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1643
1644 /* Set up color compare mask */
1645 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1646
1647 /* default color mask */
1648 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
1649
1650 /* Enable all samples for multi-sample anti-aliasing */
1651 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1652 /* Turn off AA */
1653 r700->PA_SC_AA_CONFIG.u32All = 0;
1654
1655 r700->SX_MISC.u32All = 0;
1656
1657 r700InitSQConfig(ctx);
1658 }
1659
1660 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1661 {
1662 functions->UpdateState = r700InvalidateState;
1663 functions->AlphaFunc = r700AlphaFunc;
1664 functions->BlendColor = r700BlendColor;
1665 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1666 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1667 functions->Enable = r700Enable;
1668 functions->ColorMask = r700ColorMask;
1669 functions->DepthFunc = r700DepthFunc;
1670 functions->DepthMask = r700DepthMask;
1671 functions->CullFace = r700CullFace;
1672 functions->Fogfv = r700Fogfv;
1673 functions->FrontFace = r700FrontFace;
1674 functions->ShadeModel = r700ShadeModel;
1675 functions->LogicOpcode = r700LogicOpcode;
1676
1677 /* ARB_point_parameters */
1678 functions->PointParameterfv = r700PointParameter;
1679
1680 /* Stencil related */
1681 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1682 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1683 functions->StencilOpSeparate = r700StencilOpSeparate;
1684
1685 /* Viewport related */
1686 functions->Viewport = r700Viewport;
1687 functions->DepthRange = r700DepthRange;
1688 functions->PointSize = r700PointSize;
1689 functions->LineWidth = r700LineWidth;
1690 functions->LineStipple = r700LineStipple;
1691
1692 functions->PolygonOffset = r700PolygonOffset;
1693 functions->PolygonMode = r700PolygonMode;
1694
1695 functions->RenderMode = r700RenderMode;
1696
1697 functions->ClipPlane = r700ClipPlane;
1698
1699 functions->Scissor = radeonScissor;
1700
1701 functions->DrawBuffer = radeonDrawBuffer;
1702 functions->ReadBuffer = radeonReadBuffer;
1703
1704 }
1705